Claims
- 1. A semiconductor memory comprising:a first memory array having a plurality of first bit lines extending in a first direction, a plurality of first word lines and a plurality of first dynamic memory cells; a second memory array having a plurality of second bit lines extending in said first direction, a plurality of second word lines and a plurality of second dynamic memory cells; and a plurality of sense amplifiers formed in an area between said first memory array and said second memory array, wherein each of said plurality of sense amplifiers has a pair of input terminals connected to one of said first bit lines and one of said second bit lines, wherein each length of said second bit lines is shorter than each length of said first bit lines, and wherein said second memory array is used as a redundant memory array.
- 2. A semiconductor memory according to claim 1,wherein another second bit line is connected to said one of said second bit lines, and wherein two of said second dynamic memory cells are connected to one of said pair of input terminals when one of said second word lines is selected.
Priority Claims (1)
Number |
Date |
Country |
Kind |
11-314225 |
Nov 1999 |
JP |
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Parent Case Info
This is a continuation of application Ser. No 10/084,514 filed Feb. 28, 2002(now U.S. Pat. No. 6,545,897,) which is a continuation of application Ser. No. 09/805,167, filed Mar. 14, 2001 (now U.S. Pat. No. 6,373,776) which is a divisional of application Ser. No. 09/705,837, filed Nov. 6, 2000 (now U.S. Pat. No. 6,370,054), the entire disclosures of which are hereby incorporated by reference.
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Mar 1999 |
A |
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Continuations (2)
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Number |
Date |
Country |
Parent |
10/084514 |
Feb 2002 |
US |
Child |
10/361642 |
|
US |
Parent |
09/805167 |
Mar 2001 |
US |
Child |
10/084514 |
|
US |