Patent Application
20090073786
The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to an early write (EW) with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM.
Early write techniques have previously been described in conjunction with DRAM devices to improve memory cell restore times and overall write cycle times. An early write operation generally consists of writing new data to the bitlines before the column sense amplifiers have been activated. This results in faster memory cell voltage restore times since non-early writes, or traditional DRAM writes, occur after the sense amplifier has been activated. This traditional, or late, DRAM write is slower to restore cell node voltage levels since the sense amplifier starts to amplify old data, then needs to be overpowered by the write circuitry, whereupon new data is restored into the memory cell.
A problem with conventional early write designs is that they are unable to mask data in a traditional way. Data masking during a write operation is employed when a data stream is directed to a memory cell array but it is also desired that certain data already stored in the array remain unchanged. In operation, a data mask is then utilized to block some of the data from reaching these specific memory locations.
Late write designs can mask data by bit, byte or word by holding the internal data lines at a double high (data “D” and data complement “/D” pair) which prevents the sense amplifier from flipping and new data being written. However as previously mentioned, none of the known circuits and methods for implementing early write operations allow for industry standard data masking.
U.S. Pat. No. 6,504,766 issued Jan. 7, 2003 for: “System and Method for Early Write to Memory by Injecting Small Voltage Signal” describes a technique implemented through the injection of a small voltage differential signal prior to setting a sense amplifier and thereafter setting the sense amplifier to amplify the small voltage signal to predetermined high and low voltage logic levels for writing to the memory cell. This small signal is injected after the wordline goes “high” but before the latch p-channel bar (LPB) and latch n-channel bar (LNB) nodes fire.
U.S. Pat. No. 6,788,591 issued Sep. 7, 2004 for: “System and Method for Direct Write to Dynamic Random Access Memory (DRAM) using PFET Bit-Switch” describes a technique wherein a write operation to a selected cell is commenced prior to the completion of the time associated with signal development on the true/complementary bitlines of the memory array. The technique described, while effectuating writes before the wordlines go “high” does not accomplish, or allow for, data masking and creates disturbs while consuming more power since the bitlines and local write lines transition to full power supply (VCC) levels.
Disclosed herein is an early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early writes to DRAM arrays with direct bit, byte or word data masking capability.
Particularly disclosed herein is a technique for writing data to a memory array having at least one pair of complementary bitlines, at least one pair of complementary data lines and at least one wordline, with the memory array further comprising associated column write clock and sense amplifier enable signals. The technique comprises the steps of: asserting the column write clock; writing data to the complementary bitlines; applying a predetermined signal level to the complementary data lines; activating the wordline and activating the sense amplifier enable signal.
In a particular implementation of the technique of the present invention, the technique further comprises the step of: maintaining a same voltage on the complementary data lines to mask certain of the data to be written to the complementary bitlines.
The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:
With reference now to
As illustrated, the pertinent inputs to the circuit 100 also include the shorting clock signal (φSH), the column write clock (Yw), the wordline (WL), the complementary internal data lines (D, /D), the complementary bitlines (BL, /BL) and the sense amplifier enable signal (SAE).
By way of background, in a conventional read operation, first the shorting clock signal transitions from a logic “low” to logic “high” and back followed by the assertion of the wordline which couples the associated memory cells to their respective bitlines. The sense amplifier enable signal is then asserted in conjunction with the column read clock to read the stored data from the selected column of memory cells. The complementary data lines are shorted together to VCC/2 (one half the supply voltage) for a portion of the read cycle in order to precharge the data lines in preparation of transferring signal from the sense amplifier. This read cycle is described for purposes of comparison only and is generally representative of a read operation whether or not used in conjunction with a conventional early (or late) write operation or the technique of the present invention.
With reference additionally now to
In this example, the shorting clock signal transitions from a logic “low” to logic “high” and back followed by the assertion of the wordline which again couples the associated memory cells to their respective bitlines. The column write clock then transitions and the sense amplifier enable signal is asserted to write the input data to the selected column of memory cells. It should be noted that with this timing, its is not possible to short the complementary data lines D and /D to VCC/2 to mask data because, in so doing, such a masking operation would also short out actual memory cell data causing that data to be corrupted or lost.
With reference additionally now to
With reference additionally now to
At this point, a small signal level is used on the complementary data lines D and /D to minimize any possible disturbance to surrounding bitlines. However, it is sufficiently large to maintain this data after the wordline goes “high” and old, opposite, data comes out of the memory cell. In operation, there is still enough of the new signal to sense when the sense amplifier enable signal goes “high”. The data masking (DM) signal is at VSS or 0 volts for the entire operation.
With reference additionally now to
While there have been described above the principles of the present invention in conjunction with specific operational characteristics, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
As used herein, the terms “comprises”, “comprising”, or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a recitation of certain elements does not necessarily include only those elements but may include other elements not expressly recited or inherent to such process, method, article or apparatus. None of the description in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope and THE SCOPE OF THE PATENTED SUBJECT MATTER IS DEFINED ONLY BY THE CLAIMS AS ALLOWED. Moreover, none of the appended claims are intended to invoke paragraph six of 35 U.S.C. Sect. 112 unless the exact phrase “means for” is employed and is followed by a participle.
