Claims
- 1. A system for testing integrated circuit devices, comprising:
a tester; a known good device (KGD); a channel coupled between the tester and the KGD for data communication between the KGD and the tester; and tester-DUT interface circuitry coupled to the channel, the channel-DUT interface circuitry monitoring the channel while the tester is writing data as part of a test sequence to locations in the KGD and in response writing said data to corresponding locations in each of a plurality of devices under test (DUTs), and monitoring the channel while the tester is reading from said locations in the KGD and in response performing a comparison using DUT data from said corresponding locations in the DUTs.
- 2. The system of claim 1 wherein the tester-DUT interface circuitry generates error information regarding the results of said comparison, and wherein the tester reads the error information for each of the plurality of DUTs after completing the test sequence.
- 3. The system of claim 1 wherein the tester-DUT interface circuitry compares said DUT data with KGD data, the KGD data being obtained from said locations in the KGD through the channel.
- 4. The system of claim 1 wherein the tester-DUT interface circuitry further compares DUT timing with KGD timing, the KGD timing being obtained by monitoring the channel while the tester is writing to and reading from the KGD.
- 5. The system of claim 1 further comprising:
a plurality of probes each having one end coupled to the tester-DUT interface circuitry and another end for contacting a signal point of the plurality of DUTs on a semiconductor wafer.
- 6. The system of claim 1 further comprising
error memory coupled to the tester-DUT interface circuitry for storage of error information regarding the results of said comparison.
- 7. The system of claim 6 wherein the error memory is coupled to the channel, and the tester reads the error information by accessing the memory through the channel.
- 8. The system of claim 1 further comprising
a second channel for communicatively coupling the tester to the tester-DUT interface circuitry, and wherein the tester receives error information regarding the results of said comparison during execution of the test sequence, and prepares a list of errors for each of the DUTs based on the error information.
- 9. A circuit for testing integrated circuit devices, the circuit for being coupled to a tester through a channel and for being coupled to a plurality of devices under test (DUTs), the circuit comprising:
channel monitor means for monitoring read and write transactions in the channel; DUT access means coupled to the channel monitor means for writing to and reading from one or more of the DUTs in response to an indication from the channel monitor means; and comparator means for performing a comparison using DUT data read from the DUTs.
- 10. The circuit of claim 9 wherein the comparator means compares said DUT data with KGD data, the KGD data being obtained through the channel from locations in a KGD coupled to the channel.
- 11. A probe card for testing integrated circuit devices, the card for being coupled to a tester, the card comprising:
a channel for being coupled to the tester; a known good device (KGD) coupled to the channel; channel monitor coupled to the channel, said channel monitor monitoring the channel while the tester is writing data as part of a test sequence to locations in the KGD, and for monitoring the channel while the tester is reading from said locations in the KGD; DUT (device under test) access port coupled to the channel monitor, the DUT access port for writing to and reading from corresponding locations in at least one of the plurality of DUTs in response to an indication from the channel monitor; and a comparator coupled to the DUT access port for performing a comparison using DUT data read from said corresponding locations in the DUTs.
- 12. The probe card of claim 11 further comprising
a plurality of probes each having one end coupled to the DUT access port and another end for contacting a signal point of the plurality of DUTs.
- 13. The probe card of claim 11 wherein the comparator compares said DUT data with KGD data, the KGD data being obtained from said locations in the KGD through the channel.
- 14. A method of testing integrated circuit devices, comprising:
writing data as part of a test sequence to locations in a known good device (KGD) through a channel; monitoring the channel while writing said data, and in response writing said data to corresponding locations in each of a plurality of devices under test (DUTs); reading from said locations in the KGD through the channel; and monitoring the channel while reading from said locations, and in response performing a comparison using DUT data obtained from said corresponding locations in the DUTs.
- 15. The method of claim 14 wherein the step of performing a comparison further comprises
comparing said DUT data with KGD data obtained from said locations in the KGD obtained through the channel.
- 16. The method of claim 14 further comprising accessing only a selected one of the plurality of DUTs by writing data to and reading said data from locations in the selected one of the DUTs.
Parent Case Info
[0001] The subject matter in this application is related to material in two other U.S. patent applications of Roy and Miller, entitled DISTRIBUTED INTERFACE FOR PARALLEL TESTING OF MULTIPLE DEVICES USING A SINGLE TESTER CHANNEL, having, Ser. No. ______ (P076), and PARALLEL TESTING OF INTEGRATED CIRCUIT DEVICES USING CROSS-DUT AND WITHIN-DUT COMPARISONS, having Ser. No. ______ (P077), filed on the same date as this application and expressly incorporated herein by reference.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09260460 |
Mar 1999 |
US |
Child |
10208173 |
Jul 2002 |
US |