Patent Application
20050087447
The present invention relates to a copper plating bath, more particularly, to a copper electroplating liquid to be used for filling copper in fine openings in insulating layers by electroplating, and a process for manufacturing a semiconductor integrated device with multi-layer interconnections formed using the same.
There have been conventionally used aluminum or aluminum-copper alloys as materials for use in interconnections in semiconductor devices. As interconnections are micronised with more highly integrated LSI, the delay of signal transmission due to an increase in resistance and capacitance of the interconnections and reduced reliability due to electromigration become a problem. In order to overcome this problem, there has been proposed a method of reducing the resistance of interconnections by making them with metals having a low resistance such as gold, silver and copper. Among them, copper is expected to be a substitute for aluminum and alloys thereof.
As opposed to aluminum, copper can not produce a compound having a high vapor pressure so that it is difficult to form fine patterns by dry etching. For this reason, there has been employed a technique (called as Damascene method) where trenches and vias are first formed in insulating layers in place corresponding to the patterns of interconnections, and then they are filled with copper.
Generally all the surfaces of a substrate including features therein are metallized and then excess metals are removed to form interconnections.
More practically, when interconnections are produced, a diffusion-inhibiting layer (barrier layer) and a copper seed layer are formed on the surfaces of an insulating interlayer having trenches and vias formed therein by sputtering and then copper is filled in the trenches and vias by electroplating with a seed layer being as an electron transmitting layer. Materials to be used for the barrier layer include high melting point metals such as tantalum, tungsten and the like, and alloys thereof and nitrides such as titanium nitride, tantalum nitride and the like.
Techniques for filling the features include physical vapor deposition (PVD) such as sputtering, chemical vapor deposition (CVD), and plating. The PVD method is poor in coverage with metals on the sides of the features making their aspect ratio higher (that is, making the features thinner and deeper), which may form voids in the filled metals. The CVD method is relatively good in coverage, but it suffers from high costs of source materials. The plating is lower in cost as compared with other methods and excellent in filling property. Therefore, it has attracted much interest. Particularly electroplating is excellent in filling property, provides a high throughput, and effective to mass production. Therefore, it is most promising as a method for filling features.
For example, Japanese Patent KOKAI No. Hei 11-26394 discloses a process for filling trenches by electroplating after forming an iodine coating layer on a seed layer.
Japanese Patent KOKAI No. Hei 11-97391 discloses a process for producing interconnections by electroplating with pulse current in a plating bath without additives.
Japanese Patent KOKAI No. Hei 11-310896 discloses a process for producing interconnections in a plating bath containing little support electrolyte.
Japanese Patent Kokai No. 2000-248397 discloses a process for filling trenches by adding a polymeric surfactant, a sulfur-based saturated organic compound and an organic dye compound to a plating bath.
As described above, though various processes have been studied to fill fine features with metals by using electroplating, each of them has a problem.
The process of Japanese Patent KOKAI No. Hei 11-26394 provides conformal deposit of metal by plating. If there are irregularities on the surface of a seed layer, the deposits on the raised sites may come to contact with adjacent deposits on the sides of the features as the plating proceeds, resulting in formation of voids. Even when the plated film has an appearance of a flat surface due to iodine, seam may be formed in the central portions of the features because the surface is not perfectly plat.
In the process of Japanese Patent KOKAI No. Hei 11-97391, the use of pulse current can make a diffusion layer thinner, which may allow uniform deposits on the fine features to be expected. However, the conformal deposition by this process may generate voids similarly to those as described above. It is difficult with the plating bath containing no additives to form flat films because the films to be deposited under plating grow reproducing the irregularities on the surface of the primer seed layer.
The process of Japanese Patent KOKAI No. Hei 11-310896 increases an amount of copper diffused into fine features by significantly reducing an amount of support electrolyte in a plating bath. However, even when sufficient amount of copper is supplied, conformal depositions occur in the features, resulting in formation of voids and seams.
In the process disclosed in Japanese Patent Kokai No. 2000-248397, the organic dye compound such as Absorber Dye ADI or Cy5 is added to the plating bath so as to attain levelling function which smoothes the copper surface. Absorber Dye ADI and Cy5 comprise an anionic compound having 2 or more of sulfonic groups. Such a compound is scarecely adsorbed on the surface in the plating step. Therefore, it is hard to grow plating preferentially from the bottoms, which is accomplished by a reaction of an additive described below.
Thus, it is difficult to fill completely the features having a high aspect ratio by the conventional electroplating process as described above. The interconnections having voids and seams therein suffer from increase of wiring resistivity, delay of the transmission of electric signals and the like. Therefore, there has been a need for a technique which allows such fine features to be completely filled.
As trenches were filled with copper by a bottom-up-filling technique, i.e., a technique of facilitating copper plating on the bottom of trenches as described in the report by Mr. Reid, titled “Copper Electrodeposition for IC interconnect Formation” in Advanced Metallization Conference (ADMETA), Oct. 13, 1999, pp. 65-102, studies on its mechanism and plating baths suitable for it have been intensively made.
It is an object of the present invention to provide a copper electroplating bath suitable for filling copper in features having a high aspect ratio with high reproducibility.
It is another of the present invention to provide a copper electroplating bath suitable for filling copper in features having a high aspect ratio without generating voids and seams with high reproducibility.
It is still another of the present invention to provide a semiconductor integrated circuit device having a high interconnection density in the interconnection layers having a high electromigration resistance where fine features have been filled with copper, i.e., without existing voids and seams, using such a plating bath as above.
The present invention will be summarized under.
In the present invention, an additive is added to a copper electroplating bath, said additive suitable to allow copper plating to proceed preferentially from the bottoms of features such as trenches and vias having a high aspect ratio which have been formed on the surfaces of a substrate.
The copper electroplating bath of the present invention comprises a solution containing copper ions and electrolyte(s) with an addition of, for example, cyanine dye.
In an embodiment of the copper electroplating bath of the present invention, the solution containing copper ions and electrolyte(s) contains as an additive at least one of cyanine dyes represented by, for example, the following general formula (I):
where X− is an anion, and n is 0, 1, 2, or 3 (abbreviated as n=0 to 3 hereunder).
In another embodiment of the copper electroplating bath according to the present invention, the solution containing copper ions and electrolyte(s) is characterized by having an indolium compound added thereto.
In a preferred embodiment, the copper electroplating bath may contain at least one or more of polyethers, organic sulfur compounds and halide ions as further additives.
The process for producing a semiconductor integrated circuit devices according to the present invention comprises providing an insulating layer having openings on the top of the major surface of a semiconductor wafer which has a plurality of circuit element areas formed therein, depositing a barrier layer and a seed layer on the bottom and the side surfaces of the openings and on the top surface of the insulating layer, and filling the inside of the openings with copper without forming any voids and seams by electroplating with the copper electroplating bath as described above to from a interconnection layer. The process is capable of producing a high packing density LSI having an excellent reliability with high reproducibility.
In the drawings, each reference number designates a part as follows:
As described above, metals which may be used in filling fine features with a low resistance metal by electroplating include gold, silver and copper. These metals may diffuse into adjacent insulating layers and semiconductor layers to deteriorate characteristic properties of circuit elements. Therefore, the diffusion must be prevented by providing a barrier layer under the metal layer. Electroconductive materials which can function as barrier include metal nitrides such as titanium nitride, tungsten nitride, tantalum nitride, and high melting point metals such as tantalum and tungsten and alloys thereof. These barrier layers are also disposed sequentially to the surfaces of the insulating layers having the trenches and the vias as well as the inside of thereof.
The barrier layer which may be made of any one of metal nitrides and high melting point metals and alloys thereof has a relatively high resistance and may produce a relatively stable oxide on the surface, so that it is difficult to electroplate directly the surface of the barrier layer. For this reason, a seed layer as an electron transmitting layer, e.g., a copper film is further formed on the barrier layer using PVD, CVD, or electroless deposition process.
Next, according to the subject of the present invention, a copper is electroplated on the seed layers present even on the inner surfaces of the feature by copper electroplating to fill the inside of the feature with copper. The characteristics of the copper film are very sensitively depending upon the configuration of the seed layer and the thickness of the film.
For example, when the seed layer is discontinuous, the plating rate at the sites without any seed layer is very slow or produce no plating resulting in generation of voids. When the seed layer is not uniform in thickness or has irregularities on the surface, uniformity of the growing copper film is inhibited, that is, the thickness of copper film become not uniform during copper electroplating resulting in the formation of seams, i.e., seam like boundary in the copper film filling the inside of the feature.
The presence of such voids and seams may cause the confinement of plating bath components, air and moisture at the sites to reduce the reliability of the resulting semiconductor integrated circuit devices having highly packed fine interconnections. Therefore, the seed layer must be uniformly produced throughout the surfaces of the insulating layer and the inside of the feature. A non-negligible variation of the seed layer in the LSI having quite a lot of openings has an influence on the final proportion of good products, i.e., yield.
Even when a seed layer is formed throughout the surfaces, preferential growth of electroplated copper deposit in the openings of the feature may close off the feature. As a result, voids having plating bath remained therein are produced. When a copper grows conformally by electroplating, the plated film can not perfectly be flat so that voids and seams are inevitably formed in the central portion.
In order to fill the features with seamless copper, therefore, it is necessary to allow copper electroplating deposit to grow preferentially from the bottoms of the features. Moreover, as described above, it must be reproducibly conducted without being affected by fluctuation of the characteristics of the seed layer.
The present inventors have found that electroplating deposits can be grown preferentially from the bottoms of the features by using a specific additive with good reproducibility as described above. The additive is a material which suppresses the electroplating reaction and is consumed as the electroplating reaction proceeds. That is, the commencement of the electroplating reaction reduces the concentration of the additive on the surfaces where the reaction is taking place. If the diffusion rate of the additive is lower than the rate of the additive reaction, the diffusion of the additive controls the electroplating reaction. Therefore, an extent of the suppression of reaction depends on the amount of the additive to be supplied to the surfaces through diffusion.
For this reason, there may be a difference in the amount of the additive to be supplied through diffusion between the regions in the vicinity of the openings of the features and the bottoms of the features. The additive is smoothly supplied in the vicinity of the openings, resulting in the suppression of the electroplating reaction. On the other hand, inside the features, the additive tends to react into a material having no effect of suppressing the electroplating reaction before it reaches the bottoms, so that the amount of the additive is reduced in the bottoms. Therefore, the electroplating reaction at the bottoms is much less suppressed as compared with that around the openings. That is, less amount of the additive having an effect of suppressing the reaction is supplied to the bottoms, so that the electroplating proceeds preferentially from the bottoms.
If the additive has a very low rate of reaction, or if the rate of diffusion is very high, a sufficient amount of the additive may be supplied to the bottoms of the features. Therefore, the difference in suppression is reduced between the bottoms and the openings. If the additive has a very high rate of reaction, or if the rate of diffusion is very low, little supplement of the additive may be effected to the openings of the features. The difference in suppression is again reduced between the bottoms and the openings. Therefore, preferably the additive should be of a molecule which has a rate of diffusion and a rate of reaction in such appropriate ranges as producing a difference in concentration between the openings and the bottoms of the features. Consequently, this can be an extremely effective measure to the influence of the fluctuation of the characteristics of the aforementioned seed layer.
Materials useful for such an additive include 2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-methyl]-1,3,3-trimethyl-3H-indolium perchlorate, 2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indolium chloride, 2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indolium iodide, and 2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indolium iodide. They should be preferably used in a concentration of about 1 to 15 mg/liter (which may be abbreviated as mg/L hereunder). The additive concentration outside this range may be effective as additive. If the concentration is lower than 1 mg/L, resulting effects may be insufficient, while if the concentration is higher than 15 mg/L, the concentration of impurities in the copper may possibly increased.
After the copper electroplating, excess portions of metal layers on the insulating layer (that is, the electroplated copper layer, the seed layer, and the barrier layer) are removed by CMP. At this point, since the uniformity in film thickness and the film flatness are required on the wafer, it is preferred to further add one or more of polyethers, organic sulfur compounds, and halide ions in addition of the aforementioned cyanine dyes to improve the thickness distribution on the wafer.
Such polyethers are preferably polyethylene glycols, polypropylene glycols, polyoxypropylene glycols having an average molecular weight of 1000 to 10,000.
The organic sulfur compounds are preferably 3-mercapto-1-propanesulfonic acid, 2-mercapto ethane sulfonic acid, bis(4-sulfobuthyl)disulfide, bis(3-sulfopropyl)disulfide, bis(2-sulfoethyl)disulfide, or bis(p-sulfophenyl)disulfide.
Description of Preferred Embodiments
The following Examples demonstrate preferred embodiments of the present invention.
The copper electroplating bath according to the present invention is used in a range of 15 to 35° C. in order to avoid excessive decomposition of an additive. A concentration of copper ions of 0.2 mol/L or more is preferred and usually used in a range of current density of 0.2 to 3.0 A/dm2 (square decimeter). When the copper electroplating is conducted, preferably the plating bath should be stirred with a pump or air, or the substrate should be rotated or vibrated in order to maintain the supply of the additive constant.
First, a composition of the copper electroplating bath and a process for electroplating copper on an interconnection substrate structure using the same according to the present invention and a method of evaluation for them with reference to
i) Preparation of Interconnection Substrate Structure
In order to make it possible to evaluate characteristics of various plating baths as precisely as possible, basic samples of the interconnection substrate structure were commonly prepared as follows:
That is, as shown in
Then, by sputtering, tantalum was deposited on the overall top surface to form a barrier layer 4 having a thickness of 50 nm and copper was deposited on the barrier layer to form a seed layer 5 having a thickness of 150 nm. The seed layer 5 was produced at a film formation rate of 200 to 400 nm/min using Ceraus ZX-1000, a long distance sputtering apparatus for sputtering copper (made by ULVAC Co.).
ii) Process for Electroplating Copper
There were prepared various plating baths each having a composition as indicated in the following Table 1, and copper was electroplated on the top surface of the interconnection structure as shown in
Sample Nos. 1 to 8 in Table 1 indicate copper electroplating baths according to the present invention, and Sample No. 9 was indicates a copper electroplating bath outside the present invention prepared for comparison.
Various signs described in the column “Type of Additive” designate the following chemical materials:
A-1: 2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-e)-methyl]-1,3,3-trimethyl-3H-indolium perchlorate.
A-2: 2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indolium chloride.
A-3: 2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indolium iodide.
A-4: 2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indolium iodide.
B-1: Polyethylene glycol (an average molecular weight of 3000).
B-2: Polyethylene glycol (an average molecular weight of 1000).
B-3: Polypropylene glycol (an average molecular weight of 3000).
B-4: Polypropylene glycol (an average molecular weight of 1000).
C-1: 3-mercapto-1-propanesulfonic acid.
C-2: 2-mercapto ethane sulfonic acid.
C-3: bis(3-sulfopropyl)disulfide.
C-4: bis(2-sulfoethyl)disulfide.
Each electroplating was conducted at a current density as indicated in Table 1 for a period of time capable of providing a charge corresponding to the formation of a film thickness of 1.0 μm. When the process of growth of film deposit was to be observed, the electroplating was conducted for a period of time capable of providing a charge corresponding to the formation of a film thickness of 0.03 μm.
The temperature was at 24° C. and the total amount of liquid was 20 liter in a bath. As anode electrode, phosphorus-containing copper was used. The electroplating bath was circulated through a filter at a rate of 15 liter/min with an external pump.
iii) Evaluation of Electroplated Copper Film
The cross-section of the plated film was observed by a scanning electron microscope (SEM) where the substrate structure after plated (
The designations of the signs in the column “Type of Cyanine Dye” in Table 2 are the same as those in Table 1. They are reused for convenience. The B/A is the ratio of the film thickness on the bottoms of the features (B) to that on the surface (A).
The plating bath of Sample No. 9 (comparative) produced voids as described later, while those of Sample Nos. 1 to 8 (present invention) did not produced observable voids and seams after plating, because of the addition of cyanine dyes to the plating bath allowing the bottoms of the vias to be preferentially plated. Thus, good filling performance could be achieved. Moreover, the EM resistance of the interconnections was also improved. Therefore, it has been found that the semiconductor integrated circuit devices produced according to the present invention have an improved reliability.
Sample Nos. 3 to 8 contained a polyether, an organic sulfur compound and halide ions in addition to cyanine dye. It has been found that they achieved a good filling property as well as a good uniformity in film thickness on the plane of the substrate with good reproducibility as can be seen from the excellent uniformity in sheet resistance in a range of 3 to 5%. Moreover, the EM resistance of the interconnections was also improved. Therefore, it has been found that the semiconductor integrated circuit devices having an excellent reliability can be produced.
Sample Nos. 5 to 8 made it possible to further facilitate the growth of film to be preferentially plated on the bottoms (
In order to make the effects of the present invention more easily understandable, the present Example 1 will be described with reference to the comparison with the copper electroplating bath of Sample No. 9 (comparative) as shown in Table 1.
With the copper electroplating bath of Sample No. 9 shown on the bottom in Table 1 as a case of using none of the aforementioned additives which are characteristic of the present invention, copper was plated following to steps 1A, 1B and 1C shown in the drawings.
The substrate structure after plated was processed with FIB in the same manner as above and the cross-sections of 100 vias were observed by SEM. As a result, voids were observed in the copper films in the holes indicating that there were produced portions not filled with copper in the vias as shown in the cross-sectional view thereof in
Observation of the process of the growth of copper film to be plated revealed that all the vias ave a uniform copper film grown inside the feature as shown in
The foregoing demonstrate the predominancy of the present invention that the vias can be perfectly filled with copper by allowing the electroplating to proceed preferentially from the bottoms thereof.
Next, the process for producing a semiconductor integrated circuit device having multi-layer interconnections by using the copper electroplating bath according to the present invention will be described with reference to
That is, in
Next, as described in Example 1 and as shown in
Then as shown in
The substrate which was plated by the process as described above was removed from the copper electroplating bath and washed with distilled water for 3 minutes. Then it was processed with FIB and the crosssections of 100 vias were observed by SEM. As a result, it was found that voids or seams were not observed and the vias 3 were perfectly filled with copper.
Next, as shown in
Then, on the flat surface, an insulating layer (not shown) of SiN or the like was coated to prevent the diffusion of copper, and in addition an insulating layer (not shown) of SiO2 or the like is deposited. The insulating film (SiO2 film) and the insulating layer (SiN layer) on the aforementioned filled copper film may be selectively removed by dry etching to form an interconnection structure having a plurality of vias as shown in
Moreover, on the thus obtained interconnection structure, the steps shown in
The semiconductor integrated circuit devices produced as described above according to the present invention have neither void, nor seam in the copper film filled in the vias 3 which are the key to the construction of the multi-layer fine pattern interconnection system. Therefore, the semiconductor integrated circuit devices having a highly reliable multi-layer interconnection structure can be reproducibly produced at high yield.
As shown in
In these insulating interlayers, there is provided vias 3, for connecting between interconnection layers, having a stairs type cross-section through the insulating layers 8 and 2 and having a high aspect ratio which consists of a via having φ 0.25 μm and a depth of 1 μm and having the bottom in contact with the top surface of said first interconnection layer to expose the top surface therein, and a trench or via having φ 0.25 μm and a depth of 0.5 μm terminating at the surface of the insulating layer 8, both vias being in conjunction with each other to form said stairs type. At a location apart from the vias, there is also provided in the insulating layer 2 a trench 7, for forming narrow and long interconnection extending on the surface of the insulating layer 2, having a high aspect ratio such as width 0.25 μm and a depth of 0.5 μm and having the bottom on the insulating layer 8. Thus, the provision in the insulating layers of the narrow and long trench 7 for forming interconnection, a plurality of openings having different depths, one of which is a continuous opening having a different depth differentiates this Example from Example 2 described above.
The thus produced interconnect structure is provided with a barrier layer 4 and a seed layer 5 (
Similarly to Example 2, the substrate after the step shown in
As a result of observations on the process of the growth of plated films within a short period of plating time, all the features had a higher film thickness at the bottom than that at the corner of the features. It has been found, therefore, that plated copper 6 were deposited proceeding preferentially from the bottoms as described with reference to
It has been found from the foregoing that even when there are a plurality of features having different depths, or a plurality of features having different opening diameters, or features having a sequential stairs type bottom as shown in
Large scale integrated circuits (LSIS) will be required to load an increasingly larger number of complicated circuit function blocks on one semiconductor substrate. Such LSIs will require a multi-layer fine pattern interconnection structure which is produced with copper layers filled by plating in a plurality of features having different depths and shapes as described in the present Example 3 in relation to the process of production and the configuration of circuits. Application of the present invention allows high reliability LSIs to be produced in large scale at a high yield.
According to the present invention, the inside of features can be reproducibly filled with copper without apertures such as voids and seams by allowing copper plating to proceed preferentially from the bottoms of the features. The possibility of forming fine vias and trenches not having any apertures such as voids and seams can improve the reliability of high density semiconductor integrated circuit devices having fine interconnections filled with copper and the yield of the production thereof.
The following embodiments are disclosed in relation to the above description:
(1) A copper electroplating bath comprising a solution containing copper ions and electrolyte(s) with an addition of cyanine dye(s).
(2) A copper electroplating bath comprising a solution containing copper ions and electrolyte(s) with an addition of indolium compound(s).
(3) A copper electroplating bath comprising a solution containing copper ions and electrolyte(s) with an addition of at least one of the compounds represented by the following general formula (I):
where X− is an anion, and n is 0, 1, 2, or 3.
(4) The copper electroplating bath according to above items (1) to (3), wherein comprising said copper electroplating bath with a further addition of one or more of polyethers, organic sulfur compounds and halide ions.
(5) The copper electroplating bath according to above items (1) to (4), wherein at least one or more of said cyanine dyes, indolium compounds and the compounds of the general formula (I) is added at a concentration of 1 to 15 mg/L.
(6) A process for producing a semiconductor integrated circuit device characterized in that said process comprising providing an insulating layer having features on the top of the major surface of a semiconductor wafer which has a plurality of circuit element areas formed, depositing a barrier metal layer and a seed metal layer on the bottoms and the side surfaces of said features and on the top surface of said insulating layer, and filling the inside of said features with copper by electroplating with the copper electroplating bath according to any one of above items (1) to (5).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2000-349060 | Nov 2000 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09888642 | Jun 2001 | US |
| Child | 10996382 | Nov 2004 | US |
