The present invention will now be described by way of example only and not in any limitative sense, with reference to the accompanying drawings in which
FIG. 1 shows a first embodiment of a bond pad according to the invention in cross section;
FIG. 2 shows a second embodiment of a bond pad according to the invention; and
FIG. 3 shows a bond pad according to the invention in plan view.
Shown in FIG. 1 is an electrically conducting track 1 according to the invention. The electrically conducting track 1 comprises a GaAs semiconductor substrate 2. Located on the substrate 2 is a serpentine metal resistor track 3 arranged such that the resistance between the opposite ends of the track 3 has a desired value. Covering the resistor track 3 is a dielectric layer 4. An electrically conducting track layer comprising a metal bond pad layer 5 is positioned on the dielectric layer 4.
The electrically conducting track 1 according to the invention is manufactured by depositing the metal resistor track 3 on the substrate 2. This is then covered by the dielectric layer 4. Finally, the bond pad layer 5 is laid down on the dielectric layer 4. The dielectric layer 4 is SiN having a dielectric constant in the range 6-7.5. The resistor track 3 is a thin film having a resistivity around 200 Ohms/Square and a typical thickness in the range 1-200 microns. The bulk resistivity of the metal of the resistor track 3 is substantially less (at least an order of magnitude) than that of the surrounding substrate 2.
In an alternative embodiment the substrate 2 is silicon. Silicon however has a relatively high conductivity and so must be pre-treated (typically by doping or ion implantation) to ensure its electrical resistivity is substantially higher than that of the resistor track 3 material.
Shown in FIG. 2 is a second embodiment of a electrically conducting track 1 according to the invention. The electrically conducting track 1 comprises a GaAs semiconductor substrate 2 having a semiconductor resistor track 3 thereon.
The top face of the resistor track 3 is co-planar with the top face of the substrate 2. Laid down on top of the substrate 2 and resistive track 3 is a dielectric layer 4. On top of this is an electrically conductive bond pad 5.
According to a first method of manufacture of the electrically conducting track of FIG. 2 an upper layer of the GaAs substrate 2 is doped to produce an upper layer (not shown) having improved electrical conductivity. A portion of this upper layer then has its conductivity reduced by ion implantation. The remaining portion of the upper layer defines the resistor track 3. The ion implantation reduces the bulk electrical conductivity of the semiconductor material surrounding the resistor track 3 to at least an order of magnitude less than that of the material of the resistor track 3. The resistor track 3 is then covered with the dielectric layer 4. The conductive bond pad layer 5 is then deposited on the dielectric layer 4.
In an alternative method of manufacture of the electrically conducting track of FIG. 2, a portion of the upper layer of the substrate 2 is doped directly to increase its electrical conductivity to define the resistor track 3. The substrate 2 and track 3 are again covered with a dielectric layer 4 and then a bond pad layer 5.
Shown in FIG. 3 is the electrically conducting track according to the invention in plan view. As can be seen, the resistor track 3 is a serpentine track including a plurality of bends beneath the bond pad 5 to increase its length. The ends of the resistor track 3 extend beyond the bond pad 5 to allow easy connection to the resistor track 3.
In the embodiments of FIGS. 1 to 3 the track layer is a bond pad. In alternative embodiments of the invention the track layer could comprise an alternative electrically conducting track.
In a further embodiment of the invention the electrically conducting track according to the invention comprises a plurality of resistor tracks between the semiconductor substrate and dielectric layer.
Patent Application
20070241429
