Patent Application
20130048981
The present invention relates to circuit manufacturing and identification generally and, more particularly, to a method and/or apparatus for implementing an electrically measurable on-chip IC serial identifier and/or methods for producing the same.
In conventional approaches, after process completion, Integrated Circuits (ICs) can have a visual on-chip pattern to determine their original position on a wafer. This pattern is a label usually referring to a row/column (R/C) identifier (or sometimes some type of serial number scheme) made in a 1X contact layer mask (e.g., 1st metal or nitride layer). With this method, the wafer die position is retrieved by a visual inspection under microscope. These visual methods, including X-rays, may be problematic to maintain a full traceability system of the IC, especially in the case where the dies are coated with opaque material or subsequently assembled in lidded packages. The package cover or lid (e.g., metal or dielectric) or over-molding compound of these packages precludes easy reading. Furthermore, it is also extremely difficult and costly to setup a high volume pick and place and marking process at the assembly level that allows the reprint of known good die identifiers on the top of the packages. Therefore, only the part number and lot code are usually printed, and the die position is lost at this assembly process step and full traceability is broken.
It would be desirable to implement an electrically measurable on-chip IC identifier. It would also be desirable to implement an on-chip identifier with a value that may be measured electrically, for example, by direct probing.
The present invention concerns an apparatus comprising an integrated circuit, an interconnect layer within the integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically measurable interconnect pattern by enabling one or more of a plurality of components. The one or more connections may each be configured to enable a respective one of the components. The connections may be programmable while the apparatus is part of a wafer. The interconnect pattern may be configured to identify the apparatus after the apparatus has been manufactured.
The objects, features and advantages of the present invention include providing electrically measurable on-chip IC serial identifier that may (i) overcome breaches in traceability by integrating an on-chip identifier, (ii) provide an on-chip identifier that may be measured electrically, (iii) provide different methods for producing an IC electrical identifier, (iv) track a packaged part back to a particular die location on a wafer, (v) be implemented using a nitride or metal mask and existing foundry visual ID, (vi) implement a full custom identification cell, (vii) may be used to record measurements of a particular die on a wafer to assist with possible failure analysis, and/or (viii) be implemented without adding to the cost of the device (or adding very little).
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
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The logic circuit 104 may be implemented as a number of devices 110a-110n and a number of elements 114a-114n. The devices 110a-110n may be implemented as one or more resistors, capacitors, transistors, diodes, etc. In one example, the devices 110a-110n may be implemented as a combination of resistors, transistors, capacitors, diodes, etc. The elements 114a-114n may be implemented as a number of interconnects. The interconnects 114a-114n may be programmable to be either present (e.g., connected) or not present (e.g., not connected). The interconnects 114a-114n may be programmed at a wafer level (e.g., during wafer deposition) within each die on a wafer.
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The devices 110a-110n and/or the devices 112a-112n maybe implemented in a ladder configuration. In one example, the ladder may be a configuration of series resistors used to code one or more numbers representing a particular row/column of where the apparatus 100 was located on a wafer during fabrication. The row/column numbers may be used to identify the apparatus 100 during post-production troubleshooting. The devices 110a-110n and/or 112a-112n may be contacted (e.g., shorted) with the interconnect array of the elements 114a-114n and/or 120a-120n. In the example shown, when one of the elements 114a-114n and/or 120a-120n are present, the corresponding devices 110a-110n and/or 112a-112n are bypassed.
The elements 114a-114n and/or 120a-120n may be implemented, in one example, in accordance with procedures for implementing visual RC ID elements. However, the particular implementation of the elements 114a-114n and/or 120a-120n may be varied to meet the design criteria of a particular implementation. For example, the elements 114a-114n and/or 120a-120n may be both visually readable and be used to enable a particular combination of the devices 110a-110n and/or 114a-114n.
The values (e.g., a particular resistance) of the devices 110a-110n and/or the devices 112a-112n enabled may be implemented in a progressive manner, such as 50 ohms, 100 ohms, 200 ohms, 400 ohms, etc. In one example, the devices 110a-110n and/or the devices 112a-112n may be implemented using a resistive metal (e.g., TaN, NiCr, etc.). The resistance value read may be the total resistance of all of the resistors (or devices) enabled by the particular interconnects 114a-114n that are present. In a manufacturing environment, a number of the apparatus 100 are normally implemented on a wafer. Each apparatus 100 implemented normally has a unique identifier coded defined by the interconnects 114a-114n. A unique identifier may be an identifier that may be read confidently and/or categorically to be associated with a particular device intended to be identified. In certain instances (e.g., a lot number, etc.) an identifier may be intended to be used on more than one device.
In one example, a progressive increase in values may be implemented. By implementing a progressive increase in the value of the devices 110a-110n and/or 112a-112n, an overlap situation may be reduced. Reducing overlap may help to provide a unique identification for each of the apparatus 100 implemented on a wafer. Also, the particular magnitude of resistance may also be varied. For example, resistances of 1 ohm, 2 ohms, 4 ohms, 8 ohms, 2n ohms may be implemented. In another example, resistances such as 1 ohm, 2.2 ohms, 4.7 ohms, etc. may be implemented in a non-overlapping scale. A set of resistance values may be implemented within a normalized series (e.g., E12, E24, E48, E96, and/or E192 series) to minimize overlaps. Whatever the particular coding scheme implemented, each resistance value is normally unique from the other resistance values.
In general, a plurality of pads 102a-102n are shown. The number of pads read may influence (or relate to) the amount of information stored about the apparatus 100. For example, if a plurality of pads 102a-102n are used to read information, then one of the pads 102a-102n may be implemented for a row and another of the pads 102a-102n may be used to read a column. However, a single one of the pads 102a-102n may be used to read the information if a single row (or other amount of information) is all that is needed. Since the identification may be embedded within the interconnects 114a-114n, very little die area (or real estate) may be needed.
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While a row/column coding has been described, coding of an identifier over a single one of the pads 102a-102n is also possible. The apparatus 100 may be implemented using very little extra GaAs estate (<200×100 μm). The apparatus 100 may be compatible with most IC manufacturers standard visual and/or RC identification layer in nitride or metal layer.
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The apparatus 100 may be implemented as a die or packaged IC having at least a differential terminal (e.g., one pad and one ground reference, two pads, etc.). A serial identification number (or other identifier) may be read from a direct electrical probe measurement. The interconnects 114a-114n may be formed from a number of metal and/or dielectric openings forming an interconnect pattern, A read-only-memory device, switchable at wafer layer deposition level may be implemented. A combination of resistors, capacitors and/or transistors and/or diodes, or combinations may be implemented. In one example, multiple terminals may be used to present different information that has been coded (e.g., row, column, version, lot number, etc.). The information may be retrieved either from a DC, AC and/or asynchronous measurement.
In one example, manufacturing of a specific mask and/or layout process may be used to generate the interconnects 114a-114n. The interconnects 114a-114n may be similar to the visual RC identifiers sometimes used. The interconnects 114a-114n may be used as an interconnect matrix to switch the devices 110a-110n or to code, for example, a row/column position. The interconnects 114a-114n may create an electrically measurable parameter (e.g., through probing, radio transmission, etc.) with unique value referenced to the particular position of the apparatus 100 on the wafer. The matrix of metal or nitride interconnects 114a-114n may be used to code a row/column position (or other information) as a unique electrically measurable parameter. The interconnects 114a-114n may be implemented using very little extra die area (e.g., <100×100 μm2 for a 2×5-bit resistor ladder). Furthermore, a lot number (or other information) may also be coded and later electrically measured, regardless of whether the die 100 is packaged or not. The apparatus 100 may ensure traceability of an IC part down to a original location on a wafer, including lot number.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.
