The current invention claims a foreign priority to application of China 200910202066.8 filed on Dec. 31, 2009.
This invention relates to a kind of semiconductor integrated circuit device. More particularly it relates to one type of electrode pick up structure in shallow trench isolation process and its fabrication method.
A conventional bipolar transistor is illustrated in
Present invention gives a technical solution of an electrode output structure in STI isolation process. It can reduce overall device size, reduce collector electrode pick up resistance and collector parasitic capacitance, and preserve good cut off frequency.
To resolve above mentioned technical issues, the electrode picking up structure in STI process by this invention, active region is isolated by STI. A first conduction type pseudo-buried layer is formed beneath STI. The pseudo-buried layer extends to first conduction type doped active region one. A deep trench contact is made through STI, and lead out doped region one through pseudo-buried layer.
The pseudo buried layer is an ion implant layer of the first conduction type. It can be either N type or P type. Its doping concentration should satisfy the formation of ohmic contact between the doping area and metal.
The deep trench contact is a deep trench hole filled with titanium/titanium nitride (Ti/TiN) barrier metal and metal tungsten.
The pseudo-buried layer is formed after the formation of shallow trench and before trench oxide deposition. It is an ion implantation region beneath the shallow trench. After subsequent thermal anneal process, the pseudo-buried layer extends into active region laterally by diffusion and connects to the doping region one.
The doping region one is an ion implantation layer.
The electrode pick up structure is a collector extraction structure of a bipolar transistor. The doping region one is the collector of the bipolar transistor.
The electrode pick up structure is a substrate extraction structure in a MOS transistor. The substrate which is also referred to as doping region one is the channel region between source and drain of the MOS transistor. The substrate can either be an n-well or p-well, in which N well corresponds to PMOS transistor and P well corresponds to NMOS transistor.
In present invention, the pick up electrode to doped region one in active is formed by the deep trench contact through STI and connect to pseudo buried layer. Compared to existing way of electrode pick up approach, such as existing bipolar transistor collector pick up, in which collector region connects to the buried layer and bypasses STI, then links with high energy ion implant layer and finally to contact, present invented electrode pick up can dramatically reduce device size. At the same time the deep trench contact hole is close to device active region, device collector connection path resistance and parasitic capacitance can be decreased, and device cut off frequency can be increased.
The foregoing and the object, features, and advantages of the invention will be apparent from the following detailed description of the invention, as illustrated in the accompanying drawings, in which:
As shown in
For NPN bipolar transistor, the referred first conductive type is N-type and the referred second conductive type is P-type. For PNP bipolar transistor, the referred first conductive type is P-type and the referred second conductive type is N-type. The pseudo buried layer 202 is formed at the bottom of shallow trench 204 by ion implantation, which will laterally diffuse into active region in subsequent thermal process, and make the pseudo buried layer 202 connecting with ion implantation layer of collector region 210. The collector region is picked up by making deep trench contact 203 in oxide layer of shallow trench 204 and connects with pseudo-buried layer 202. The referred deep trench contact 203 is formed by filling Titanium-titanium nitride (Ti/TiN) barrier metal layer and Tungsten into deep trench hole. The referred deep trench contact 203 penetrates inter layer dielectric (ILD) film 209 and oxide layer of shallow trench.
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Above invention has been detailed by concrete implementation examples. However the invention is by no means restricted by above descriptions. Technical staffs in this area can make various deformation and improvement under this principle. These deformation and improvement should be considered as within the scope of this invention.
Number | Date | Country | Kind |
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200910202066.8 | Dec 2009 | CN | national |