Razdan, Rahul, et al., “A High-Performance Microarchitecture with Hardware-Programmable Functional Units,” MICRO 27 Proceedings of the 27th Annual International Symposium on Microarchitecture, 11/94, San Jose, California, pp. 172-180. |
Vuillemin, J., et al., “Programmable Active Memories: Reconfigurable Systems Come of Age,” IEEE Transactions on VLSI Systems, vol. XX, No. Y, Month 1995, pp. 1-15. |
Clarke, P. “Pilkington Preps Reconfigurable Video DSP,” EE Times, week of Jul. 31, 1995 (1 pg.). |
Brown, C., “Smart Compilers Puncture Code Bloat,”Electronic Engineering Times, Oct. 9, 1995, pp. 38 and 42. |
Mirsky, Ethan A., “Coarse-Grain Reconfigurable Computing,” Massachusetts Institute of Technology, Jun. 1996, pp. 1-119. |
Mirsky, E., “Transit Note #130 MATRIX: Micro-Architecture Specification,” Sep. 15, 1996, pp. 1-53. |
Mirsky, E., et al., “MATRIX: Coarse-Grain Reconfigurable Computing (Abstract),” MIT AI Lab, Cambridge, MA, May 1, 1995, pp. 1-2. |
Mirsky, E., et al., “MATRIX: A Reconfigurable Computing Device with Configurable Instruction Distribution (Extended Abstract),” MIT AI Lab, Cambridge, MA, pp. 1-3. |
Mirsky, E., et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources,” (Extended Abstract), FCCM'96, IEEE Symposium on FPGAs for Custom Computing Machines, Apr. 17-19, 1996, Napa, CA, pp. 1-10. |
Yang, C.K., et al., “A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,” IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1988, pp. 713-722. |
Frajad-Rad, R., et al., “A 0.3-μm CMOS 8-Gb/s 4-PAM Serial Link Transceiver,” IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 757-764. |