Electron-beam lithography method and apparatus, and program thereof

Abstract

An electron-beam lithography apparatus, an electron-beam lithography method, and an electron-beam lithography program are provided that prevent any deformation in pattern dimension at a connection from being recognized as a false defect even with higher-sensitivity optical defect inspection. A circuit pattern containing a plurality of areas with high repetition rates, each of which having more repetitive patterns than surrounding areas of each of the areas with high repetition rates, is split into a plurality of drawing areas so that a boundary between adjacent drawing areas is laid between adjacent areas with high repetition rates. The circuit pattern is drawn on a drawing target for each of the drawing areas.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating the electron-beam lithography method employed in the electron-beam lithography apparatus.

FIG. 2 is a graph showing the correlation between the deflection positions and the beam outputs during drawing.

FIG. 3 is a chart showing the distribution of the beam outputs within the areas across the connections.

FIG. 4A is view showing the arrangement of the areas to be drawn without multi-pass drawing.

FIG. 4B is a graph describing the position-dependence of the beam outputs without multi-pass drawing.

FIG. 4C is a view showing the arrangement of the areas to be drawn with double-pass drawing.

FIG. 4D is a graph describing the position-dependence of the beam outputs with double-pass drawing.

FIG. 4E is a view showing the arrangement of the areas to be drawn with quadruple-pass drawing.

FIG. 4F is a graph showing the position-dependence of the beam outputs with quadruple-pass drawing.

FIG. 5 is a view showing the correlation between the circuit pattern and the drawing areas according to the related art.

FIG. 6 is a view showing the deformation in pattern dimension at the connection.

FIG. 7 is a block diagram showing the configuration of the electron-beam lithography apparatus according to an embodiment of the present invention.

FIG. 8 is a view showing the correlation between the drawing areas and the circuit pattern in the embodiment of the present invention.

FIG. 9 is a flowchart illustrating the electron-beam lithography method according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Now, referring to the accompanying drawings, an embodiment of the present invention is described below in detail. It should be noted that in this embodiment, it is exemplified that the electron-beam lithography method is executed by a program installed in a computer (i.e., a control device 2).

FIG. 7 shows the block diagram of the configuration of the electron-beam lithography apparatus 10 according to the embodiment of the present invention. The electron-beam lithography apparatus 10 is provided with: an exposure device 1 for making a drawing on a drawing target 4; and a control device 2 for controlling the operations of the exposure device 1 and a stage 30 with the drawing target 4 mounded thereon. In this embodiment, the drawing target 4 is assumed to be a photo mask used to draw the DRAM patterns on the semiconductor wafer. The present embodiment is easy to apply to the DRAM pattern, which has the areas with more repetitive patterns than its surrounding areas arranged in a reticular pattern. It should be noted that the patterns to be drawn according to the present embodiment are not limited to the DRAM patterns. Besides the DRAM patterns, the present embodiment may be applied to any pattern containing an area with more repetitive patterns than its surrounding areas, such as the pattern of a multi-functional large scale integrated circuit (LSI), in which the same chip mounts a plurality of functions.

The exposure device 1 has a deflector 11 disposed therein. The exposure device 1 draws patterns by irradiating the electron beam onto the drawing target 4. In this case, the deflector 11 scans the positions, at which the electron beam irradiates, to toggle the electron beam between on and off.

The control device 2 controls the operation of the exposure device 1. The control device 2 is configured by, for example, a computer containing a central processing unit (CPU), read-only memory (ROM), random-access memory (RAM), and the like, and realizes its function through the electron-beam lithography program 20 installed therein.

In addition, data of the circuit pattern to be drawn may be entered in the control device 2 via an input device 30.

Now, the DRAM circuit pattern to be drawn in the embodiment of the present invention is described below. FIG. 8 is a schematic diagram showing the DRAM circuit pattern. In the DRAM circuit pattern, a plurality of memory cell mat areas 5 are arranged in a reticular pattern with a slight gap left between the adjacent ones. The memory cell mat area 5 is an area with the memory cells arranged in an array pattern therein, in which dot-patterns are regularly arranged. This means that the memory cell mat area 5 contains more repetitive patterns than its surrounding areas have. It should be noted that the length of one side of the memory cell mat area 5, drawn on the drawing target 4, is approximately 100 to 300 micrometers.

Next, the electron-beam lithography program 20 is described below. The electron drawing program 20 is provided with: a module for allowing the computer as the control device 2 to act as a drawing area determination section 21; a module for allowing the computer to act as a drawing section 22; and a module for allowing the computer to act as a position movement section 23.

The drawing area determination section 21 realizes the function of setting the area to be drawn. In this case, the drawing areas are set so as to split the whole circuit pattern into a plurality of areas. How to split the whole circuit pattern into the drawing areas is described later.

The drawing section 22 draws the circuit pattern on the drawing target 4 in each of the drawing areas by means of the exposure device 1. The position movement section 23 moves the stage 30 mounting the drawing target 4. As soon as drawing is finished in one drawing area, the stage 30 is moved by one drawing area by means of the position movement section 23, and drawing is initiated in the adjacent drawing area by means of the drawing section 22. These operations are repeated until the whole circuit pattern is drawn on the drawing target 4.

Next, the electron-beam lithography method according to the embodiment of the present invention is described below. FIG. 9 is a flowchart of the electron-beam lithography method according to the embodiment of the present invention. The electron-beam lithography method involves a process composed of steps S10 to S50. Each of the steps is in detail described below.

Step S10: Reads the Circuit Pattern

First, data of the circuit pattern to be drawn is entered into the control device 2 via the input device 30.

Step S20: Sets the Areas to be Drawn

Second, the drawing area determination section 21 sets the drawing areas based on the entered data on the circuit pattern. Referring to FIG. 8, the drawing areas 6 are described. The drawing area determination section 21 sets the boundary between the adjacent drawing areas 6 (i.e., the connection 7) so that the boundary is laid between the adjacent memory cell mat areas 5. In this embodiment of the present invention, each of the drawing areas 6 is set so that it corresponds to two vertically adjacent memory cell mat areas 5. It should be noted that each drawing area 6 may correspond to any number of memory cell mat areas 5 provided that the connection 7 is laid between the adjacent memory cell mat areas 5 and the drawing areas 6 are narrower than the allowable deflection area of the exposure device 1.

Step S30 to S50: Draws the Circuit Pattern in Each Drawing Area

Third, the drawing section 22 draws the circuit pattern on the drawing target 4 by means of the exposure device 1. In this case, the circuit pattern is drawn in units of the drawing areas 6. This means that as soon as drawing is finished in one of the drawing areas 6 (step S30), it is determined whether drawing has been made in all the drawing areas (step S40). If any drawing area 6 with no pattern drawn is detected, the stage 30 mounting the drawing target 4 moves by one drawing area (step S50). Then, a drawing is made in the adjacent drawing area 6. On the other hand, at the step 40, when it is determined that a drawing has been made in all the drawing areas 6, the drawing process is brought to completion.

As described above, according to the embodiment of the present invention, no sudden deformation in pattern dimension due to a rapid change in beam output occurs in the memory cell mat areas 5 during the drawing process because the connection 7 is laid between the memory cell mat areas 5. Conventionally, when a rapid change in pattern dimension occurs in the memory cell mat areas 5, a sudden deformation in pattern dimension may occur in the area with more repetitive patterns than its surrounding areas. This may induce light interference in the site with the dimension deformed, causing a stripe-pattern or reticular-pattern of color shading to be observed in some cases. This type of stripe-pattern or reticular-pattern color shading is recognized as a lot of false defects during the optical defect inspection process. In contrast, according to the embodiment of the present invention, no sudden deformation in pattern dimension occurs in the area with more repetitive patterns than its surrounding areas, and thus the occurrence of stripe-pattern or reticular-pattern color shading being suppressed. In this case, a sudden deformation in pattern dimension may occur at the connection 7 laid between the memory cell mat areas 5. However, since the boundary between the memory cell mat areas 5 is not the area with more repetitive patterns than its surrounding areas, no light interference is induced. This means that no false defects are observed during the optical defect inspection process. Accordingly, false defect detection is suppressed during the optical defect inspection process, improving its yield.

When the circuit pattern is drawn by the conventional multi-pass drawing technique, throughput reduces because the same areas are scanned many times. In contrast, according to the embodiment of the present invention, the false defect detection can be suppressed during the optical defect inspection process with no loss in throughput because the single-pass drawing technique is applied.

It should be noted that the embodiment of the present invention has been described assuming that the drawing target 4 is the photo mask. However, it is self-evident truth for those skilled in the art that the present embodiment can be applied to the case in which the circuit pattern is drawn directly on the semiconductor wafer as the drawing target 4 in the absence of an intermediate photo mask.

It may be possible that the aforementioned electron-beam lithography program 20 is recorded on a computer-readable recording medium and then the electron-beam lithography program 20 recorded in the recording medium is read in a computer system, for example, the aforementioned computer, for execution to perform the foregoing steps. It should be noted that the computer system referred herein contains any operating system (OS) and peripheral hardware. The computer system having an Internet connection contains a home-page providing environment (home-page viewing environment). The computer-readable recording medium should include portable media such as a flexible disk, magnetic optical disk, ROM, CD (compact disk) -ROM, or storage devices including hard disk contained in the computer system, and those storing a program for a certain time period such as volatile memory (RAM) contained in the computer system, which acts as a server or client when the program is transferred through a network, for example the Internet or a communication line, for example a telephone line. The aforementioned electron beam lithography program 20 may be transmitted from the computer system containing it in a storage device to another computer system through a transmission medium or on a carrier running within the transmission medium. Herein, the transmission medium is a medium which has a function of transmitting information as in the network (communication network), for example the Internet or communication circuits (communication lines), for example a telephone line. The electron-beam lithography program 20 may be intended to partially implement the aforementioned function. It also may be a product provided by combining the aforementioned function with the program already recorded in the computer system, what is known as a difference file (difference program).

While preferred embodiments of the present invention have been described and illustrated above, it should be understood that these are exemplary of the present invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Accordingly, the present invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.

Claims

1. An electron-beam lithography method comprising: a drawing area setting step of splitting a circuit pattern containing a plurality of areas with high repetition rates, each of which having more repetitive patterns than surrounding areas of each of the areas with high repetition rates, into a plurality of drawing areas so that a boundary between adjacent drawing areas is laid between adjacent areas with high repetition rates; anda drawing step of drawing the circuit pattern on a drawing target for each of the drawing areas.

2. The electron-beam lithography method as recited in claim 1, wherein the circuit pattern is a DRAM circuit pattern, and each of the areas with high repetition rates is a memory cell mat area containing an area where a plurality of memory cells are arranged into an array.

3. The electron-beam lithography method as recited in claim 1, wherein the drawing target is a mask used in an electron-beam lithography apparatus.

4. The electron-beam lithography method as recited in claim 1, wherein the drawing target is a semiconductor wafer.

5. The electron-beam lithography method as recited in claim 1, wherein a single-pass drawing is made on the drawing target at the drawing step.

6. The electron-beam lithography method as recited in claim 1, wherein each of the drawing areas is narrower than an area where an exposure device, which makes a drawing on the drawing target, can deflect an electron beam.

7. An electron-beam lithography apparatus comprising: an exposure device which makes a drawing on a drawing target by means of an electron beam; anda control device which controls the operation of the exposure device,wherein the control device comprises:a drawing area determination section which splits a circuit pattern containing a plurality of areas with high repetition rates, each of which having more repetitive patterns than surrounding areas of each of the areas with high repetition rates, into a plurality of drawing areas so that a boundary between adjacent drawing areas is laid between adjacent areas with high repetition rates; anda drawing section which allows the exposure device to draw the circuit pattern on the drawing target for each of the drawing areas.

8. The electron-beam lithography apparatus as recited in claim 7, wherein the circuit pattern is a DRAM circuit pattern, and each of the areas with high repetition rates is a memory cell mat area containing an area where a plurality of memory cells are arranged into an array.

9. The electron-beam lithography apparatus as recited in claim 7, wherein the drawing target is a mask used in the electron-beam lithography apparatus.

10. The electron-beam lithography apparatus as recited in claim 7, wherein the drawing target is a semiconductor wafer.

11. The electron-beam lithography apparatus as recited in claim 7, wherein the drawing section allows the exposure device to make a single-pass drawing.

12. The electron-beam lithography apparatus as recited in claim 7, wherein each of the drawing areas is narrower than an area where the exposure device can deflect the electron beam.

13. An electron-beam lithography program which allows a computer to execute: a drawing area setting step of splitting a circuit pattern containing a plurality of areas with high repetition rates, each of which having more repetitive patterns than surrounding areas of each of the areas with high repetition rates, into a plurality of drawing areas so that a boundary between adjacent drawing areas is laid between adjacent areas with high repetition rates; anda drawing step of drawing the circuit pattern on a drawing target for each of the drawing areas.

14. The electron-beam lithography program as recited in claim 13, wherein the circuit pattern is a DRAM circuit pattern, and each of the areas with high repetition rates is a memory cell mat area containing an area where a plurality of memory cells are arranged into an array.

15. The electron-beam lithography program as recited in claim 13, wherein the drawing target is a mask used in an electron-beam lithography apparatus.

16. The electron-beam lithography program as recited in claim 13, wherein the drawing target is a semiconductor wafer.

17. The electron-beam lithography program as recited in claim 13, wherein a single-pass drawing is made on the drawing target at the drawing step.

18. The electron-beam lithography program as recited in claim 13, wherein each of the drawing areas is narrower than an area where an exposure device, which makes a drawing on the drawing target, can deflect an electron beam.