Patent Application
20240194761
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0170045, filed on Dec. 7, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to an electronic device and an electronic apparatus including the same.
According to the trend of increasing the integration density of electronic devices such as memories or logic circuits, electronic devices in electronic apparatuses have become more refined. Accordingly, there is an increasing demand for refinement and low power consumption of electronic devices such as transistors and capacitors. However, because the capacitance of an electronic device is proportional to its area, the capacitance may decrease as the size of the electronic device decreases, and a leakage current may increase when the thickness of a dielectric is reduced to increase the capacitance. Accordingly, dielectric materials having a high dielectric constant (high-K) are increasingly used in electronic devices.
Recently, in order to overcome power scaling limitations of related-art devices with high dielectric constants, new low-power devices using negative capacitance characteristics of ferroelectric materials have been proposed. In order to implement such a low-power device, stabilization of the negative capacitance state of a ferroelectric thin film is required.
Provided is an electronic device having an extended region exhibiting negative capacitance.
Provided is an electronic apparatus including the electronic device.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an aspect of at least one embodiment, an electronic device include a conductive material layer, a mixed material layer covering the conductive material layer and comprising a mixture of an orthorhombic crystal phase and a tetragonal crystal phase such that a ferroelectric material and an anti-ferroelectric material coexist in the mixed material layer, wherein a proportion of the orthorhombic crystal phase is between about 35% and about 65% in the mixed material layer, and an electrode layer covering the mixed material layer.
The mixed material layer may include an oxide including Hf1-xAxO2 (x≤0.5), and A may include at least one of Al, Si, Zr, Y, La, Gd, and Sr.
The mixed material layer may include Hf1-xZrxO2 (x≤0.5).
The mixed material layer may be a single layer.
The orthorhombic crystal phase may have ferroelectricity, the tetragonal crystal phase may have anti-ferroelectricity, and the mixed material layer may include one to three energy barrier regions.
The mixed material layer may be configured to have two or three S-curves in a polarization-electric field relationship.
The mixed material layer may exhibit negative capacitance within an electric field range of about −10 MV/cm to about +10 MV/cm.
The mixed material layer may be a thickness of about 0.1 nm to about 20 nm.
Crystallization of the mixed material layer may be obtained by performing a heat treatment before forming the electrode layer or by performing a heat treatment before and after the forming of the electrode layer.
The electronic device may further include a dielectric layer between the mixed material layer and at least one of the conductive material layer and the electrode layer.
The electronic device may comprise a transistor, the conductive material layer may include a channel, and the electrode layer may include a gate electrode.
The electronic device may further include a substrate, and the channel may be at least one of spaced apart from an upper surface of the substrate and extends in a first direction, or include a plurality of channel elements spaced apart from each other in a second direction different from the first direction.
The channel may include the plurality of channel elements, and the mixed material layer may include a plurality of mixed material layers surrounding the plurality of channel elements, respectively, and the gate electrode may protrude from the upper surface of the substrate to surround the plurality of mixed material layers.
The electronic device may further include a stack structure including a plurality of the gate electrode alternately stacked in a vertical direction with a plurality of insulating layers, a plurality of channel holes penetrating the stack structure in the vertical direction, and a plurality of memory cell strings in the plurality of channel holes, the plurality of memory cell strings each including the mixed material layer and the conductive material layer concentrically arranged inside the plurality of channel holes, wherein the plurality of memory cell strings are two-dimensionally arranged.
According to an aspect of another embodiment, an electronic apparatus includes at least one electronic device, wherein the at least one electronic device includes a conductive material layer, a mixed material layer covering the conductive material layer and comprising a mixture of an orthorhombic crystal phase and a tetragonal crystal phase such that a ferroelectric material and an anti-ferroelectric material coexist in the mixed material layer, wherein a proportion of the orthorhombic crystal phase is between about 35% and about 65% in the mixed material layer, and an electrode layer covering the mixed material layer.
The mixed material layer may include a single layer including Hf1-xAxO2(x≤0.5), A may include at least one of Al, Si, Zr, Y, La, Gd, and Sr, and the mixed material layer may include one to three energy barrier regions.
The mixed material layer may be a single layer including Hf1-xZrxO2 (x≤0.5) and may be configured to include one to three energy barrier regions.
The electronic device may comprise a transistor, the conductive material layer may include a channel, the electrode layer may include a gate electrode, the electronic device may further include a substrate, and the channel may be at least one of spaced apart from an upper surface of the substrate and extending in a first direction, or include a plurality of channel elements spaced apart from each other in a second direction different from the first direction.
The channel may comprise the plurality of channel elements, and the mixed material layer may include a plurality of mixed material layers arranged to surround the plurality of channel elements, respectively, and the gate electrode may be arranged to protrude from the upper surface of the substrate to surround the plurality of mixed material layers.
The electronic device may comprise a transistor, the conductive material layer may include a channel, the electrode layer may include a gate electrode. The electronic device may further include a stack structure including a plurality of the gate electrode alternately stacked in a vertical direction with a plurality of insulating layers, a plurality of channel holes penetrating the stack structure in the vertical direction, and a plurality of memory cell strings in the plurality of channel holes, the plurality of memory cell strings each including the mixed material layer and the conductive material layer concentrically arranged inside the plurality of channel holes, wherein the plurality of memory cell strings are two-dimensionally arranged.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. Hereafter and in the following drawings, like reference numerals refer to like elements, and the sizes of elements in the drawings may be exaggerated for clarity and convenience of description. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects and the embodiments described below are merely provided as examples, and various modifications are possible from these embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
In the following descriptions, when an element is referred to as being “on” or “above” another element, the element may directly contact a top/bottom/left/right portion of the other element, or may be on/under/next to the other element with intervening elements therebetween. Unless otherwise defined specifically, a singular expression may encompass a plural expression. In addition, when an element is referred to as “including” a component, the element may additionally include other components rather than excluding other components as long as there is no particular opposing recitation. Additionally, spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, device may be otherwise oriented, for example, rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein should be interpreted accordingly.
The term “the” and other demonstratives similar thereto may include a singular form and plural forms. Operations of a method described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context, and the disclosure is not limited to the described order of the operations.
In addition, as used herein, functional blocks, including those described with terms such as “ . . . er (or)”, “ . . . unit”, “ . . . module”, etc., denote a unit that is configured to perform at least one function or operation, which may be implemented as processing circuitry such as hardware, software, and/or a combination thereof. For example, the processing circuitry more specifically may include (and/or be included in), but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
Line connections or connection members between elements depicted in the drawings represent functional connections and/or physical or circuit connections by way of example, and in actual applications, they may be replaced or embodied with various suitable additional functional connections, physical connections, or circuit connections.
The use of any and all examples, or exemplary language provided herein, is intended merely to describe the technical spirit of the disclosure in more detail and does not pose a limitation on the scope of the disclosure unless otherwise claimed. Additionally, when the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values are modified as “about” or “substantially,” it will be understood that these values should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values. When referring to “C to D”, this means C inclusive to D inclusive unless otherwise specified.
A ferroelectric material has spontaneous polarization due to a non-centrosymmetric charge distribution (e.g., in a material structure crystallized into an orthorhombic crystal phase). Thus, the ferroelectric material has remnant polarization due to a dipole even in an absence of an external electric field. In addition, the direction of polarization may be switched by an external electric field.
In contrast, an anti-ferroelectric material may crystallize, e.g., into a tetragonal crystal phase, such that the anti-ferroelectric material includes an array of electric dipoles, but the remnant polarization of the anti-ferroelectric material may be 0 or close to 0. Thus, the directions of adjacent dipoles become the opposite in the absence of an electric field, so as to offset polarization, and thus, overall spontaneous polarization and remnant polarization may be 0 or close to 0. However, when an external electric field is applied, the anti-ferroelectric material may have polarization characteristics and switching characteristics.
An electronic device according to at least one embodiment may include a mixed material layer in which an orthorhombic crystal phase and a tetragonal crystal phase are mixed and thus a ferroelectric material and an anti-ferroelectric material coexist, and the mixed material layer may be formed such that, in each of positive and negative polarization states, an energy barrier local maximum of the anti-ferroelectric material is located outside an energy well local minimum of the ferroelectric material such that the polarization size becomes larger, so as to have, for example, 3 or less energy barriers or 4 or less energy wells. Accordingly, the mixed material layer may have one, two, or three regions exhibiting an S-curve. Because the mixed material layer expands a region exhibiting negative capacitance, performance boosting of the electronic device due to a negative capacitance effect may be enhanced and expanded.
Referring to
The electronic device 10 according to at least one embodiment has negative capacitance (NC) and may be implemented as a memory device and/or a logic device having two or more threshold voltages.
In at least one embodiment, the conductive material layer 11a may be configured to function as conductive region of a channel layer 11. Therefore, in at least some embodiments, the conductive material layer 11a may include a semiconductive material, or, as described in further detail below, may include a metallically conductive material (e.g., in reference to
The first source/drain region 13 may be formed on one side of the channel 11 and the second source/drain region 15 may be formed on the other side of the channel 11. In a case in which the channel 11 is formed from a substrate base, the first source/drain region 13, the second source/drain region 15, and the channel 11 may be formed by injecting impurities into different regions of a semiconductor substrate, and may include a substrate material as a base material. For example, channel 11 may be a Si channel with Si as a base material. In a case in which the channel 11 is not formed as a substrate base but is implemented as a separate material layer, the first source/drain region 13 and the second source/drain region 15 may be formed of a conductive material. For example, the first source/drain region 13 and the second source/drain region 15 may also include a metal, a metal compound, or a conductive polymer.
In the electronic device 10 according to at least one embodiment, the gate insulating layer 20 may include the mixed material layer 30. The mixed material layer 30 has a material composition in which an orthorhombic crystal phase and a tetragonal crystal phase are mixed and thus a ferroelectric material and an anti-ferroelectric material coexist, and may be formed as a single layer. As noted above, the orthorhombic crystal phase exhibits ferroelectricity, and the tetragonal crystal phase exhibits anti-ferroelectricity. The mixed material layer 30 may have polycrystalline or multiple grains. In addition, the mixed material layer 30 may be provided to have a texture and thus have a preference for a particular crystal orientation. The ratio of the ferroelectric material to the anti-ferroelectric material in the mixed material layer 30 may be adjusted by using the composition and structure of materials, a deposition method, heat treatment conditions, a material type and structure of the first electrode layer 50a (e.g., the gate electrode 50), and/or the like.
As will be described below with reference to
To this end, the proportion of the orthorhombic crystal phase in the mixed material layer 30 may be between 35% and 65%. That is, the mixed material layer 30 may be formed such that the ratio of the orthorhombic crystal phase to the tetragonal crystal phase is between 65:35 and 35:65. As such, the mixed material layer 30 may be formed such that the proportion of a major phase in the ferroelectric material and the anti-ferroelectric material is not greater than 65% and the proportion of a minority phase is not less than 35%. In the mixed material layer 30, the ratio of the orthorhombic crystal phase to the tetragonal crystal phase is between 65:35 and 35:65, and the orthorhombic crystal phase and the tetragonal crystal phase are mixed such that the mixed material layer 30 may crystallize to have characteristics in which the ferroelectric material and the anti-ferroelectric material coexist. Such crystallization may be achieved through a heat treatment process as described below.
Accordingly, the mixed material layer 30 may generate one to three regions exhibiting an S-curve in a polarization-electric field relationship, may expand a region exhibiting negative capacitance, and may exhibit negative capacitance characteristics within a range greater than an electric field range exhibiting negative capacitance when a material layer 30 is formed of only a ferroelectric material. For example, the mixed material layer 30 may exhibit negative capacitance within an electric field range of −10 MV/cm to +10 MV/cm. Here, in a comparative case in which the material layer is formed of only a ferroelectric material, the electric field range exhibiting negative capacitance may be, for example, less than about 3 MV/cm.
In at least one embodiment, the mixed material layer 30 may be formed of an oxide containing Hf1-xAxO2 (x≤0.5). Here, component A may be at least one selected from Zr, Si, Al, Y, La, Gd, and Sr. In at least one embodiment, component A may be added as a dopant. For example, the mixed material layer 30 may be formed to include a dopant of component A within a material having a hafnia-based fluorite structure. Here, the dopant of component A may be at least one selected from Zr, Si, Al, Y, La, Gd, and Sr, and the doping proportion may be 50% or less (x≤0.5). The oxide containing Hf1-xAxO2 (x≤0.5) may also be referred to as an HAO oxide.
In at least one embodiment, the mixed material layer 30 may be formed of the HAO oxide containing 50% or greater of Hf, that is, having a ratio of Hf to component A of 1:1, or being Hf-rich, or may include a perovskite material.
A matrix material of the mixed material layer 30 may be formed by atomic layer deposition through sequential injection cycles of a Hf precursor and an oxidant, and, for the injection the dopant, sub-cycle (SC) doping (e.g., for injecting and doping a dopant of component AG may be added in a middle of the sequential injection cycles of the Hf precursor and the oxidant for forming the matrix material. Here, for example, the sub-cycle doping may be performed after a Hf precursor injection cycle.
Accordingly, by adding the dopant sub-cycle doping of component A in the middle the sequential injection cycles of the Hf precursor and the oxidant for forming the matrix material through atomic layer deposition and after the precursor injection cycle, the matrix material may be doped with the dopant at a desired concentration, and thus, as described above, the mixed material layer 30 formed of HAO oxide that has Hf and component A in a ratio of 1:1 or that is Hf-rich may be formed.
For example, the mixed material layer 30 may be formed of Hf1-xZrxO2 (x≤0.5) that has a ratio of Hf to Zr of 1:1 and/or that is Hf-rich. In a case in which the mixed material layer 30 is formed as Hf1-xZrxO2 (x≤0.5) that has a ratio of Hf to Zr of 1:1 or that is Hf-rich by doping HfO2 with a Zr dopant, a matrix material of HfO2 may be formed by atomic layer deposition through sequential injection of a Hf precursor and an oxidant, and Zr dopant sub-cycle (SC) doping may be performed after Hf precursor injection in the middle of sequential injection, and then oxidant injection may be performed. Accordingly, the mixed material layer 30 made of Hf1-xZrxO2 (x≤0.5) doped with Zr at a desired concentration may be formed.
Additionally, in a case of forming the mixed material layer 30 made of HAO oxide with a ratio of Hf to component A of 1:1, for example, the mixed material layer 30 may be formed by alternately and repeatedly depositing hafnium oxide (HfO2) and an oxide including component A. That is, the mixed material layer 30 may be formed by a solid solution deposition method. For example, hafnium oxide and an oxide including component A may be alternately deposited in one cycle and/or in a plurality of cycles. Hafnium oxide may be deposited by one cycle or a plurality of cycles of atomic layer deposition through sequential injection of a Hf precursor and an oxidant, and an oxide including component A may be deposited by one cycle or a plurality of cycles of atomic layer deposition through sequential injection of a precursor of component A and an oxidant. As such, the mixed material layer 30 made of HAO oxide with a ratio of Hf to component A of 1:1 may be formed by alternately depositing hafnium oxide and an oxide including component A in one cycle or in a plurality of cycles. Here, component A may be at least one selected from Zr, Si, Al, Y, La, Gd, and Sr. That is, the mixed material layer 30 may be formed as, e.g., Hf0.5Zr0.5O2 (HZO), which is a doped hafnia ferroelectric thin film, by a solid solution deposition method in which hafnium oxide and a dopant oxide are alternately deposited.
In the electronic device 10 according to at least one embodiment, the mixed material layer 30 may be formed to a thickness of, for example, about 0.1 nm to about 20 nm. For example, when the electronic device 10 according to at least one embodiment is implemented as a logic device, the mixed material layer 30 may be formed to a thickness of about 0.1 nm to about 5 nm. For example, when the electronic device 10 according to at least one embodiment is implemented as a memory device, the mixed material layer 30 may be formed to a thickness of about 1 nm to about 20 nm.
In addition, the mixed material layer 30 may be heat-treated before depositing the electrode layer 50a, that is, the gate electrode 50, and selectively additionally heat-treated after depositing the gate electrode 50, so as to have a characteristic in which the orthorhombic crystal phase and the tetragonal crystal phase are mixed in the above ratio and thus a ferroelectric material and an anti-ferroelectric material coexist, such that an energy barrier local maximum of the anti-ferroelectric material is located outside an energy well local minimum of the ferroelectric material as illustrated in
Meanwhile, the electrode layer 50a, that is, the gate electrode 50, may include a metallically conductive material, such as a metal, a metal nitride, a metal carbide, polysilicon, and/or a 2D conductive material. For example, the electrode layer 50a may include an electrode material (e.g., a material with no band gap within the operational temperatures). For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and/or tantalum (Ta). The metal nitride may include titanium nitride (TiN) and/or tantalum nitride (TaN). The metal carbide may be a metal carbide doped with (or containing) aluminum and/or silicon, and as a specific example, may include TiAlC, TaAlC, TiSiC, or TaSiC. The gate electrode 50 may have a structure in which a plurality of materials are stacked, and for example, may have a stack structure of metal nitride layer/metal layer such as TiN/Al, or a stack structure of metal nitride layer/metal carbide layer/metal layer such as TiN/TiAlC/W. As noted above, in at least one embodiment, the material of the electrode layer 50a may be selected based on a characteristic of the material to promote the desired ratio of ferroelectric and anti-ferroelectric phases in the mixed material layer 30.
Meanwhile, in the electronic device 10 according to at least one embodiment, the gate insulating layer 20 may further include a dielectric layer 25 between the channel 11 and the mixed material layer 30. The dielectric layer 25 may be formed of, for example, a dielectric material that is not ferroelectric. For example, the dielectric layer 25 may include an anti-ferroelectric or amorphous dielectric material. In another examples, the dielectric layer 25 may be provided between the mixed material layer 30 and the gate electrode 50, and/or may be provided between the channel 11 and the mixed material layer 30 and between the mixed material layer 30 and the gate electrode 50, respectively.
The dielectric layer 25 may serve to stabilize negative capacitance of the mixed material layer 30. The dielectric layer 25 may include, for example, at least one of SiO, AlO, SiON, and SiN, and may have a single-layer or multi-layer structure.
For example, in a case in which the channel 11 includes Si or Ge, the dielectric layer 25 may be formed of, for example, a native oxide layer and/or an oxide layer other than the native oxide layer. As another example, even in a case in which the channel 11 includes Si or Ge, the native oxide layer may be removed, and as in an electronic device 100 illustrated in
Even in the electronic device 100 according to at least one embodiment, as described above, the channel 11 may be formed as a substrate base and/or implemented as a separate material layer. In addition, the channel 11 may include Si or Ge, and in this case, and the mixed material layer 30 may be formed on the channel 11 after removing a native oxide layer formed on the channel 11.
In the electronic device 100 according to at least one embodiment, in a case in which the channel 11 is formed by using the semiconductor substrate 11′ as a base, as in the electronic device 10′ exemplarily illustrated in
Referring to
Referring to
As such, in a case in which only the ferroelectric exists or only the anti-ferroelectric material exists, the negative capacitance region NC may be limited. On the other hand, as in the electronic device 10, 10′, and/or 100 according to at least one embodiment, in a case in which an orthorhombic crystal phase and a tetragonal crystal phase are mixed to form the mixed material layer 30 in which a ferroelectric material and an anti-ferroelectric material coexist, and the difference between the proportions of the ferroelectric material and the anti-ferroelectric material is not large as in the above-described embodiment, all S-curves of the ferroelectric material and the anti-ferroelectric material may be utilized, and thus, a negative capacitance region may be expanded to increase, and/or maximize the negative capacitance effect. Thus, according to the electronic device according to at least one embodiment, it is possible to enhance and expand a performance boosting effect of the electronic device by the negative capacitance effect, and thus, the performance improvement of the device may be increased and/or maximized.
Referring to
The graph indicated by “Antiferro” shows a relationship between the energy and polarization of an anti-ferroelectric material in the mixed material layer 30, and as described above with reference to
According to the electronic device 10, 10′, and/or 100 according to at least one embodiment, the mixed material layer 30 is formed such that the energy barrier local maxima B1 and B2 of the anti-ferroelectric material (Antiferro) in each of positive and negative polarization states are located outside energy well local minima W1 and W2 of the ferroelectric material (Ferro). Accordingly, as shown in
Referring to
As such, as in the mixed material layer 30 according to at least one embodiment, when the orthorhombic crystal phase and the tetragonal crystal phase are mixed in the above-described ratio, the negative capacitance range may be expanded in the electric field (E-field) axis than by the orthorhombic crystal phase, and the number of S-curves may be one or greater, and/or up to three.
It may be seen from
On the other hand, it may be seen that, in the sample of the comparative sample, about 80% of the orthorhombic crystal phase (O) and about 20% of the tetragonal crystal phase (T) are mixed, and one S-curve appears but no effect of expanding the negative capacitance region is obtained. From this, it may be seen that when the portion of the orthorhombic crystal phase is out of the range of 35% to 65% as in the sample of the comparative example, the effect of expanding the negative capacitance region is not obtained.
Referring to
As may be seen from comparison between
In the above, it is illustrated that the electronic device 10, 10′, and/or 100 according to at least one embodiment is a field-effect transistor having the planar channel 11, but the disclosure is not limited thereto. For example, the concept according to the above-described embodiment may be applied to a fin field-effect transistor (FinFET), a gate-all-around FET (GAAFET), or a multi-bridge channel FET (MBCFET) having a three-dimensional (3D) channel structure.
Referring to
In addition, for example, a shallow trench insulator (STI) may be formed for electrical separation from adjacent devices (not shown) and to form a gate electrode 150 surrounding the channel 111. The STI may be formed by forming a shallow trench around the channel 111 or a region corresponding to the channel 111 and filling the trench with an insulating material. The gate electrode 150 may be formed on the STI to surround the channel 111. A gate insulating layer 120 may be provided between the channel 111 and the gate electrode 150. For example, the electronic device 110 having a fin channel structure may be formed by forming the gate insulating layer 120 to surround the channel 111 and forming the gate electrode 150 to surround the gate insulating layer 120. The electronic device 110 illustrated in
As in the electronic devices 10, 10′, and 100 described above with reference to
Referring to
Referring to
The electronic devices 10, 10′, 100, 110, and 200 described above may be employed in various electronic apparatuses. For example, the electronic devices 10, 10′, 100, 110, and 200 described above may be used as logic transistors or memory transistors. In addition, the electronic devices 10, 10′, 100, 110, and 200 described above may be utilized as memory cells, and may constitute a memory cell array in which a plurality of memory cells are arranged two-dimensionally, arranged in one vertical or horizontal direction, or arranged in one direction to form a memory cell string and a plurality of memory cell strings are two-dimensionally arranged. In addition, the above-described electronic devices may constitute part of an electronic circuit constituting an electronic apparatus together with other circuit elements such as capacitors.
Although illustrated as a two-dimensional plane in
Referring to
As in the electronic devices 10 and 100 described above with reference to
For example, the plurality of insulating layers 460 and the plurality of gate electrodes 450 each extend along an X-Y plane on a substrate 401 and are alternately and repeatedly stacked in the Z-direction to form the stack structure 402. In addition, the electronic device 400 may include the gate insulating layer 420 including the mixed material layer 30 and the dielectric layer 25, a cell string 403 including the channel 411 and the dielectric filler 405, and the cell string 403 may be arranged to penetrate the stack structure 402. In other words, the insulating layers 460 and the gate electrodes 450 may be arranged to surround the periphery of the cell string 403. In detail, the gate insulating layer 420 including the mixed material layer 30 and the dielectric layer 25, the channel 411, and the dielectric filler 405 may all extend in the Z-direction to intersect with the insulating layers 460 and the gate electrodes 450.
In addition, the dielectric filler 405 may be arranged at a central portion of the cell string 403, and the gate insulating layer 420 including the mixed material layer 30 and the dielectric layer 25, and the channel 411 may be arranged to concentrically surround the dielectric filler 405. The dielectric layer 25 may be arranged between the mixed material layer 30 and the channel 411. In at least some embodiments, the gate insulating layer 420 may include the mixed material layer 30 in which a ferroelectric material and an anti-ferroelectric material coexist and the dielectric layer 25, or may include the mixed material layer 30 in which the ferroelectric material and the anti-ferroelectric material coexist and the dielectric layer 25 may be omitted. The electronic device 400 may include a plurality of cell strings 403, and the cell strings 403 may be two-dimensionally arranged on an X-Y plane to be spaced apart from each other.
As another example, as illustrated in
Referring to
The electrode layer 550 and the electrode layer 511 may include a conductive material. For example, the electrode layer 550 and the electrode layer 511 may each include a metal (and/or an alloy thereof), a metal nitride, a metal carbide, a metal oxide, a two-dimensional conductive material, and/or a combination thereof. For example, the metal may include at least one of aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), chromium (Cr), and copper (Cu), an alloy thereof, and/or the like. The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), and/or the like. The metal carbide may include a metal carbide doped with (or containing) at least one of aluminum and silicon, for example, TiAlC, TaAlC, TiSiC, or TaSiC. The metal oxide may include, for example, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide-tin oxide alloy (In2O3-SnO2:ITO), indium oxide-zinc oxide alloy (In2O3—ZnO), and/or the like. At least one of the electrode layer 550 and the electrode layer 511 may include a plurality of layers, and may have, for example, a stack structure of metal nitride layer/metal layer or a stack structure of metal nitride layer/metal carbide layer/metal layer.
The mixed material layer 530 may correspond to the mixed material layer 30 described above with reference to
The dielectric layer 525 may be formed of, for example, a dielectric material that is not ferroelectric. For example, the dielectric layer 525 may include an amorphous or anti-ferroelectric dielectric material. The dielectric layer 525 may correspond to the dielectric layer 25 described above with reference to
Referring to
As the capacitor 610, the electronic device 500 or 510 of
The capacitor 610 may be electrically connected to the transistor 650, e.g., through a contact 601. The transistor 650 may be a field-effect transistor. One of the electrodes 511 and 550 of the capacitor 610 may be electrically connected to one of a source SR and a drain DR of the transistor 650 through the contact 601.
The transistor 650 may include a semiconductor substrate 651 including the source SR, the drain DR, and a channel CH, and a gate electrode 657 arranged to face the channel CH, and may include a gate insulating layer 655 arranged between the channel CH and the gate electrode 657.
The semiconductor substrate 651 may include a semiconductor material. The semiconductor substrate 651 may include the source SR, the drain DR, and the channel CH electrically connected to the source SR and the drain DR. The source SR may be electrically connected to or in contact with one end of the channel CH, and the drain DR may be electrically connected to or in contact with the other end of the channel CH. In other words, the channel CH may be defined as a substrate region between the source SR and the drain DR in the semiconductor substrate 651.
The source SR, the drain DR, and the channel CH may be independently formed by injecting impurities into different regions of the semiconductor substrate 651, and in this case, the source SR, the channel CH, and the drain DR may include a substrate material as a base material. In addition, the source SR and the drain DR may be formed of a conductive material. The channel CH may not be formed as a substrate base, but may be implemented as a separate material layer.
The gate electrode 657 may be arranged on the semiconductor substrate 651 to be spaced apart from the semiconductor substrate 651 and face the channel CH.
The gate insulating layer 655 arranged between the semiconductor substrate 651 and the gate electrode 657 may include a paraelectric material or a high-k material. The gate insulating layer 655 and the gate electrode 657 may constitute a gate stack.
Alternatively, as the transistor 650, the electronic device 10, 10′, and/or 100 according to at least one embodiment described above with reference to
The contact 601 may include any suitably conductive material, for example, tungsten, copper, aluminum, polysilicon, and/or the like.
The arrangement of the capacitor 610 and the transistor 650 may be variously modified. For example, the capacitor 610 may be arranged on the semiconductor substrate 651 as illustrated, or may be buried in the semiconductor substrate 651.
Although
In the electronic device according to the various embodiments described above and an electronic apparatus to which the electronic device is applied, thin film deposition may be performed by using various deposition methods such as atomic layer deposition (ALD), metal organic ALD (MOALD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), or physical vapor deposition (PVD). In addition, doping may be performed by using methods such as light ion implant, plasma treatment, or annealing under specific atmosphere, in addition to the above deposition methods.
According to the electronic device according to various embodiments described above, in a metal-oxide-semiconductor capacitor (MOSCAP) structure (including a gate stack) or a capacitor structure in which a mixed material layer in which an orthorhombic crystal phase and a tetragonal crystal phase are mixed and thus a ferroelectric material and an anti-ferroelectric material coexist, and a dielectric layer are stacked, a negative capacitance region may be expanded compared to a structure to which only a ferroelectric material or an anti-ferroelectric material is applied, and thus, device performance may be boosted. In addition, the electronic device according to various embodiments described above may have a MOSCAP structure or a capacitor structure obtained by stacking a mixed material layer in which an orthorhombic crystal phase and a tetragonal crystal phase are mixed and thus a ferroelectric material and an anti-ferroelectric material coexist, and a dielectric layer, and when applied to a FET, may be used as a gate stack and may be applied to a 2D structure as well as a 3D structure.
Referring to
The controller 910 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The input/output device 920 may include at least one device configured to receive inputs and/or to output data, including, e.g., at least one of a keypad, a keyboard, a display, a speaker, etc. The memory 930 may be used to store a command executed by controller 910. For example, the memory 930 may be used to store user data. The electronic apparatus 900 may use the wireless interface 940 to transmit/receive data through a wireless communication network. The wireless interface 940 may include an antenna and/or a wireless transceiver. In some embodiments, the electronic apparatus 900 may be used, for example, in a third generation communication system, for example, code-division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or a communication interface protocol for the third generation communication system, for example, wide-band CDMA (WCDMA). The memory 930 of the electronic apparatus 900 may include an electronic device according to the above-described embodiments.
Referring to
Referring to
In some cases, the electronic device architecture may be implemented in such a manner that computing unit devices and memory unit devices are adjacent to each other in one chip without distinguishing sub-units.
Although the electronic device and the electronic apparatus including the electronic device are described above with reference to the embodiments illustrated in the drawings, the embodiments are merely exemplary, and it will be understood by one of skill in the art that various modifications and equivalent embodiments may be made therefrom. Therefore, the disclosed embodiments are to be considered in a descriptive sense only, and not for purposes of limitation. The scope of the disclosure is in the claims rather than the above descriptions, and all differences within the equivalent scope should be construed as being included in the disclosure.
According to the electronic device and the electronic apparatus including the electronic device according to the embodiments, by forming the electronic device to include a mixed material layer in which an orthorhombic crystal phase and a tetragonal crystal phase are mixed and thus a ferroelectric material and an anti-ferroelectric material coexist, a region exhibiting negative capacitance may be expanded, and accordingly, it is possible to enhance and expand performance boosting of the electronic device by a negative capacitance effect.
It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0170045 | Dec 2022 | KR | national |
