The present invention relates to a semiconductor package and more particularly to a package having an enclosure for protecting a semiconductor die.
A well-known semiconductor device package includes a threaded base, a semiconductor die electrically attached to the threaded base, an electric lead connected to the silicon die and projecting in the opposite direction of the threaded base and a housing enclosing a portion of the electric lead, the semiconductor die and the top surface of the threaded base. Such packages are typically used in commercial applicances and low frequency industrial applications, such as welding equipment.
The housings for these packages represent a significant portion of the manufacturing cost and add to the complexity of the manufacturing process. Specifically, in many cases the housing may need to be brazed or soldered to the threaded base. An inexpensive housing concept that adequately protects the semiconductor die, reduces cost, and simplifies the manufacturing process is a long standing and unresolved need.
One object of the present invention is to provide for an easily assembled semiconductor package having a secure enclosure protecting a semiconductor die.
To achieve this objective, a semiconductor package according to the present invention includes a semiconductor die mounted on a base portion, a perimeter wall snap-fitted on the base portion, surrounding the die, a lead mounted on the die opposite of the base portion and an encapsulant disposed within at least a portion of the space provided between the perimeter and the base portion, encapsulating the die and a portion of the lead. Thus, another portion of the lead is available for connection to an electronic circuit.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
Referring to
The die 16 is electrically connected to a lead 18 by a first electrode 15 thereof and to the base 12 by a second electrode 17 thereof, as will be described later. Preferably, the perimeter wall 14 is cylindrically-shaped and annular, such as a ring, allowing the lead 18 to extend above the perimeter wall 14 for connection to an electronic circuit. The lead 18 may be any conventional lead, such as wire shaped or any other form. An encapsulant 20 fills at least a portion of the space between the perimeter wall 14 and the base portion 12, encapsulating the die 16 and a portion of the lead 18.
The semiconductor device package 10 may include a threaded extension 22, as shown in
In one preferred embodiment, threaded extension 22 is comprised of copper or an alloy of copper. Alternatively, the threaded extension 22 may be of iron or an alloy of iron, which may be plated with tin. The threaded extension 22 may be insulated with a silicone sleeve or may be without insulation.
Referring next to
In one embodiment, the perimeter wall 14 has a lip 24 disposed at one end. In the example of an annular perimeter wall 14, the lip extends inwardly toward the interior of the annulus. Referring to
For example, the diameters of the annular portion of the perimeter wall 14, the lip 24, the base portion 12 and the recessed portion 26 are dimensioned such that the perimeter wall 14 is tightly coupled to the base portion 12, preventing an encapsulant 20 from escaping the interior of the perimeter wall 14, for example, when the encapsulant 20 is poured in a liquid state into the volume defined by the perimeter wall 14 and the base portion 12. In one embodiment, the encapsulant 20 is a viscous resin and is introduced by vacuum filling. The resin is then cured, encapsulating the die 16 and a portion of the lead 18. During curing, the resin is retained within the ring 14 by the snap fitting between the recessed portion 26 and the lip 24. For example, the encapsulant 20 is an epoxy resin, such as Araldite (e.g. CW 1195-1 BD Black) with a cathalizer (e.g. Hardener HW 1196 BD).
An exploded view of a second embodiment is shown in
The base shelf 81 is joined to an intermediate shelf 83. The intermediate shelf 83 has a smaller diameter than the base shelf 81. The upper surface 86 of the base shelf 81 may be joined to a lower surface of the intermediate shelf 83 by soldering, welding or gluing, or the intermediate shelf 83 may be an integral part of the base portion 42. The base portion 42 may be formed as a unit by casting, forging, extruding and machining processes, for example. The intermediate shelf 83 has a first cylindrical extension 82 from its sidewall that defines a recessed portion of the intermediate shelf 83. The bulge 52 in the bottom edge of the annular ring 44 or the inner wall of the ring 44 may create a compression fitting against a portion of the intermediate shelf 83, such as the extension 82, and/or the upper surface 86 of the first shelf 81.
Also, the base portion 12, 42 may be adapted to enhance adhesion of the cured resin to the base portion 12, 42. For example, a retaining structure, such as a shelf 88 having another recessed portion, may be used to retain the encapsulant 20 on the base 12. Also, a projection may be used to prevent the cured resin from rotating with respect to the base. For example, the projection may extend from a portion of the base 12, 42 such as a pin, fin or other projection from the second notch, which locks the encapsulant 20 to the base portion 12. Alternatively, a portion of the retaining structure 88 may be knurled, scored or striated to prevent rotation of the encapsulant 20 on the base portion 12, 42.
The intermediate shelf 83 may be joined to the retaining structure 88 that retains the cured encapsulant 76, fixing the encapsulant 76 to the base portion 42, as shown in
In the second embodiment, such as shown in
The base portion 42 has a die mounting surface 89 that may be joined to a semiconductor die 47. For example, the die 47 is joined to the die mounting surface 89 by a layer of solder 49, making an electrical connection between the die 47 and the base portion 42, as shown in
Next, the ring 44 is snap fitted to the base portion 42, as shown in
A semiconductor device packaged according to the present invention can be adapted to receive any type of die. For example, the die 16, 47 may be a semiconductor chip having any shape with an electrode on each of a top surface and a bottom surface of a thin semiconductor material. The size of the die 16, 47 affects both the size of the package and the rated current. In three examples, the die is a rectifier having dimensions and being capable of handling current as follows:
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the examples herein, but only by the claims themselves.
This application claims the benefit of U.S. Provisional Application No. 60/430,011, filed Nov. 27, 2002, entitled “Package with Snap-on Housing,” which is incorporated in its entirety by reference herein.
Number | Name | Date | Kind |
---|---|---|---|
5005069 | Wasmer et al. | Apr 1991 | A |
5838703 | Lebby et al. | Nov 1998 | A |
5886403 | Yoshinaga et al. | Mar 1999 | A |
6060776 | Spitz et al. | May 2000 | A |
6541800 | Barnett et al. | Apr 2003 | B1 |
6821613 | Kagi et al. | Nov 2004 | B1 |
Number | Date | Country | |
---|---|---|---|
20040099935 A1 | May 2004 | US |
Number | Date | Country | |
---|---|---|---|
60430011 | Nov 2002 | US |