Patent Application
20090195946
The invention relates generally to electrostatic discharge (ESD) protection circuits, and more specifically to ESD protection circuits for Radio Frequency (RF) circuits.
The diminishing feature size of electronic integrated circuits (ICs) has brought the benefit of both lower cost and lower power consumption to electronic systems. Modern IC manufacturers operating at an advanced lithographic node can achieve MOS field-effect transistor (MOSFET) channel lengths of 65 nm and dielectrics of 1.2 nm. This decrease in feature size has increased the susceptibility of IC's to electrostatic discharge (ESD) events. ESD is a common phenomenon that expresses itself in a static shock felt when one's skin is brought into contact with metallic surfaces on dry winter days. The human body can act as a capacitor that builds up charge through an effect known as tribocharging which occurs when two different materials, such as a person's shoes and a carpet, are brought together and then separated. The shock is the result of this charge discharging rapidly to a lower potential. ESD events detectable to human perception are orders of magnitude greater than those capable of damaging the delicate components of modern electronic circuits. ESD is a leading cause of electrical overstress and resultant irreversible damage in electronic circuits and must be considered throughout the design, manufacturing, and distribution process.
Integrated circuits are encased in insulating packages that protect them from ESD events but their input and output (I/O) pins must necessarily be conductive for the circuit to communicate electronically with external systems. The purpose of ESD protection circuits is therefore to delineate electronic signals received at the pins that the circuit receives for power and information processing from the electronic signals that are the result of ESD. The most common technique for ESD protection circuits is to trigger a secondary path for the ESD signals when they are detected. In this regard, the operative action of an ESD protection circuit can be compared to the action of a lightning rod protecting a building. As a lightning rod is connected to conductive paths that divert the energy of a lighting strike to ground without damaging the building, an ESD circuit provides conductive paths from a set of pins to another without damaging the internal circuit.
The filtering aspect of ESD protection circuits needs to be designed to react to the typical characteristic of an ESD signal and not to the typical characteristics of operational signals. ESD events in ICs are characterized by large currents, large voltage potentials, and rapid transients. ESD events typically have energy spectrums that are negligible in the higher than 1 GHz operating frequency range of RF microwave circuits. A standard characteristic for an ESD event is described by the Human Body Model (HBM) which is used to model the effect of a charged human person coming into contact with a packaged integrated circuit. The RC discharge time of the HBM pulse is much slower than typical RF microwave application frequencies. The fastest ESD phenomenon is the Charged Device Model (CDM) which has a rise time on the order of 250 ps. The energy spectrum of the CDM extends into frequencies typical of RF microwave applications but is negligible above 5 GHz. Another commonly applied characteristic is the Machine Model (MM) whose energy spectrum is placed between the CDM and HBM patterns. The robustness of a particular circuit is determined by applying ESD signals that are characterized by these models at progressively higher voltages. The industry standard typically requires a circuit to be able to withstand a 2000V pulse applied with the HBM characteristic, a 200V pulse applied with the MM characteristic and 1000V pulse applied with the CDM characteristic.
The three main failure mechanisms in the internal circuitry of an IC caused by ESD events are thermal breakdown caused by the heat from large currents, dielectric breakdown from large voltage potentials, and metallization melt from large currents. Thermal breakdown is also called avalanche degradation and will occur in the pn-junctions that form MOSFETs and bipolar junction transistors (BJTs) when they are forced to conduct excessive currents. Dielectric breakdown is also known as oxide punch-through and is caused by excessive voltage potential differentials across the gate of a MOSFET. The dielectric of a typical MOSFET is 8×106 V/cm which can translate to a dielectric breakdown of as little as 0.96V given the minimum achievable gate widths available in modern semiconductor manufacturing processes.
The implementation of RF functionality on a MOS integrated circuit is a fairly recent development that has been in response to and has enabled the recent proliferation of portable wireless communication devices. Power Amplifiers (PAs) are a necessary component of RF circuits that amplify a signal to be transmitted.
Traditional ESD protection circuits are not capable of protecting this new class of integrated circuits for two reasons. As explained in reference to
One solution to the problem of parasitic capacitance in an ESD protection circuit is described in U.S. Pat. No. 6,509,779 to Yue. This reference takes advantage of the fact that ESD events have energy spectrums centered around much lower frequencies than the salient electronic signals on which RF circuits operate. The impedance of an inductor increases with frequency according to the equation:
Z=2*π*f*L
Where Z is the impedance, L is the inductance, and f is the frequency. The Yue circuit takes advantage of this characteristic by placing an inductor in series with the ESD device. In this manner the inductor acts as a filter allowing the ESD device to conduct current from the I/O pin to ground at low frequency but not at high frequency. The overall effect of such a circuit is that the ESD device can conduct current and protect the circuit during an ESD event but does not provide a current path at higher frequency for signal loss to occur.
Another group of circuits that address the problem of parasitic capacitance in RF ESD circuits takes advantage of the fact that an inductor and conductor in parallel have very large impedance at a specific frequency. The pair of devices is called an LC pair and the frequency of large impedance is known as the resonant frequency. The resonant frequency can be expressed in radians by the equation:
w
o=1/(LC)1/2
Where wo is the resonant frequency, L is the inductance of the inductor, and C is the capacitance of the capacitor. The LC pair behaves like a notch filter because it has high impedance at the resonant frequency, but its impedance decreases rapidly as the distance between the frequency under consideration and the resonant frequency increases.
The first method that utilizes this principle places a bond wire with an adjustable inductance in parallel with a typical ESD protection diode. In such a circuit the value of C in the above equation is equivalent to the parasitic capacitance of the ESD protection diode (CESD) and L is equivalent to the adjustable inductance of the bond wire (LESD). By setting LESD so that the resonant frequency is equivalent to the operating frequency of the circuit the LC pair presents a high impedance path at the operating frequency and very little signal energy is lost through this path. The result of such a technique is that the parasitic paths are tuned out from affecting the circuit at the operating frequency. A description of such a method can be found in E. Rosenbaum, Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs, Proc EOS/ESD Symp 2005; 9-17.
Another circuit that applies resonance to cancel the effect of the parasitic capacitance of ESD devices is displayed in
Another set of ESD protection schemes that use inductors are disclosed in U.S. Pat. No. 6,624,999 to Johnson and U.S. Pat. No. 7,129,589 to Behzad. The difference between the methods provided in these two patents and those discussed previously is that an inductor acts as an ESD protection device on its own and is not meant to cancel out the capacitance of another ESD device. As mentioned previously, the impedance of an inductor increases with frequency. Therefore, an inductor can be selected that provides a low resistance path for ESD currents at the low frequencies where such currents take effect and a high resistance path during usual RF high frequency operation. The approach disclosed in U.S. Pat. No. 7,129,589 includes an on-chip inductor meant to serve as an ESD protection device that provides a low impedance path to ground at the low frequencies associated with ESD events. The PA is then tuned using another inductor in the form of a bond wire attached from the output of the PA to a separate pin used specifically for the bond wire inductor. The approach described in U.S. Pat. No. 6,634,999 is similar but it is applied to a differential PA with an off chip load. As a result of this different configuration, there are multiple ESD inductors. In this approach the ESD inductors are built into the package substrate of the IC.
In one embodiment of the present invention, an electrostatic discharge protection circuit provides efficient electrostatic discharge protection to an RFIC. The circuit includes several parts such as an inductor coupled from a first rail to an internal node. A power amplifier transistor having a transconductance control node is coupled to internal circuitry, a first terminal coupled to a second rail, and a second terminal coupled to an internal node. The circuit also comprises a pad coupled to an internal node, and this pad is capable of being coupled to off chip systems such as an antenna. The power amplifier transistor serves as the active device for an RF power amplifier. The inductor serves as one of either a bias inductor or a tank inductor for the RF power amplifier. Additionally the inductor acts as a low impedance path to the first rail to protect the power amplifier transistor during an ESD pulse.
Reference now will be made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, it will be apparent to those skilled in the art that modifications and variations can be made in the present technology without departing from the spirit and scope thereof. For instance, features illustrated or described as part of one embodiment may be used on another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers such modifications and variations as come within the scope of the appended claims and their equivalents.
Known resonance isolation techniques and parasitic matching circuits can be very effective. However, both techniques require tuning or an exacting design. Parasitic matching circuits require tuning because the exact capacitive parasitic of ESD protection devices will vary from part to part and depend on many variant factors of the manufacturing process. The resonance matching circuits also need to be tuned or designed with extreme care such that the resonant frequency of the LC pair used to isolate the devices matches the operating frequency of the internal circuit. In addition, if the circuit operates at varying frequencies, then the LC pair has to be adjusted each time the circuit shifts operating frequencies.
The circuit techniques that use additional inductors as low impedance shunts do not require delicate tuning if they don't also use specialized ESD devices. These circuit types can function without specialized ESD devices, such as diodes connected to the I/O pins, because the inductors are less susceptible to damage from ESD events. Passive devices such as inductors can be damaged by metallization melt and other failure mechanisms when forced to carry large currents. However, these devices are more robust than the transistors that form the other connection to the I/O pin in a PA. Therefore, the inductor serves as the ESD protection device for the transistor and the circuit does not need an additional ESD device to protect the inductor itself. Although these circuits do not require specialized ESD devices, they will still require significant area and cost. Passive devices can be some of the most area hungry parts of an integrated circuit design. The additional ESD inductors will consume area and could also require that the original inductor be made larger for targeting the same performance. Inductors placed in parallel between two nodes generate effective impedance less than the impedance of the individual inductors. Therefore, if an additional ESD shunt inductor is added in parallel to the operating circuit's inductor, the original inductor may need to be increased in size which will result in additional cost.
The drawbacks inherent in the prior art are not shared by a circuit that uses the tank inductor of the power amplifier itself as a single polarity ESD protection device. If too much voltage is applied across the amplifier's active device, then the tank inductor can provide a shunt to ground. The inductor can be selected to take advantage of the fact that ESD events tend to have lower frequencies than the operating frequency of the amplifier. The inductor will therefore have a large impedance when needed to amplify the signal at the operating frequency and a lower impedance to provide an easier route for the ESD pulse to shunt at lower frequencies. An added benefit of the invention is that its ESD protection capability will improve as the ever continuing march towards smaller geometries continues. Although this technique is contrary to the focus of the previously discussed prior art, the invention has been reduced to practice, has been found operable, and exceeds minimum industry standards in performance.
The intrinsic inductor ESD protection technique has the advantage of not requiring any matching for the ESD protection devices because there are none. The solution for how to make the ESD devices invisible to the circuit when the circuit is at its regular operating frequency was to have the ESD protection devices be an actual part of the circuit operating in its regular manner. The circuit also has an advantage over the prior art in that a separate inductor for providing the shunt to ground is no longer needed. This results in size and costs savings.
The transistor of the PA will not be able to withstand ESD events in the same manner as the tank inductor withstands ESD events with the opposite polarity. An ESD event with the opposite polarity of that previously discussed will bring the voltage at VINT up to and beyond VDD. Depending upon the voltage at VOUT, either a large voltage will build up across transistor 502 and exceed the punch-through voltage causing dielectric breakdown or a large current will flow through transistor 502 causing thermal breakdown. A combination of both failure mechanisms is also possible. However, with a proper size selected for inductor 501, the voltage at VINT and current IDEV can be kept within the range that transistor 502 can withstand without damage. Inductor 501 will have lower impedance than is necessary for amplifying the operating signal at the lower frequency ESD events. This lower impedance path will allow current to flow through inductor 501 instead of transistor 502 while keeping the voltage at node VINT low. As the voltage at VDD increases ESD clamp 505 will trip and shunt current from VDD to VSS. The ESD current will therefore ultimately be kept away from harming transistor 502.
An added benefit of the intrinsic inductor technique is that the capability of the ESD circuit will improve with decreasing geometries. This is advantageous due to the aforementioned fact that decreasing geometries are more susceptible to ESD failure. The improved performance of this ESD protection scheme with decreasing geometries can be explained with reference to the RF ESD protection circuit with impedance matching illustrated in
There are several other PA configurations to which this invention may be applied. For example, in
Certain techniques can be used in combination with the selection of an adequately sized inductor to increase the ESD protection performance of the circuit. For example, other types of clamps such as silicon controlled rectifiers can be used in place of the gate grounded NMOS device. Also, the clamp can be placed in close proximity to the pad to improve the reaction of the clamp to ESD pulses. The PA transistor itself can be modified to improve its resilience to ESD events. A series resistor can be applied to couple the drain contact from node VINT to the gate covered region of transistor 502. Alternatively, a lesser number of contacts can be used to couple the drain of transistor 502 to node VINT than are usually used. Either of these configurations will effectively create a series resistance on the drain of transistor 502 that will act to limit the current that flows to the transistor instead of the inductor.
The invention will also function with other I/O structures attached to the same pad as the PA. For example, a Low Noise Amplifier (LNA) input could also be attached to the pin and the PA's intrinsic inductor would still provide ESD protection to the transistors coupled to the pad. Also, the ESD protection inductor does not have to be the tank inductor of the PA. An inductor used to bias the I/O node could also be used to provide the same effect.
An embodiment of the invention was reduced to practice and tested using the HBM and Machine Model (MM) industry standard. A differential output PA output driver pin was tested using the intrinsic inductive shunt ESD protection method and a PA transistor with sparse contacts. The invention performed better than the industry standard. The industry HBM standard is 2000V and the device performed up to 8000V. The industry MM standard is 200V and the device performed up to 450V.
A method that applies the invention can be discussed with reference to the flow diagram illustrated in
Although embodiments of the invention have been discussed primarily with respect to specific embodiments thereof, other variations are possible. Various configurations of RF input and output circuits may be used in place of, or in addition to, the circuit configurations presented herein. The invention is not limited to use with silicon and can be applied to any semiconductor material including compound semiconductors. Functions may be performed by hardware or software, as desired. In general, any circuit diagrams presented are only intended to indicate one possible configuration, and many variations are possible. Those skilled in the art will also appreciate that methods and systems consistent with the present invention are suitable for use in a wide range of applications encompassing any involving protection of circuitry from large current and voltage signals. While the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. These and other modifications and variations to the present invention may be practiced by those skilled in the art, without departing from the spirit and scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those skilled in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.
