Claims
- 1. A method for forming a gate structure in a semiconductor device, the gate structure formed on a silicon substrate with an overlying layer of gate oxide, the gate structure having an encapsulated metal and barrier layer, the method comprising the acts of:
- depositing a polysilicon layer on the gate oxide, the polysilicon layer having a top surface;
- depositing a sacrificial layer;
- patterning and etching a trench in said sacrificial layer, said trench having opposing sidewalls and exposing said top surface of said polysilicon layer to form a trench bottom;
- forming a sidewall layer on said trench sidewalls, said sidewall layer extending to said top surface of said polysilicon layer;
- forming a barrier layer on said top surface of said polysilicon layer;
- forming a metal layer in said trench to overly said barrier layer and partially fill said trench;
- forming a top dielectric layer overly said metal layer;
- removing said sacrificial layer; and
- etching said polysilicon layer to stop on said gate oxide.
- 2. A method for forming a gate structure of a semiconductor device, the gate structure formed on a silicon substrate with an overlying layer of gate oxide, the gate structure having an encapsulated metal layer, the method comprising the acts of:
- depositing a polysilicon layer on the gate oxide;
- depositing a barrier layer on said polysilicon layer, the barrier layer having a top surface;
- depositing a sacrificial layer;
- patterning and etching a trench in said sacrificial layer, said trench having opposing sidewalls and exposing said top surface of said barrier layer to form a trench bottom;
- forming a sidewall layer on said trench sidewalls, said sidewall layer extending to said top surface of said barrier layer;
- forming a metal layer in said trench to overly said barrier layer and partially fill said trench;
- forming a top dielectric layer to overly said metal layer;
- removing said sacrificial layer to form a stack of metal, top dielectric layer and said dielectric sidewall; and
- etching said barrier layer and said polysilicon layer to stop on said gate oxide.
Parent Case Info
This application is a divisional of prior application Ser. No. 09/216,126 filed Dec. 18, 1998.
US Referenced Citations (6)
Divisions (1)
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Number |
Date |
Country |
Parent |
216126 |
Dec 1998 |
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