Patent Application
20250040191
The present application generally relates to electronic device fabrication. More specifically, the present application relates to engineering metal oxide layer interfaces to improve electronic device stability.
An electronic device manufacturing apparatus can include multiple chambers, such as process chambers and load lock chambers. Such an electronic device manufacturing apparatus can employ a robot apparatus in the transfer chamber that is configured to transport substrates or wafers between the multiple chambers. In some instances, multiple substrates are transferred together. Process chambers may be used in an electronic device manufacturing apparatus to perform one or more processes on substrates, such as deposition processes and etch processes.
Processes for fabrication of electronic devices (e.g., semiconductor devices) generally include deposition of material (e.g., one or more thin film layers) on a substrate, and processing of the material. Deposition chamber systems, such as chemical vapor deposition (CVD) chamber systems, utilize process gases to perform a deposition process to deposit the material onto a substrate. Examples of CVD deposition processes include plasma enhanced (PE) CVD, thermally enhanced (TE) CVD, high density plasma (HDP) CVD, etc. To perform such CVD deposition processes, a substrate or wafer can be placed within a reactor chamber, and chemical vapors can be introduced into the reactor chamber that cause deposition of a particular material.
In accordance with an embodiment, a transistor device is provided. The transistor device includes a base structure and a metal oxide layer disposed on the base structure. The metal oxide layer includes at least one region having a gradient profile with respect to oxygen (O2) composition.
In accordance with another embodiment, a method is provided. The method includes obtaining a base structure of a transistor device, and forming, on the base structure using a gas mixture comprising oxygen (O2), a metal oxide layer comprising at least one region having a gradient profile with respect to O2 composition.
Aspects and implementations of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings, which are intended to illustrate aspects and implementations by way of example and not limitation.
A transistor can be a component of an electronic device. In some implementations, a transistor is a component of a display device. In some implementations, a transistor is a component of a photovoltaic cell. For example, a transistor can be a component of a solar cell.
For example, a display device can be an organic light emitting diode (OLED) display device. An OLED display device can include a frontplane and a backplane. The frontplane is a layer including a number of pixels that generate images, and the backplane is a layer including switching circuitry having a number of components for controlling the pixels of the frontplane (e.g., an on/off state of the pixels). One example of a backplane is a low-temperature polycrystalline silicon (LTPS) backplane. An LTPS backplane utilizes LTPS to form the transistors of the switching circuitry included within the backplane (“LTPS transistors”). LTPS backplanes may not allow for dynamic changes in refresh rates absent external hardware. Another example of a backplane is a low-temperature polycrystalline oxide (LTPO) backplane. An LTPO backplane can include an LTPO device. The LTPO device can include switching circuitry to control a pixel of the frontplane, and driving circuitry to drive the display. The use of the driving circuitry can provide for a more efficient display that enables dynamic changes in refresh rates without using external hardware. The switching circuitry of an LTPO device can include an array of transistors.
In some implementations, a transistor is a field-effect transistor. For example, a transistor can include a substrate including one or more layers, a channel region disposed on the substrate and between a source region and a drain region, a gate structure disposed on the channel region. The channel region and the source/drain regions can be formed from a semiconductor layer, with the source/drain regions corresponding to respective doped regions of the semiconductor layer. In some implementations, the semiconductor layer is a metal oxide layer. The substrate can include one or more layers of materials. In some embodiments, the channel region and the source and drain regions are formed on a dielectric layer of the substrate. For example, the dielectric layer can be a buffer layer. The gate structure can include a gate dielectric disposed on the channel region, the source/drain regions and the substrate, and a gate conductor disposed on the gate dielectric. The transistor can further include an interlevel dielectric (ILD) layer disposed on the gate structure. The transistor can further include a set of contacts including a source contact electrically connected to the source region using a via, a drain contact electrically connected to the drain region using a via, and a gate contact electrically connected to the gate conductor using a via. The channel region becomes conductive when the transistor is turned on. A threshold voltage of the transistor is the minimum gate-to-source voltage that is sufficient to create a conducting path between the source region and the drain region. Output current (e.g., source-drain current) can be controlled by the voltage applied to the gate structure. More specifically, voltage applied to the gate conductor can generate an electric field that controls the flow of charge carriers through the channel region from the source region to the drain region. In some implementations, a transistor is a thin film transistor (TFT).
In some implementations, the channel region and the source and drain regions can be formed by forming a metal oxide layer on a substrate. For example, the metal oxide layer can be formed on a buffer layer of the substrate. The buffer layer can include any suitable dielectric material. Examples of dielectric materials that can be used to form buffer layers include silicon nitride (Si3N4), silicon dioxide (SiO2), etc. For example, the channel region can be formed from a metal oxide layer, and the source region and the drain regions can be formed at respective ends of the region by doping respective regions of the metal oxide layer. The metal oxide layer can include any suitable metal oxide material. Examples of metal oxide materials include indium oxide, gallium oxide, zinc oxide, tin oxide, indium-zinc-oxide (IZO), indium-tin-oxide (ITO), indium-gallium oxide (IGO), gallium-zinc-oxide (GZO), gallium-tin-oxide (GTO), zinc-tin-oxide (ZTO), indium-gallium-zinc-oxide (IGZO), indium-gallium-tin-oxide (IGTO), indium-zinc-tin-oxide (IZTO), indium-gallium-zinc-tin-oxide (IGZTO), cadmium-tin-oxide (CTO), titanium-tin-oxide (TiTO), copper-aluminum-oxide (CAO), strontium-copper-oxide (SCO), etc.
The metal oxide layer can be formed on the substrate using a deposition process that uses a gas mixture including oxygen gas (O2) and an inert gas. The inert gas can be a noble gas. One example of an inert gas that can be included in a gas mixture is argon (Ar). The presence and control of O2 can impact the properties and characteristics of the metal oxide layer. For example, the level of the partial pressure of O2 (pO2), which is a measurement representing the pressure (e.g., concentration) of O2 within the gas mixture, can be controlled during a deposition process. The total pressure of a gas mixture including O2 and an inert gas is the sum of pO2 and the partial pressure of the inert gas. For example, if the inert gas is Ar, then the partial pressure of Ar in the gas mixture can be represented by pAr. The pO2 level within a gas mixture can be measured as a percent composition of O2 relative to the composition of the inert gas (e.g., Ar). For example, for a gas mixture that includes an approximate 1:1 ratio of O2 to the inert gas, the pO2 level can be about 50%. The pO2 level of a gas mixture can alter properties of the material being deposited. For example, a gas mixture with a higher pO2 level can promote the formation of oxides, while a gas mixture with a lower pO2 level can favor reduced or non-oxidized states.
Positive bias temperature stress (PBTS) of a transistor is a measure of voltage stress resulting from the application of a positive bias voltage to at least one contact of the transistor (e.g., gate contact, source contact and/or drain contact) at an elevated temperature (e.g., a temperature greater than a normal operating temperature of the transistor) over time. PBTS of a transistor can be used to assess the stability and/or reliability of electrical characteristics of the transistor over time by identifying any potential points of failure.
A metal oxide layer can include a first interfacial region and a second interfacial region separated by a non-interfacial region. More specifically, the first interfacial region can include a first metal oxide layer interface (“interface”) defined between a metal oxide layer and a substrate (e.g., a buffer layer), and the second interfacial region can include a second interface defined between the metal oxide layer and a gate dielectric of a gate structure. The non-interfacial region can be referred to as a bulk region. In some implementations the first interface is a bottom interface and the second interface is a top interface. A deposition process to form a metal oxide layer can employ a gas mixture of O2 and an inert gas (e.g., Ar) that has a high pO2 level, which can be used to reduce temperature sensitivity and to prevent transistor shorting. For example, a high pO2 level can be an approximately constant or uniform at about 50% (i.e., 1:1 ratio between O2 and the inert gas). However, using a high pO2 level can degrade stability at one or more interfaces between a metal oxide layer and adjacent layers (e.g., the bottom interface between the metal oxide layer and the substrate and/or the top interface between the metal oxide layer and the gate dielectric), which can be reflected by large threshold voltage shift after PBTS (e.g., high PBTS). For example, the high PBTS can be caused at least in part by the generation of interface traps at the interface(s).
Aspects and implementations of the present disclosure address these and other shortcomings of existing technologies by engineering metal oxide layer interfaces to improve electronic device stability. For example, an electronic device can be a transistor device. Implementations described herein can employ at least one interface engineering method with respect to at least one interface. The at least one interface engineering method can be used to form at least one interfacial region of a metal oxide layer to reduce threshold voltage shift after PBTS while maintaining uniform high pO2 in the bulk region. The at least one interface engineering method can include a bottom interface engineering method to reduce threshold voltage shift after PBTS with respect to a bottom interfacial region including a bottom interface and/or a top interface engineering method to reduce threshold voltage shift after PBTS with respect to interfacial region including a top interface. In some embodiments, one of the bottom interface engineering method or the top interface engineering method is performed. In some embodiment, both of the bottom interface engineering method and the top interface engineering method are performed. An interface engineering method described herein can be used to form an interfacial region having a gradient profile with respect to O2 composition. For example, a bottom interface engineering method can be used to form a bottom interfacial region having a lowest O2 composition at the bottom interface (e.g., the interface between the bottom interfacial region and the base structure), and a highest O2 composition at the interface between the bottom interfacial region and the bulk region. As another example, a top interface engineering method can be used to form a top interfacial region having a lowest O2 composition at the top interface (e.g., the interface between the top interfacial region and the gate dielectric), and a highest O2 composition at the interface between the top interfacial region and the bulk region. Various embodiments for performing the bottom interface engineering method and/or the top interface engineering method are contemplated, as will be described in further detail below with reference to
As shown in
Metal oxide layer 120 can be formed using a deposition process that utilizes a gas mixture including O2 and an inert gas. In some embodiments, the inert gas is Ar. In some embodiments, the deposition process is a physical vapor deposition (PVD) process. For example, the deposition process can be a sputtering process. In some embodiments, the deposition process is a plasma-enhanced deposition process.
The deposition process used to form metal oxide layer 120 (e.g., PVD process) can implement at least one interface engineering method with respect to at least one of interfacial region 122-1 or interfacial region 122-2. More specifically, a first interface engineering method (e.g., a bottom interface engineering method) can be used to with respect to interfacial region 122-1 and/or a second interface engineering method (e.g., a top interface engineering method) can be used with respect to interfacial region 122-2.
In some embodiments, a first interface engineering method (e.g., bottom interface engineering method) includes initiating an inert gas flow of inert gas of a gas mixture, initiating, at a first time, formation of interfacial region 122-1 using a first O2 flow of O2 gas of the gas mixture, and ramping up, from the first time to a second time, the first O2 flow to a second O2 flow to form interfacial region 122-1. Bulk region 124 and interfacial region 122-2 can then be formed to complete the formation of metal oxide layer 120. More specifically, inert gas flow can be approximately constant or uniform, the first O2 flow can be about 0, and the second O2 flow can be selected to achieve a target pO2 level of the gas mixture. For example, the second O2 flow can be approximately equal to the inert gas flow, and the target pO2 level can be about 50%. In some embodiments, the first time is 0 seconds(s). The difference between the first time and the second time defines an O2 flow ramp up time. In some embodiments, the O2 flow ramp up time ranges from about 0 s to about 90 s. In some embodiments, the O2 flow ramp up time ranges from about 1 s to about 10 s. If the deposition process is a plasma-enhanced deposition process, then plasma power (“power”) can be ramped up to a target power while ramping up the O2 flow to the target O2 flow. For example, the target power can be ramped up to the target power at some time between t0 and t1, and the plasma power ramp up time can be less than the O2 flow ramp up time.
An illustrative example of O2 flow (F) over time (t) is shown with reference to
Referring back to
An illustrative example of O2 flow (F) over time (t) is shown with reference to
Referring back to
An illustrative example of O2 flow (F) over time (t) is shown with reference to
Referring back to
An illustrative example of O2 flow (F) over time (t) is shown with reference to
Referring back to
An illustrative example of O2 flow (F) over time (t) is shown with reference to
In some embodiments, a second interface engineering method involves forming the gate dielectric using a deposition process performed at a target temperature to cause a target dissociation of O2 at least from interfacial region 122-2. Dissociation of O2 has the effect of decreasing pO2 (or O2 composition) of interfacial region 122-2. In some embodiments, a second interface engineering method (e.g., top interface engineering method) includes forming the gate dielectric on the metal oxide layer using a deposition process performed at a temperature that is greater than or equal to a threshold temperature. In some embodiments, the deposition process is a chemical vapor deposition (CVD) process. For example, the deposition process can be a plasma-enhanced CVD (PECVD) process. The higher the temperature, the greater the amount of dissociation of O2 from interfacial region 122-2, and thus the greater the decrease in pO2 (or O2 composition). In some embodiments, the temperature ranges from about 200° C. to about 500° C.
For example,
In some embodiments, both a first interface engineering method and a second interface engineering method are used with respect to interfacial regions 122-1 and 122-2, respectively. An illustrative example of pO2 (or O2 composition) as a function of thickness (THK) of metal oxide layer 120 is shown with reference to
As further shown in
As further shown in
As further shown in
In this illustrative example, device 100 includes a transistor device having a planar transistor structure in which the source, drain and channel regions are arranged in a horizontal configuration. Alternatively, device 100 can include a transistor device having a fin field-effect transistor (FinFET) structure in which the gate structure is placed along multiple sides of the channel region (e.g., wrapped around the channel region). That is, a FinFET can be referred to as a multi-gate device. Alternatively, device 100 can include a vertical transistor device (e.g., vertical FET (VFET) or vertical transport FET (VTFET)) in which the source, drain and channel regions are arranged in a vertical configuration.
At block 910, a base structure of a transistor device is obtained. In some embodiments, the base structure includes a buffer layer.
At block 920, a metal oxide layer is formed on the base structure and, at block 930 a gate dielectric is formed on the metal oxide layer. For example the metal oxide layer can be formed on the buffer layer. The metal oxide layer can include a first interfacial region (e.g., bottom interfacial region) and a second interfacial region (e.g., top interfacial region) separated by a bulk region. The first interfacial region can include a first interface (e.g., bottom interface) defined between the metal oxide layer and the base structure (e.g., the buffer layer). The second interfacial region can include a second interface (e.g., bottom interface) defined between the metal oxide layer and the gate dielectric layer.
Forming the metal oxide layer can include performing a deposition process using a gas mixture including O2 and an inert gas. In some embodiments, the deposition process is a PVD process. For example, the deposition process can be a sputtering process.
The metal oxide layer can include at least one region having a gradient profile with respect to O2 composition. More specifically, at least one interface engineering method can be used to form at least one region of the metal oxide layer to have a gradient profile with respect to O2 composition.
In some embodiments, the first interfacial region is formed using at least one first interface engineering method. In some embodiments, a first interface engineering method involves ramping up O2 flow during a deposition process to form the metal oxide layer. In some embodiments, a first interface engineering method involves initiating a deposition process to form the metal oxide layer, stopping the deposition process, performing an anneal process after stopping the deposition process to form the first interfacial region, and resuming the deposition process after performing the anneal process. Further details regarding first interface engineering methods are described above with reference to
In some embodiments, the second interfacial region is formed using at least one second interface engineering method. In some embodiments, a second interface engineering method involves ramping down O2 flow during a deposition process to form the metal oxide layer. Further details regarding these second interface engineering methods are described above with reference to
In some embodiments, a second interface engineering method involves forming the gate dielectric using a deposition process performed at a target temperature to cause a target dissociation of O2 from the metal oxide layer. In some embodiments, the second interface engineering method includes forming the gate dielectric on the metal oxide layer using a deposition process performed at a temperature that is greater than or equal to a threshold temperature. The deposition process can be any suitable deposition process. In some embodiments, the deposition process is a CVD process. For example, the deposition process can be a PECVD process. Further details regarding these second interface engineering methods are described above with reference to
The metal oxide layer can be formed using any suitable deposition process. For example, at least one interface engineering method can be used to form at least one interfacial region of the metal oxide layer prior to forming the gate dielectric at the target temperature. Multiple interface engineering methods can be used. For example, the first interfacial region and the second interfacial region can be formed using at least one first interface engineering method and at least one second interface engineering method (e.g., as shown in
At block 940, fabrication of the transistor device is completed. For example, completing fabrication of the transistor device can include at least one of: forming a channel region and a pair of source/drain regions from the metal oxide layer, forming a gate conductor on the gate dielectric to form a gate structure, forming an ILD layer on the gate structure, or forming a set of contacts. For example, the set of contacts can include a pair of source/drain contacts electrically coupled to the pair of source/drain regions. As another example, the set of contacts can include a gate contact electrically coupled to the gate conductor. Further details regarding blocks 910-940 are described above with reference to
At block 1010A, a deposition process to form a metal oxide layer on a base structure is initiated at a first time and a first O2 flow.
At block 1020A, the first O2 flow is ramped up, from the first time to a second time, to a second O2 flow to form a first interfacial region of the metal oxide layer.
At block 1030A, a bulk region and a second interfacial region of the metal oxide layer are formed. Further details regarding blocks 1010A-1030A are described above with reference to
At block 1010B, a deposition process to form a metal oxide layer on a base structure is initiated at a first time and a first O2 flow.
At block 1020B, the first O2 flow is maintained for a period of time defined between the first time and a second time.
At block 1030B, the first O2 flow is ramped up, from the second time to a third time, to a second O2 flow.
At block 1040B, a bulk region and a second interfacial region of the metal oxide layer are formed. Further details regarding blocks 1010B-1040B are described above with reference to
At block 1010C, a deposition process to form a metal oxide layer on a base structure is initiated at a first time and a first O2 flow.
At block 1020C, an anneal process is performed at a second time to form a first interfacial region of the metal oxide layer. More specifically, the deposition process can be stopped prior to performing the anneal process.
At block 1030C, a bulk region and a second interfacial region of the metal oxide layer are formed. More specifically, the deposition process can be resumed after performing the anneal process. Further details regarding blocks 1010C-1030C are described above with reference to
At block 1110A, a portion of a metal oxide layer is formed using a gas mixture having a first O2 flow. More specifically, the portion of the metal oxide layer can include a first interfacial region including a first interface formed on a base structure (e.g., a buffer layer) and a bulk region.
At block 1120A, the first O2 flow is ramped down to a second O2 flow to form an interfacial region of the metal oxide layer. In some embodiments, the second O2 flow is approximately zero. Further details regarding blocks 1110A-1120A are described above with reference to
At block 1110B, a portion of a metal oxide layer is formed using a gas mixture having a first O2 flow. More specifically, the portion of the metal oxide layer can include a first interfacial region including a first interface formed on a base structure (e.g., a buffer layer) and a bulk region.
At block 1120B, the first O2 flow is ramped down, from a first time to a second time, to a second O2 flow. In some embodiments, the second O2 flow is greater than zero and less than the first O2 flow.
At block 1130B, the second O2 flow is maintained for a period of time defined between the second time and a third time to form an interfacial region of the metal oxide layer. For example, the interfacial region can be a top interfacial region. Further details regarding blocks 1110B-1130B are described above with reference to
The preceding description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present invention. It will be apparent to one skilled in the art, however, that at least some embodiments of the present invention may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” When the term “about” or “approximately” is used herein, this is intended to mean that the nominal value presented is precise within +10%.
Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operation may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be in an intermittent and/or alternating manner.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other implementation examples will be apparent to those of skill in the art upon reading and understanding the above description. Although the present disclosure describes specific examples, it will be recognized that the systems and methods of the present disclosure are not limited to the examples described herein, but may be practiced with modifications within the scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
The present application claims the benefit of U.S. Provisional Patent Application No. 63/528,688, filed on Jul. 25, 2023 and entitled “ENGINEERING METAL OXIDE LAYER INTERFACES TO IMPROVE ELECTRONIC DEVICE STABILITY”, the entire contents of which are hereby incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 63528688 | Jul 2023 | US |
