Claims
- 1. A computer-readable medium comprising computer code for receiving sample data from a logic analyzer embedded within a programmable logic device (PLD), said computer code of said computer-readable medium effecting the following:
automatically embedding a logic analyzer within a programmable logic device (PLD); specifying a breakpoint indicative of the state of at least one signal within said PLD; indicating to said logic analyzer to continuously store internal signals of said PLD in a memory of said logic analyzer such that said internal signals are stored before the occurrence of said breakpoint; receiving said stored internal signals from said logic analyzer, said stored signals representing at least signals stored before said breakpoint, whereby said stored internal signals may be viewed on a user computer.
- 2. A computer-readable medium as recited in claim 1 further comprising computer code for effecting the following:
determining total number of samples to be captured and number of samples to be captured after said breakpoint; and communicating said total number of samples to be captured and said number of samples to be captured after said breakpoint to said logic analyzer, whereby once said breakpoint occurs said logic analyzer continues to capture samples equal to said number of samples to be captured after said breakpoint.
- 3. A computer-readable medium as recited in claim 1 wherein communication to and from said logic analyzer occurs through a JTAG port of said PLD.
- 4. A computer-readable medium comprising computer code for retrieving data stored in a logic analyzer embedded in a programmable logic device (PLD), said computer code of said computer-readable medium effecting the following:
compiling an electronic design and automatically inserting a logic analyzer to produce a complete design file; programming a PLD with said complete design file, said logic analyzer being embedded in said PLD; instructing said logic analyzer in said PLD to run such that said logic analyzer begins to continuously monitor internal nodes of said PLD and to continuously store internal signals from said internal nodes in a memory of said logic analyzer at least up to a breakpoint; issuing a dump data request to said logic analyzer in said PLD; and receiving said stored internal signals from said memory of said logic analyzer, said stored signals representing at least signals monitored before said breakpoint, whereby said stored internal signals may be viewed on a user computer.
- 5. A computer-readable medium as recited in claim 4 further comprising computer code for effecting the following:
determining total number of samples to be captured and number of samples to be captured after said breakpoint; and communicating said total number of samples to be captured and said number of samples to be captured after said breakpoint to said logic analyzer, whereby once said breakpoint occurs said logic analyzer continues to capture samples equal to said number of samples to be captured after said breakpoint.
- 6. A computer-readable medium as recited in claim 4 wherein communication to and from said logic analyzer occurs through a JTAG port of said PLD.
- 7. A method for receiving sample data from a logic analyzer embedded within a programmable logic device (PLD), said method comprising:
automatically embedding a logic analyzer within a programmable logic device (PLD); specifying a breakpoint indicative of the state of at least one signal within said PLD; indicating to said logic analyzer to continuously store internal signals of said PLD in a memory of said logic analyzer such that said internal signals are stored before the occurrence of said breakpoint; receiving said stored internal signals from said logic analyzer, said stored signals representing at least signals stored before said breakpoint, whereby said stored internal signals may be viewed on a user computer.
- 8. A method as recited in claim 7 further comprising:
determining total number of samples to be captured and number of samples to be captured after said breakpoint; and communicating said total number of samples to be captured and said number of samples to be captured after said breakpoint to said logic analyzer, whereby once said breakpoint occurs said logic analyzer continues to capture samples equal to said number of samples to be captured after said breakpoint.
- 9. A method as recited in claim 7 wherein said steps of specifying, indicating and receiving make use a JTAG port of said PLD.
- 10. A method for retrieving data stored in a logic analyzer embedded in a programmable logic device (PLD), said method comprising:
compiling an electronic design and automatically inserting a logic analyzer to produce a complete design file; programming a PLD with said complete design file, said logic analyzer being embedded in said PLD; instructing said logic analyzer in said PLD to run such that said logic analyzer begins to continuously monitor internal nodes of said PLD and to continuously store internal signals from said internal nodes in a memory of said logic analyzer at least up to a breakpoint; issuing a dump data request to said logic analyzer in said PLD; and receiving said stored internal signals from said memory of said logic analyzer, said stored signals representing at least signals monitored before said breakpoint, whereby said stored internal signals may be viewed on a user computer.
- 11. A method as recited in claim 10 further comprising:
determining total number of samples to be captured and number of samples to be captured after said breakpoint; and communicating said total number of samples to be captured and said number of samples to be captured after said breakpoint to said logic analyzer, whereby once said breakpoint occurs said logic analyzer continues to capture samples equal to said number of samples to be captured after said breakpoint.
- 12. A method as recited in claim 10 wherein said steps of instructing, issuing, receiving and communicating make use a JTAG port of said PLD.
- 13. A method for capturing sample data by a logic analyzer embedded within a programmable logic device (PLD), said method comprising:
receiving a breakpoint indicative of a state of at least one signal within said PLD; receiving PLD signal information indicating specified signals to monitor within said PLD; continuously storing said specified signals in a memory of said logic analyzer such that said internal signals are stored before the occurrence of said breakpoint; determining the occurrence of said breakpoint; wherein when it is determined that said breakpoint has occurred, arranging said memory of said logic analyzer such that a portion of said internal signals stored before said breakpoint are available for later analysis.
- 14. A method as recited in claim 13 further comprising:
receiving a value indicating the number of samples to be captured after said breakpoint; and continuing to store said specified signals in said memory of said logic analyzer after the occurrence of said breakpoint, whereby once said breakpoint occurs said logic analyzer continues to capture signals equal to said number of samples to be captured after said breakpoint.
- 15. A method as recited in claim 13 wherein said steps of continuously storing and continuing to store both store said specified signals in a ring buffer that overwrites earlier stored signals when full, whereby signals stored before said breakpoint are made available for later analysis.
- 16. A method as recited in claim 13 wherein said step of receiving a breakpoint receives said breakpoint from a user computer through a JTAG port of said PLD.
- 17. A programmable logic device (PLD) comprising:
PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD; logic analyzer circuitry integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer circuitry; logic means within said logic analyzer circuitry for initiating the capture of signals from said PLD circuitry before a breakpoint occurs; and sample memory circuitry within said logic analyzer circuitry arranged to capture said signals before said breakpoint occurs, whereby said sample memory circuitry is available to present said captured signals for analysis after said capture.
- 18. A programmable logic device (PLD) as recited in claim 17 further comprising:
second logic means within said logic analyzer circuitry for continuing the capture of signals from said PLD circuitry after said breakpoint occurs, said sample memory circuitry being further arranged to capture said signals after said breakpoint occurs, whereby said sample memory circuitry is available to present said captured signals for analysis after said capture.
- 19. A programmable logic device as recited in claim 17 wherein said sample memory circuitry includes a ring buffer that overwrites earlier stored signals when full, whereby signals stored before said breakpoint are made available for later analysis.
- 20. A programmable logic device as recited in claim 17 further comprising:
a JTAG port in communication with said logic analyzer, said JTAG port used to receive said breakpoint and an indication of said signals from a user computer, said JTAG port further used to present said captured signals for analysis to said user computer.
- 21. A programmable logic device (PLD) comprising:
PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD; logic analyzer circuitry integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer circuitry; a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD; and means for performing the function of controlling said logic analyzer circuitry using said JTAG port of said PLD, whereby said logic analyzer circuitry receives said commands from outside said PLD and operates appropriately.
- 22. A PLD as recited in claim 21 wherein said means includes:
unbonded I/O cells through which signals pass between said JTAG port and said logic analyzer circuitry.
- 23. A PLD as recited in claim 21 wherein said means includes:
a test data register implemented in the core of said PLD through which signals pass between said JTAG port and said logic analyzer circuitry.
- 24. A PLD as recited in claim 1 further comprising:
a plurality of logic analyzers; means for performing the function of selecting one of said logic analyzers, wherein said means for controlling controls said selected logic analyzer, whereby said selected logic analyzer receives said commands from outside said PLD and operates appropriately.
- 25. A programmable logic device (PLD) comprising:
PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD; a logic analyzer integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer; a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD; a plurality of first I/O cells arranged to receive serial data from said JTAG port and to provide said serial data to said logic analyzer; and a plurality of second I/O cells arranged to receive captured data from said logic analyzer and to provide said captured data serially to said JTAG port, whereby said logic analyzer receives said commands from outside said PLD and delivers said captured data to said JTAG port.
- 26. A PLD as recited in claim 25 wherein said first I/O cells are arranged to drive said serial data into the core of said PLD while said PLD is in a normal operating environment.
- 27. A programmable logic device (PLD) comprising:
PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD; a logic analyzer integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer; a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD; and a test data register implemented in the core of said PLD arranged to provide serial data from said JTAG port to said logic analyzer, and to provide data captured from said logic analyzer serially to said JTAG port, whereby said logic analyzer receives said commands from outside said PLD and delivers said captured data to said JTAG port.
- 28. A PLD as recited in claim 27 wherein said test data register includes:
a plurality of stimulus cells for providing said serial data to said logic analyzer; and a plurality of sense cells for receiving said captured data from said logic analyzer.
- 29. A method for debugging a programmable logic device (PLD), said method comprising:
compiling an electronic design and inserting a logic analyzer to produce a complete design file; programming said PLD with said complete design file, said logic analyzer being embedded in said PLD; connecting a JTAG (Joint Test Action Group) port of said PLD to said logic analyzer; and controlling said embedded logic analyzer using said JTAG port, whereby said PLD may be debugged.
- 30. A method as recited in claim 29 further comprising:
providing serial data from said JTAG port to first I/O cells of said PLD, said first I/O cells being arranged to load said serial data into said logic analyzer; and receiving captured data from said logic analyzer into second I/O cells, said second I/O cells being arranged to provide said captured data to said JTAG port.
- 31. A method as recited in claim 29 further comprising:
forming a test data register in the core of said PLD through which signals between said JTAG port and said logic analyzer may pass serially.
- 32. A method for debugging a programmable logic device (PLD), said method comprising:
compiling an electronic design and inserting a logic analyzer to produce a complete design file; programming said PLD with said complete design file, said logic analyzer being embedded in said PLD; downloading logic analyzer commands from a computer through a JTAG port of said PLD to be delivered to said logic analyzer; and receiving captured data from said logic analyzer via said JTAG port of said PLD, whereby said PLD may be debugged.
- 33. A method as recited in claim 32 wherein said commands and said captured data pass serially through said JTAG port, wherein said commands are delivered in parallel to said logic analyzer, and wherein said captured data is captured in parallel from said logic analyzer.
- 34. A computer-readable medium comprising computer code for debugging a programmable logic device (PLD), said computer code effecting the following:
compiling an electronic design and inserting a logic analyzer to produce a complete design file; programming said PLD with said complete design file, said logic analyzer being embedded in said PLD; connecting a JTAG (Joint Test Action Group) port of said PLD to said logic analyzer; and controlling said embedded logic analyzer using said JTAG port, whereby said PLD may be debugged.
- 35. A computer-readable medium as recited in claim 34 further comprising computer code for effecting:
providing serial data from said JTAG port to first I/O cells of said PLD, said first I/O cells being arranged to load said serial data into said logic analyzer; and receiving captured data from said logic analyzer into second I/O cells, said second I/O cells being arranged to provide said captured data to said JTAG port.
- 36. A computer-readable medium as recited in claim 34 further comprising computer code for effecting:
forming a test data register in the core of said PLD through which signals between said JTAG port and said logic analyzer may pass serially.
- 37. A computer-readable medium comprising computer code for debugging a programmable logic device (PLD), said computer code effecting the following:
compiling an electronic design and inserting a logic analyzer to produce a complete design file; programming said PLD with said complete design file, said logic analyzer being embedded in said PLD; downloading logic analyzer commands from a computer through a JTAG port of said PLD to be delivered to said logic analyzer; and receiving captured data from said logic analyzer via said JTAG port of said PLD, whereby said PLD may be debugged.
- 38. A computer-readable medium as recited in claim 37 wherein said commands and said captured data pass serially through said JTAG port, wherein said commands are delivered in parallel to said logic analyzer, and wherein said captured data is captured in parallel from said logic analyzer.
Parent Case Info
[0001] This application claims priority of U.S. provisional patent application No. 60/065,602, filed Nov. 18, 1997, entitled “Enhanced Embedded Logic Analyzer” which is incorporated by reference. This application is a continuation of U.S. patent application Ser. No. 09/186,607, which in turn is a continuation-in-part of U.S. patent application Ser. No. 08/958,435, filed Oct. 27, 1997, entitled “Embedded Logic Analyzer For A Programmable Logic Device” which is incorporated by reference.
[0002] This application is related to U.S. Pat. No. 6,247,147, entitled “Enhanced Embedded Logic Analyzer,” which is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
|
60065602 |
Nov 1997 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09186607 |
Nov 1998 |
US |
Child |
09887918 |
Jun 2001 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
08958435 |
Oct 1997 |
US |
Child |
09186607 |
Nov 1998 |
US |