This application claims priority of U.S. provisional patent application No. 60/065,602, filed Nov. 18, 1997, entitled “Enhanced Embedded Logic Analyzer” which is incorporated by reference. This application is a divisional of U.S. patent application Ser. No. 09/887,918 filed Jun. 21, 2001, now U.S. Pat. No. 6,460,148, which is a continuation of Ser. No. 09/186,607 filed Nov. 6, 1998. U.S. Pat. No. 6,286,114 which in turn is a continuation-in-part of Ser. No. 08/958,435 filed Oct. 27, 1997, U.S. Pat. No. 6,182,247, which are all incorporated by reference. This application is related to U.S. Pat. No. 6,247,147, entitled “Enhanced Embedded Logic Analyzer,” which is hereby incorporated by reference.
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Number | Date | Country | |
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60/065602 | Nov 1997 | US |
Number | Date | Country | |
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Parent | 09/186607 | Nov 1998 | US |
Child | 09/887918 | US |
Number | Date | Country | |
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Parent | 08/958435 | Oct 1997 | US |
Child | 09/186607 | US |