Patent Application
20240290784
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-028556, filed on Feb. 27, 2023, the entire contents of which are incorporated herein by reference.
The present disclosure relates to an enhancement type metal-oxide semiconductor field-effect transistor (MOSFET) and a semiconductor device.
In the related art, a constant current circuit is known as a circuit including a reference voltage generation circuit. The constant current circuit includes a reference voltage generation circuit configured by a depletion (DEN) type MOSFET and an enhancement (EN) type MOSFET, an operational amplifier to which a signal outputted from the reference voltage generation circuit is inputted, a transistor to which the output from the operational amplifier is inputted, and a resistor connected to the source of the transistor.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
The semiconductor device 1 includes a reference voltage generation circuit 2, and an amplifier circuit 3 as an operating circuit connected to the reference voltage generation circuit 2.
The reference voltage generation circuit 2 includes a depletion type MOSFET 4 (DEN) whose drain (D) is connected to a power supply terminal VDD and whose source(S) and gate (G) are connected to each other, and an enhancement type MOSFET 5 (EN) whose drain (D) and gate (G) are connected to each other and connected to the source of the depletion type MOSFET 4. The back gates of the depletion type MOSFET 4 and the enhancement type MOSFET 5 and the source of the enhancement type MOSFET 5 are fixed to a ground (GNE) potential.
In such a reference voltage generation circuit 2, the constant current of the depletion type MOSFET 4, which always operates at VGS=0 V, is allowed to flow through the enhancement type MOSFET 5 connected in series to the depletion type MOSFET 4, so that the voltage generated in the enhancement type MOSFET 5 is inputted to the amplifier circuit 3 as a reference voltage (Vref), and the voltage amplified by the amplifier circuit 3 is taken out as an output voltage (Vout). The reference voltage Vref is a difference (Vth_E-Vth_D) between the threshold voltage Vth_E of the enhancement type MOSFET 5 and the threshold voltage Vth_D of the depletion type MOSFET 4.
The semiconductor device 1 includes a p-type semiconductor substrate 6 made of, for example, silicon, a CMOS region 7 as an operating circuit region set in the semiconductor substrate 6, and a Ref (Reference) circuit region 8 as a reference circuit region set in the semiconductor substrate 6. The CMOS region 7 and the Ref circuit region 8 are set on the common semiconductor substrate 6.
An n-type MOSFET 9 and a p-type MOSFET 10 as operational MOSFETs are formed in the CMOS region 7. These MOSFETs 9 and 10 constitute the amplifier circuit 3 shown in
In this embodiment, the semiconductor substrate 6 includes a base substrate 61, and an n-type epitaxial layer 62 as an example of a semiconductor layer. Although the base substrate 61 is made of a silicon (Si) substrate in this embodiment, it may be a substrate made of another material (e.g., silicon carbide (SiC) or the like). The base substrate 61 is p-type in this embodiment. The base substrate 61 may have an impurity concentration of, for example, 1×1015 cm−3 or more and 1×1018 cm−3 or less. Further, the thickness of the base substrate 61 may be 100μ m or more and 500μ m or less.
The n-type epitaxial layer 62 is in contact with the base substrate 61 and is laminated on the base substrate 61. The n-type epitaxial layer 62 has a first main surface 62a on the opposite side to the base substrate 61 side, and a second main surface 62b on the base substrate 61 side. In this embodiment, the n-type epitaxial layer 62 has a conductivity type opposite to that of the base substrate 61, and is n-type. The n-type epitaxial layer 62 may have an impurity concentration of, for example, 1×1015 cm−3 or more and 1×1017 cm−3 or less. Further, the thickness of the n-type epitaxial layer 62 may be 2 μm or more and 15 μm or less.
In the semiconductor substrate 6, an element isolation portion 11 including a p-type element isolation well is formed in order to secure the CMOS region 7 and the Ref circuit region 8. Further, in the semiconductor substrate 6, a field insulating film 12 (element isolation film) as an element isolation portion made of an insulating material such as silicon oxide or the like is formed in order to secure regions 4R, 5R, 9R and 10R for the MOSFETs 4, 5, 9 and 10.
A gate insulating film 13 is formed in a region of the semiconductor substrate 6 defined by the field insulating film 12.
An n-type buried layer 14 is formed in each of the CMOS region 7 and the Ref circuit region 8. The n-type buried layer 14 is formed so as to straddle the boundary between the base substrate 61 and the n-type epitaxial layer 62. The n-type buried layer 14 has a higher n-type impurity concentration than the n-type epitaxial layer 62. The thickness of the n-type buried layer 14 may be 1 μm or more and 5 μm or less.
In the CMOS region 7, the n-type MOSFET 9 includes a p-type well 21, an n-type source region 22, an n-type drain region 23, and a p-type back gate region 24.
The p-type well 21 is formed in a surface layer region of the n-type epitaxial layer 62 on the first main surface 62a side. The n-type source region 22 and the n-type drain region 23 are formed in a surface layer region of the p-type well 21 at an interval. The n-type source region 22 and the n-type drain region 23 have a higher n-type impurity concentration than the n-type epitaxial layer 62.
The p-type back gate region 24 is a surface layer region of the p-type well 21, and is formed in a region on the opposite side of the n-type drain region 23 from the n-type source region 22 in a spaced-apart relationship with the n-type drain region 23. The p-type back gate region 24 has a higher p-type impurity concentration than the p-type well 21.
A polysilicon gate 26 is formed to face a channel region 25 between the n-type source region 22 and the n-type drain region 23 with the gate insulating film 13 interposed between the n-type source region 22 and the n-type drain region 23. Both sides of the polysilicon gate 26 are covered with sidewalls 27 made of an insulating material such as silicon oxide or the like. The polysilicon gate 26 is made of conductive polysilicon containing an n-type impurity. The n-type impurity is P (phosphorus) in this embodiment. That is, the polysilicon gate 26 is made of n-type polysilicon. The polysilicon gate 26 may be referred to as n-type polysilicon gate 26.
N-type low concentration layers 28 and 29 are formed between the n-type source region 22 and the n-type drain region 23 and the polysilicon gate 26, i.e., in the region directly under the sidewalls 27. In this way, an LDD structure is formed. The n-type low concentration layers 28 and 29 are regions formed to have a lower concentration than the n-type source region 22 and the n-type drain region 23 and formed by implanting impurity ions more shallowly than in the n-type source region 22 and the n-type drain region 23.
The n-type low concentration layers 28 and 29 are formed in a self-aligned manner with respect to the polysilicon gate 26, and the n-type source region 22 and the n-type drain region 23 are formed in a self-aligned manner with respect to the sidewalls 27. The n-type low concentration layers 28 and 29 relax an electric field in the vicinity of the n-type drain region 23 and suppress a hot electron effect.
In the CMOS region 7, the p-type MOSFET 10 includes an n-type well 31, a p-type source region 32, a p-type drain region 33, and an n-type back gate region 34.
The n-type well 31 is formed in a surface layer region of the n-type epitaxial layer 62 on the side of the first main surface 62a. The p-type source region 32 and the p-type drain region 33 are formed in a surface layer region of the n-type well 31 at an interval.
The n-type back gate region 34 is a surface layer region of the n-type well 31 and is formed in a region on the opposite side of the p-type source region 32 from the p-type drain region 33 in a spaced-apart relationship with the p-type source region 32. The n-type back gate region 34 has a higher n-type impurity concentration than the n-type well 31.
A polysilicon gate 36 is formed to face a channel region 35 between the p-type source region 32 and the p-type drain region 33 with the gate insulating film 13 interposed between the p-type source region 32 and the p-type drain region 33. Both sides of the polysilicon gate 36 are covered with sidewalls 37 made of an insulating material such as silicon oxide or the like. The polysilicon gate 36 is made of conductive polysilicon containing a p-type impurity. The p-type impurity is B (boron) in this embodiment. That is, the polysilicon gate 36 is made of p-type polysilicon. The polysilicon gate 36 may be referred to as p-type polysilicon gate 36.
P-type low concentration layers 38 and 39 are formed between the p-type source region 32 and the p-type drain region 33 and the polysilicon gate 36, i.e., in the region directly under the sidewalls 37. In this way, an LDD structure is formed. The p-type low concentration layers 38 and 39 are regions formed to have a lower concentration than the p-type source region 32 and the p-type drain region 33, and are formed by implanting impurity ions more shallowly than in the p-type source region 32 and the p-type drain region 33.
The p-type low concentration layers 38 and 39 are formed in a self-aligned manner with respect to the polysilicon gate 36, and the p-type source region 32 and the p-type drain region 33 are formed in a self-aligned manner with respect to the sidewalls 37. The p-type low concentration layers 38 and 39 relax an electric field in the vicinity of the p-type drain region 33 and suppress a hot electron effect.
In the Ref circuit region 8, the depletion type MOSFET 4 includes a p-type well 41, an n-type source region 42, an n-type drain region 43, and a p-type back gate region 44. The p-type well 41 is an example of a “first p-type region” of the present disclosure. The n-type source region 42 is an example of a “first (n-type) source region” of the present disclosure. The n-type drain region 43 is an example of a “first (n-type) drain region” of the present disclosure.
The p-type well 41 is formed in a surface layer region of the n-type epitaxial layer 62 on the side of the first main surface 62a. The n-type source region 42 and the n-type drain region 43 are formed in a surface layer region of the p-type well 41 at an interval. The n-type source region 42 and the n-type drain region 43 have a higher n-type impurity concentration than the n-type epitaxial layer 62.
The p-type back gate region 44 is formed in the surface layer region of the p-type well 41 on the opposite side of the n-type drain region 43 from the n-type source region 42 in a spaced-apart relationship with the n-type drain region 43. The p-type back gate region 44 has a higher p-type impurity concentration than the p-type well 41.
A polysilicon gate 46 is formed to face a channel region 45 between the n-type source region 42 and the n-type drain region 43 with the gate insulating film 13 interposed between the n-type source region 42 and the n-type drain region 43. Both sides of the polysilicon gate 46 are covered with sidewalls 47 made of an insulating material such as silicon oxide or the like. An n-type impurity is implanted into the channel region 45. The polysilicon gate 46 is made of conductive polysilicon containing an n-type impurity. The n-type impurity is P (phosphorus) in this embodiment. That is, the polysilicon gate 46 is made of n-type polysilicon. The polysilicon gate 46 may be referred to as n-type polysilicon gate 46.
The channel region 45 is an example of a “first channel region” of the present disclosure. The polysilicon gate 46 is an example of a “first polysilicon gate” of the present disclosure. The gate insulating film 13 below the polysilicon gate 46 is an example of a “first gate insulating film” of the present disclosure. The sidewalls 47 are an example of “first sidewalls” of the present disclosure.
N-type low concentration layers 48 and 49 are formed between the n-type source region 42 and the n-type drain region 43 and the polysilicon gate 46, i.e., in the region directly under the sidewalls 47. In this way, an LDD structure is formed. The n-type low concentration layers 48 and 49 are regions formed to have a lower concentration than the n-type source region 42 and the n-type drain region 43, and are formed by implanting impurity ions more shallowly than in the n-type source region 42 and the n-type drain region 43.
The n-type low concentration layers 48 and 49 are formed in a self-aligned manner with respect to the polysilicon gate 46, and the n-type source region 42 and the n-type drain region 43 are formed in a self-aligned manner with respect to the sidewalls 47. The n-type low concentration layers 48 and 49 relax an electric field near the n-type drain region 43 and suppress a hot electron effect.
In the Ref circuit region 8, the enhancement type MOSFET 5 includes a p-type well 51, an n-type source region 52 as a second source region, an n-type drain region 53 as a second drain region, and a p-type back gate region 54.
The p-type well 51 is an example of a “p-type region” and a “second p-type region” of the present disclosure. The n-type source region 52 is an example of an “n-type source region” and a “second source region” of the present disclosure. The n-type drain region 43 is an example of an “n-type drain region” and a “second drain region” of the present disclosure.
The p-type well 51 is formed in a surface layer region of the n-type epitaxial layer 62 on the first main surface 62a side in a spaced-apart relationship with the p-type well 41 of the depletion type MOSFET 4. The n-type source region 52 and the n-type drain region 53 are formed in a surface layer region of the p-type well 51 at an interval. The n-type source region 52 and the n-type drain region 53 have a higher n-type impurity concentration than the n-type epitaxial layer 62.
The p-type back gate region 54 is formed in the surface layer region of the p-type well 51 on the opposite side of the n-type drain region 53 from the n-type source region 52 in a spaced-apart relationship with the n-type drain region 53. The p-type back gate region 54 has a higher p-type impurity concentration than the p-type well 51.
A polysilicon gate 56 is formed to face a channel region 55 between the n-type source region 52 and the n-type drain region 53 with the gate insulating film 13 interposed therebetween. Both sides of the polysilicon gate 46 are covered with sidewalls 57 made of an insulating material such as silicon oxide or the like. The channel region 55 is doped with an n-type impurity. The n-type impurity concentration in the channel region 55 is equal to the n-type impurity concentration in the channel region 45 of the depletion type MOSFET 4.
The channel region 55 is an example of a “second channel region” of the present disclosure. The polysilicon gate 56 is an example of a “polysilicon gate” and a “second polysilicon gate” of the present disclosure. The gate insulating film 13 below the polysilicon gate 56 is an example of a “second gate insulating film” of the present disclosure. The sidewalls 57 are an example of “second sidewalls” of the present disclosure.
The main portion of the polysilicon gate 56 is made of non-doped polysilicon. The main portion of the polysilicon gate 56 refers to a region that occupies 80% or more of the portion of the polysilicon gate 56 facing the channel region 55. Furthermore, the non-doped polysilicon refers to polysilicon having an impurity concentration of 1×1014 cm−3 or less.
In this embodiment, the polysilicon gate 56 includes n-type portions 71 arranged on both sides of the polysilicon gate 56 and made of n-type polysilicon, and a non-doped portion 72 arranged between the n-type portions 71 and made of non-doped polysilicon. The n-type impurity contained in the n-type portion 71 is P (phosphorus) in this embodiment. In this embodiment, the non-doped portion 72 corresponds to the main portion. The entire polysilicon gate 56 may be made of non-doped polysilicon.
N-type low concentration layers 58 and 59 are formed between the n-type source region 52 and the n-type drain region 53 and the polysilicon gate 46, i.e., in the region directly under the sidewalls 57. In this way, an LDD structure is formed. The n-type low concentration layers 58 and 59 are regions formed to have a lower concentration than the n-type source region 52 and the n-type drain region 53, and are formed by implanting impurity ions more shallowly than in the n-type source region 52 and the n-type drain region 53.
The n-type low concentration layers 58 and 59 are formed in a self-aligned manner with respect to polysilicon gate 56, and the n-type source region 52 and the n-type drain region 53 are formed in a self-aligned manner with respect to the sidewalls 57. The n-type low concentration layers 58 and 59 relax an electric field near the n-type drain region 53 and suppress a hot electron effect.
In the first embodiment, in the Ref circuit region 8, the impurity concentration of the channel region 45 of the depletion type MOSFET 4 and the impurity concentration of the channel region 55 of the enhancement type MOSFET 5 are equal to each other. On the other hand, the main portion of the polysilicon gate 46 of the depletion type MOSFET 4 is made of n-type polysilicon, whereas the main portion of the polysilicon gate 56 of the enhancement type MOSFET 5 is made of non-doped polysilicon.
Thus, there is a difference between the work function difference between the polysilicon gate 46 and the channel region 45 in the depletion type MOSFET 4 and the work function difference between the polysilicon gate 56 and the channel region 55 in the enhancement type MOSFET 5. Therefore, the threshold voltage Vth_D of the depletion type MOSFET 4 and the threshold voltage Vth_E of the enhancement type MOSFET 5 are made different. For example, the threshold voltage Vth_D is −1.0 V to −0.2 V, and the threshold voltage Vth_E is 0.2 V to 1.0 V. In
Although not shown, an interlayer insulating film that collectively covers the respective polysilicon gates 26, 36, 46 and 56 is laminated on the semiconductor substrate 6. Although not shown, on the interlayer insulating film, there are formed a plurality of source electrodes corresponding to the plurality of source regions 22, 32, 42 and 52, respectively, a plurality of drain electrodes corresponding to the plurality of drain regions 23, 33, 43 and 53, respectively, and a plurality of back gate electrodes corresponding to the plurality of back gate regions 24, 34, 44 and 54, respectively.
Although not shown, in the interlayer insulating film, there are formed vias for connecting the plurality of source regions 22, 32, 42 and 52 to their corresponding source electrodes, vias for connecting the plurality of drain regions 23, 33, 43 and 53 to their corresponding drain electrodes, and vias for connecting the plurality of back gate regions 24, 34, 44 and 54 to their corresponding back gate electrodes. The source electrode of the depletion type MOSFET 4 and the drain electrode of the enhancement type MOSFET 5 are integrally formed and connected on the interlayer insulating film.
Next, a semiconductor device 101 according to a first comparative example (hereinafter simply referred to as “first comparative example 101”) will be described. The first comparative example 101 includes a CMOS region and a Ref circuit region just like the semiconductor device 1 according to the first embodiment. The configuration of the CMOS region of the first comparative example 101 is the same as the configuration of the CMOS region 7 of the semiconductor device 1 according to the first embodiment.
The Ref circuit region 108 of the first comparative example 101 includes a depletion type MOSFET 4 and an enhancement type MOSFET 105. The configuration of the depletion type MOSFET 4 of the first comparative example 101 is the same as the configuration of the depletion type MOSFET 4 of the semiconductor device 1 according to the first embodiment.
The enhancement type MOSFET 105 of the first comparative example 101 differs from the enhancement type MOSFET 5 of the semiconductor device 1 according to the first embodiment in terms of the following points (A1) and (A2).
(A1) In the enhancement type MOSFET 105 of the first comparative example 101, no n-type impurity is implanted into the channel region 155. Therefore, in the first comparative example 101, the n-type impurity concentration of the channel region 45 of the depletion type MOSFET 4 and the n-type impurity concentration of the channel region 155 of the enhancement type MOSFET 105 are different from each other.
(A2) In the enhancement type MOSFET 105 of the first comparative example 101, the polysilicon gate 156 is made of n-type polysilicon. The n-type impurity contained in the polysilicon gate 1562 is P (phosphorus) in this example. That is, in the first comparative example 101, the polysilicon gate 46 of the depletion type MOSFET 4 and the polysilicon gate 156 of the enhancement type MOSFET 105 are both made of n-type polysilicon.
In the first comparative example 101, by providing a difference between the n-type impurity concentration of the channel region 45 of the depletion type MOSFET 4 and the n-type impurity concentration of the channel region 155 of the enhancement type MOSFET 105, the threshold voltage Vth_D of the depletion type MOSFET 4 and the threshold voltage Vth_E of the enhancement type MOSFET 105 are made different from each other.
In the first comparative example 101, the n-type impurity concentration of the channel region 45 of the depletion type MOSFET 4 is different from the n-type impurity concentration of the channel region 155 of the enhancement type MOSFET 105. Therefore, as shown in
Next, a semiconductor device 201 according to a second comparative example (hereinafter simply referred to as “second comparative example 201”) will be described. The second comparative example 201 includes a CMOS region and a Ref circuit region just like the semiconductor device 1 according to the first embodiment. The configuration of the CMOS region of the second comparative example 201 is the same as the configuration of the CMOS region 7 of the semiconductor device 1 according to the first embodiment.
The Ref circuit area 208 of the second comparative example 201 includes a depletion type MOSFET 4 and an enhancement type MOSFET 205. The configuration of the depletion type MOSFET 4 of the second comparative example 201 is the same as the configuration of the depletion type MOSFET 4 of the semiconductor device 1 according to the first embodiment.
The enhancement type MOSFET 205 of the second comparative example 201 differs from the enhancement type MOSFET 105 of the first comparative example 101 in terms of the following points (B1) and (B2).
(B1) In the enhancement type MOSFET 205 of the second comparative example 201, an n-type impurity is implanted into the channel region 55 as in the semiconductor device 1 according to the first embodiment. In the second comparative example 201, as in the semiconductor device 1 according to the first embodiment, the impurity concentration of the channel region 55 of the enhancement type MOSFET 205 is equal to the impurity concentration of the channel region 45 of the depletion type MOSFET 4.
(B2) In the enhancement type MOSFET 205 of the second comparative example 201, the main portion of the polysilicon gate 256 is made of p-type polysilicon instead of n-type polysilicon. Specifically, the polysilicon gate 256 includes n-type portions 271 arranged on both sides of the polysilicon gate 256 and made of n-type polysilicon, and a p-type portion 272 arranged between the n-type portions 271 and made of p-type polysilicon. The p-type impurity contained in the p-type portion 272 is B (boron) in this example. The p-type impurity concentration of the p-type portion 272 is 1×1019 cm−3 or more.
In the second comparative example 201, there is a difference between the work function of the polysilicon gate 46 in the depletion type MOSFET 4 and the work function of the polysilicon gate 256 in the enhancement type MOSFET 205. Thus, there is a difference between the work function difference between the polysilicon gate 46 and the channel region 45 in the depletion type MOSFET 4 and the work function difference between the polysilicon gate 256 and the channel region 55 in the enhancement type MOSFET 205. Therefore, the threshold voltage Vth_D of the depletion type MOSFET 4 and the threshold voltage Vth_E of the enhancement type MOSFET 5 are made different.
In the second comparative example 201, the n-type impurity concentration of the channel region 255 of the enhancement type MOSFET 205 is equal to the n-type impurity concentration of the channel region 45 of the depletion type MOSFET 4. Therefore, as shown in
However, in the second comparative example 201, the main portion (p-type portion 272) of the polysilicon gate 256 in the enhancement type MOSFET 205 contains a p-type impurity (boron (B) in this example). Therefore, the following problems may occur. That is, during the manufacturing process or the like, the p-type impurity in the polysilicon gate 256 of the enhancement type MOSFET 205 is diffused, thereby forming fixed charges or trap sites in the gate insulating film 13 or changing the impurity concentration in the channel region 255. As a result, variations in the manufacture and deterioration over time are more likely to occur.
In the semiconductor device 1 according to the first embodiment, the n-type impurity concentration of the channel region 55 of the enhancement type MOSFET 5 is equal to the n-type impurity concentration of the channel region 45 of the depletion type MOSFET 4. As a result, the slope of the Vg-Id characteristic of the depletion type MOSFET 4 and the slope of the Vg-Id characteristic of the enhancement type MOSFET 5 are substantially equal to each other. Therefore, the change in the reference voltage Vref due to the temperature can be suppressed as compared with the first comparative example 101.
Furthermore, in the semiconductor device 1 according to the first embodiment, the main portion (non-doped portion 72) of the polysilicon gate 56 of the enhancement type MOSFET 5 does not contain a p-type impurity. Therefore, as in the second comparative example, the diffusion of the p-type impurity in the polysilicon gate 256 of the enhancement type MOSFET 205 can be suppressed or prevented. Thus, in the semiconductor device 1 according to the first embodiment, variations in the manufacture and deterioration over time are less likely to occur as compared with the second comparative example 201.
First, as shown in
For example, the semiconductor device shown in
During the epitaxial growth of the base substrate 61, the n-type impurity and the p-type impurity implanted into the base substrate 61 are diffused in the growth direction of the n-type epitaxial layer 62. As a result, a buried layer 14 is formed at the boundary between the base substrate 61 and the n-type epitaxial layer 62. Further, a portion of the p-type element isolation portion 11 is thereby formed. Thereafter, a p-type impurity is selectively implanted into a portion of the n-type epitaxial layer 62. Then, the silicon of the base substrate 61 is further epitaxially grown while adding an n-type impurity. As a result, a semiconductor substrate 6 including the p-type base substrate 61 and the n-type epitaxial layer 62 is formed.
Thereafter, an n-type well 31 is formed by selectively implanting an n-type impurity into the surface layer region of the n-type epitaxial layer 62. Furthermore, p-type wells 21, 41 and 51 are formed by selectively implanting a p-type impurity into the surface layer region of the n-type epitaxial layer 62. Next, a field insulating biofilm 12 is formed on the semiconductor substrate 6. Next, n-type impurity diffusion regions 345 and 355 are formed by selectively implanting an n-type impurity into the surface layer region of the n-type epitaxial layer 62. Thereafter, a gate insulating film 13 is formed.
Next, as shown in
Specifically, first, as shown in
Next, as shown in
Next, an insulating film such as a silicon oxide film or the like is formed over the entire surface of the semiconductor substrate 6 on the first main surface 62a side by a CVD method, and then the insulating film is etched back by dry etching. By performing the etching-back until the respective non-doped gates 326, 336, 346 and 356 are exposed, sidewalls 27, 37, 47 and 57 are formed on both sides thereof.
Next, as shown in
Then, n-type impurity ions (e.g., P+ ions) are implanted into the non-doped gates 326 and 346, both sides of the non-doped gate 356, and the n-type epitaxial layer 62 through the resist film 82. Thereafter, the resist film 82 is removed.
As a result, as shown in
Next, as shown in
As a result, a p-type polysilicon gate 36, a p-type source region 32, a p-type drain region 33, and p-type back gate regions 24, 44 and 54 are formed. Thus, a semiconductor device 1 as shown in
In
The circuit diagram of the semiconductor device 401 according to the second embodiment of the present disclosure is similar to the circuit diagram (
The semiconductor device 401 according to the second embodiment of the present disclosure includes a CMOS region and a Ref circuit region just like the semiconductor device 1 according to the first embodiment. The configuration of the CMOS region 7 of the semiconductor device 401 according to the second embodiment is the same as the configuration of the CMOS region 7 of the semiconductor device 1 according to the first embodiment.
The Ref circuit region 408 of the semiconductor device 401 according to the second embodiment includes a depletion type MOSFET 4 and an enhancement type MOSFET 405. The configuration of the depletion type MOSFET 4 of the semiconductor device 401 according to the second embodiment is the same as the configuration of the depletion type MOSFET 4 of the semiconductor device 1 according to the first embodiment.
The enhancement type MOSFET 405 of the semiconductor device 401 according to the second embodiment differs from the enhancement type MOSFET 5 of the semiconductor device 1 according to the first embodiment in that the main portion of the polysilicon gate 456 is made of p-type polysilicon.
Specifically, the polysilicon gate 456 includes n-type portions 471 on both sides of the polysilicon gate 456 and a p-type portion 472 between the n-type portions 471. The n-type portions 471 are made of n-type polysilicon. The p-type portion 472 is made of p-type polysilicon. The p-type impurity contained in the p-type portion 472 is boron (B) in this embodiment.
The p-type impurity concentration of the p-type portion 472 is lower than the p-type impurity concentration of the p-type portion 272 (see
In the semiconductor device 401 according to the second embodiment, as in the semiconductor device 1 according to the first embodiment, the n-type impurity concentration of the channel region 55 of the enhancement type MOSFET 405 is equal to the n-type impurity concentration of the channel region 45 of the depletion type MOSFET 4. Therefore, the slope of the Vg-Id characteristic of the depletion type MOSFET 4 and the slope of the Vg-Id characteristic of the enhancement type MOSFET 405 are substantially equal to each other. Therefore, the change in the reference voltage Vref due to the temperature can be suppressed as compared with the first comparative example 101.
Furthermore, in the semiconductor device 401 according to the second embodiment, the main portion (p-type portion 472) of the polysilicon gate 456 of the enhancement type MOSFET 5 contains a p-type impurity. However, the p-type impurity concentration thereof is lower than the p-type impurity concentration of the main portion (p-type portion 272) of the polysilicon gate 256 of the second comparative example 201. As a result, the diffusion of the p-type impurity in the polysilicon gate 456 of the enhancement type MOSFET 405 is suppressed as compared with the second comparative example. Therefore, variations in the manufacture and deterioration over time are less likely to occur as compared with the second comparative example 201.
The entire polysilicon gate 456 is made of p-type polysilicon. Even in this case, the concentration of the p-type impurity contained in the polysilicon gate 456 may be 1×1017 cm−3 or less.
First, as shown in
Next, as shown in
Next, as shown in
Next, the polysilicon film 81 is patterned by photolithography. As a result, as shown in
Next, as shown in
Next, an insulating film such as a silicon oxide film or the like is formed over the entire surface of the semiconductor substrate 6 on the first main surface 62a side by a CVD method, and then the insulating film is etched back by dry etching. This etching-back is performed until the respective non-doped gates 326, 336 and 346 and the p-type gate 356A are exposed, thereby forming sidewalls 27, 37, 47 and 57 on both sides thereof.
Next, as shown in
Then, n-type impurity ions (e.g., P+ ions) are implanted into the non-doped gates 326 and 346, both sides of the p-type gate 356A, and the n-type epitaxial layer 62 through the resist film 85. Thereafter, the resist film 85 is removed.
As a result, as shown in
Next, as shown in
Thus, a p-type polysilicon gate 36, a p-type source region 32, a p-type drain region 33, and p-type back gate regions 24, 44 and 54 are formed. As a result, a semiconductor device 401 as shown in
The semiconductor device 501 according to the first modification (hereinafter referred to as “first modification 501”) differs from the semiconductor device 1 according to the first embodiment in terms of the configuration and internal structure of the semiconductor substrate 6.
In the first modification 501, the semiconductor substrate 6 includes a base substrate 61, a p-type epitaxial layer 63, an n-type region 65, and an n-type region 66. The p-type epitaxial layer 63 has a first main surface 63a on the opposite side to the base substrate 61, and a second main surface 63b on the opposite side to the first main surface 63a.
The p-type epitaxial layer 63 is formed on the semiconductor substrate 6. In the CMOS region 7, the n-type buried layer 14 is formed so as to straddle the boundary between the base substrate 61 and the p-type epitaxial layer 63. In the Ref circuit region 8, the n-type buried layer 14 is formed so as to straddle the boundary between the base substrate 61 and the p-type epitaxial layer 63.
In the CMOS region 7, the n-type region 65 is formed in the surface layer region of the p-type epitaxial layer 63 and above the n-type buried layer 14. In the Ref circuit region 8, the n-type region 66 is formed in the surface layer region of the p-type epitaxial layer 63 and above the n-type buried layer 14. The element isolation portion 11 is formed of a p-type epitaxial layer 63.
A p-type well 21 and an n-type well 31 are formed in the surface layer region of the n-type region 65, and a p-type well 41 and a p-type well 51 are formed in the surface layer region of the n-type region 66.
The configuration and internal structure of the semiconductor substrate 6 according to the first modification 501 may also be applied to the semiconductor device 401 according to the second embodiment.
The semiconductor device 601 according to the second modification (hereinafter referred to as “second modification 601”) differs from the semiconductor device 1 according to the first embodiment in terms of the configuration and internal structure of the semiconductor substrate 6.
In the first modification 601, the semiconductor substrate 6 includes a base substrate 61, and a p-type epitaxial layer 67 formed on the base substrate 61. The p-type epitaxial layer 67 has a first main surface 67a on the opposite side to the base substrate 61, and a second main surface 67b on the opposite side to the first main surface 67a.
In the CMOS region 7, a deep n-type well (DNW) 91 is formed in the intermediate thickness portion of the p-type epitaxial layer 67. In CMOS region 7, a p-type well 21 and an n-type well 31 are formed in a region between the deep n-type well 91 and the first main surface 67a of the p-type epitaxial layer 67.
Further, an n-type region 92 that covers the side surface of the p-type well 21 opposite to the n-type well 31 is formed in a region between the deep n-type well 91 and the first main surface 67a of the p-type epitaxial layer 67.
In the Ref circuit region 8, a deep n-type well (DNW) 93 is formed in the intermediate thickness portion of the p-type epitaxial layer 67. In the Ref circuit region 8, a p-type well 41 and a p-type well 51 are formed in a region between the deep n-type well 93 and the first main surface 67a of the p-type epitaxial layer 67.
Further, an n-type region 94 that covers the side surface of the p-type well 41 opposite to the p-type well 51, an n-type region 95 arranged between the p-type well 41 and the p-type well 51, and an n-type region 96 that covers the side surface of the p-type well 51 on the side opposite to the p-type well 41 are formed in a region between the deep n-type well 93 and the first main surface 67a of the p-type epitaxial layer 67.
The configuration and internal structure of the semiconductor substrate 6 according to the second modification 601 may also be applied to the semiconductor device 401 according to the second embodiment.
The semiconductor device 701 according to the third modification (hereinafter referred to as “third modification 701”) differs from the semiconductor device 1 according to the first embodiment in terms of the configuration and internal structure of the semiconductor substrate 6.
In the second modification 601, the semiconductor substrate 6 is composed of only a p-type semiconductor substrate 68. The p-type semiconductor substrate 68 has a first main surface 68a on which p-type wells 21, 41 and 51 and an n-type well 31 are formed, and a second main surface 68b on the opposite side to the first main surface 68a.
In the CMOS region 7, a deep n-type well (DNW) 91 is formed in the intermediate thickness portion of the p-type semiconductor substrate 68 (semiconductor substrate 6). In the CMOS region 7, a p-type well 21 and an n-type well 31 are formed in a region between the deep n-type well 91 and the first main surface 68a of the p-type semiconductor substrate 68.
Further, an n-type region 92 that covers the side surface of the p-type well 21 opposite to the n-type well 31 is formed in a region between the deep n-type well 91 and the first main surface 68a of the p-type semiconductor substrate 68.
In the Ref circuit region 8, a deep n-type well (DNW) 93 is formed in the intermediate thickness portion of the p-type semiconductor substrate 68. In the Ref circuit region 8, a p-type well 41 and a p-type well 51 are formed in a region between the deep n-type well 93 and the first main surface 68a of the p-type semiconductor substrate 68.
Further, an n-type region 94 that covers the side surface of the p-type well 41 opposite to the p-type well 51, an n-type region 95 arranged between the p-type well 41 and the p-type well 51, and an n-type region 96 that covers the side surface of the p-type well 51 on the side opposite to the p-type well 41 are formed in a region between the deep n-type well 93 and the first main surface 68a of the p-type semiconductor substrate 68.
The configuration and internal structure of the semiconductor substrate 6 according to the third modification 701 may also be applied to the semiconductor device 401 according to the second embodiment.
Although the first embodiment, the second embodiment, the first modification, the second modification, and the third modification have been described above, the present disclosure may be implemented in other forms as well.
In the first embodiment described above, the polysilicon gate 56 of the enhancement type MOSFET 5 includes n-type portions 71 on both sides and a non-doped portion 72 between the n-type portions 71. The reason why the n-type portions 71 on both sides are formed will be described.
When forming the n-type source region 52 and the n-type drain region 53 of the enhancement type MOSFET 5, as shown on the left side in
At this time, if one side or both sides of the resist film 82 is formed to protrude outward from the sidewalls 57, one or both of the n-type source region 22 and the n-type drain region 23 is not formed in a self-aligned manner with respect to the sidewalls 27. If this happens, the characteristics of the enhancement type MOSFET 5 will be changed.
Therefore, in order to prevent both sides of the resist film 82 from protruding beyond the sidewalls 57, as shown on the left side in
In the semiconductor device 1 according to the first embodiment, the n-type portions 71 may not be formed on both sides of the polysilicon gate 56. That is, the entire polysilicon gate 56 may be made of non-doped polysilicon. In order to obtain such a configuration, the enhancement type MOSFET 5 may have the following structure.
For example, as shown in
In order to form the n-type source region 52 and the n-type drain region 53 of the enhancement type MOSFET 5, the resist film 82 is formed so that both sides of the resist film 82 are located between the outer edges of the sidewalls 57 on the corresponding sides and the outer edges of the gate insulating films 801 and 802 on the corresponding sides. N-type impurity ions (e.g., P+ ions) are implanted into the p-type well 51 through the resist film 82.
In this case, since the entire non-doped gate 356 is covered with the resist film 82, n-type portions 71 are not formed on both sides of the non-doped gate 356. Further, in this case, since the n-type source region 52 and the n-type drain region 53 are formed in a self-aligned manner with respect to the gate insulating films 801 and 802, variations in the characteristics of the enhancement type MOSFET 5 are less likely to occur.
As shown in
The configurations shown in
Although the embodiments of the present disclosure have been described in detail above, these are nothing more than specific examples used to clarify the technical content of the present disclosure. The present disclosure should not be construed as being limited to these specific examples. Rather, the scope of the present disclosure is limited only by the claims appended hereto.
The features described below as supplementary notes can be extracted from the description of this specification and the drawings.
An enhancement type MOSFET (5), comprising:
An enhancement type MOSFET (405), comprising:
The enhancement type MOSFET (5 or 405) of [Supplementary Note 1-1] or [Supplementary Note 1-2], wherein the channel region (55) contains an n-type impurity.
The enhancement type MOSFET (5 or 405) of any one of [Supplementary Note 1-1] to [Supplementary Note 1-3], wherein the polysilicon gate (56 or 456) includes n-type portions (71 or 471) formed on both sides of the polysilicon gate and made of n-type polysilicon.
The enhancement type MOSFET (5 or 405) of any one of [Supplementary Note 1-1] to [Supplementary Note 1-4], wherein, in the surface layer region of the p-type region (51), two n-type low concentration regions (58 and 59) having a lower n-type impurity concentration than both of the n-type source region (52) and the n-type drain region (53) are disposed between the n-type source region (52) and the polysilicon gate (56 or 456) and between the n-type drain region (53) and the polysilicon gate (56 or 456), and
The enhancement type MOSFET (5 or 405) of any one of [Supplementary Note 1-1] to [Supplementary Note 1-5], further comprising:
The enhancement type MOSFET (5 or 405) of [Supplementary Note 1-6], wherein the two n-type low concentration regions (58 and 59) are formed in a region directly below the sidewalls (57).
A semiconductor device (1), comprising:
A semiconductor device (401), comprising:
The semiconductor device of [Supplementary Note 1-8] or [Supplementary Note 1-9], wherein the polysilicon gate (56 or 456) includes n-type portions (71 or 471) formed on both sides of the polysilicon gate and made of n-type polysilicon.
The semiconductor device of any one of [Supplementary Note 1-8] to [Supplementary Note 1-10], wherein in the surface layer region of the second p-type region (51), two second n-type low concentration regions (58 and 59) having a lower n-type impurity concentration than both of the second n-type source region (52) and the second n-type drain region (53) are disposed between the second n-type source region (52) and the second polysilicon gate (56 or 456) and between the second n-type drain region (53) and the second polysilicon gate (56 or 456), and
The semiconductor device of [Supplementary Note 1-11], further comprising:
The semiconductor device of [Supplementary Note 1-12], wherein the two second n-type low concentration regions (58 and 59) are formed in a region directly below the second sidewalls (57).
The semiconductor device of any one of [Supplementary Note 1-8] to [Supplementary Note 1-10], wherein, in the surface layer region of the first p-type region (41), two first n-type low concentration regions (48 and 49) having a lower n-type impurity concentration than both of the first n-type source region (42) and the first n-type drain region (43) are disposed between the first n-type source region (42) and the first polysilicon gate (46) and between the first n-type drain region (43) and the first polysilicon gate (46), and
The semiconductor device of [Supplementary Note 1-14], further comprising:
The semiconductor device of [Supplementary Note 1-15], wherein the two first n-type low concentration regions (48 and 49) are formed in a region directly below the first sidewalls (57).
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the contents of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and contents of the disclosures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-028556 | Feb 2023 | JP | national |
