Claims
- 1. A flash memory device comprising:
an array of memory cells arranged in rows and columns; sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array; and addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
- 2. The non-volatile memory device of claim 1 wherein the array comprises X columns divided into Y pages, and the erase blocks are X columns wide and Z rows long.
- 3. The non-volatile memory device of claim 2 wherein each erase block comprises at least X*Y memory cells having linear addresses.
- 4. The non-volatile memory device of claim 2 wherein X=512 and Y=4.
- 5. The non-volatile memory device of claim 1 wherein the memory cells are floating gate memory cells.
- 6. A flash memory comprising:
an array of memory cells arranged in rows and columns; sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array; and erase circuitry to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages.
- 7. The flash memory of claim 6 wherein the memory cells are floating gate memory cells.
- 8. The flash memory device of claim 6 further comprising addressing circuitry to access the array, wherein addresses of the memory cells are scrambled such that each erase block contains linear addresses.
- 9. A flash memory device comprising:
an array of floating gate memory cells arranged in rows and columns; sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array; erase circuitry to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages; and addressing circuitry to access the array, wherein addresses of the memory cells are scrambled such that each erase block contains linear addresses.
- 10. The flash memory device of claim 9 wherein the array comprises 512 columns divided into 4 pages of 128 columns, and the erase blocks are 512 columns wide.
- 11. The flash memory device of claim 9 wherein the array is divided into four erase blocks.
- 12. The flash memory device of claim 11 wherein erase block one contains addresses 0 000 0h to 0 FF FCh, erase block two contains addresses 0 000 01h to 0 FF FDh, erase block three contains addresses 0 000 02h to 0 FF FDh, and erase block four contains addresses 0 000 03h to 0 FF FFh.
- 13. A processing system comprising:
a processor; and a non-volatile memory coupled to communicate with the processor, the nonvolatile memory comprises:
an array of floating gate memory cells arranged in a plurality of addressable banks containing addressable blocks of memory cells; a plurality of erase blocks spanning multiple ones of the plurality of addressable banks; sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array; and addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
- 14. The processing system of claim 13 wherein the array comprises X columns divided into Y pages, and the erase blocks are X columns wide and Z rows long.
- 15. The processing system of claim 14 wherein each erase block comprises at least X*Y memory cells having linear addresses.
- 16. A non-volatile memory device, comprising:
an array of floating gate memory cells arranged in rows and columns and having a plurality of addressable banks containing addressable blocks of memory cells; sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array; and addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
- 17. The non-volatile memory device of claim 16 wherein the array comprises X columns divided into Y pages, and the erase blocks are X columns wide and Z rows long.
- 18. The non-volatile memory device of claim 17 wherein each erase block comprises at least X*Y memory cells having linear addresses.
- 19. The non-volatile memory device of claim 2 wherein X=512 and Y=4.
- 20. A non-volatile memory device, comprising:
an array of floating gate memory cells arranged in a plurality of addressable banks containing addressable blocks of memory cells; a plurality of erase blocks spanning multiple ones of the plurality of addressable banks; sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array; and addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
- 21. The non-volatile memory device of claim 20 wherein the array comprises X columns divided into Y pages, and the erase blocks are X columns wide and Z rows long.
- 22. The non-volatile memory device of claim 21 wherein each erase block comprises at least X*Y memory cells having linear addresses.
- 23. The non-volatile memory device of claim 21 wherein X=512 and Y=4.
- 24. A method of arranging an erase block architecture for a non-volatile memory, comprising:
providing a plurality of addressable banks of memory cells in an array; providing a plurality of erase blocks, each erase block spanning at least two of the plurality of addressable banks
- 25. The method of claim 24, and further comprising scrambling pages such that adjacent pages contain serialized addresses
- 26. A method of erasing in a non-volatile memory, comprising:
defining erase blocks that span a plurality of pages within a memory array; erasing portions of each of a plurality of pages within a memory array without data loss.
- 27. The method of claim 26, wherein defining erase blocks comprises scrambling address locations within each page of a memory array.
RELATED APPLICATION
[0001] This is a continuation application of U.S. patent application Ser. No. 10/100,856, filed Mar. 19, 2002 (allowed), titled “ERASE BLOCK ARCHITECTURE FOR NON-VOLATILE MEMORY” and commonly assigned, the entire contents of which are incorporated herein by reference.
Continuations (1)
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Number |
Date |
Country |
Parent |
10100856 |
Mar 2002 |
US |
Child |
10376936 |
Feb 2003 |
US |