ERROR CORRECTION CODE CIRCUIT, MEMORY DEVICE INCLUDING ERROR CORRECTION CODE CIRCUIT, AND OPERATION METHOD OF ERROR CORRECTION CODE

Abstract

A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0166030, filed Dec. 1, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND

Embodiments of the present disclosure described herein relate to integrated circuit devices and, more particularly, to integrated circuit memory devices having error correction capability and methods of operating same.

A semiconductor memory device may include a volatile memory device, in which stored data disappear when a power supply is turned off, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), and a nonvolatile memory device, in which stored data are retained even when a power supply is turned off, such as a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM). As will be understood by those skilled in the art, a DRAM is widely used as a system memory, a buffer memory, or a working memory of a computing system.

In addition, as the degree of integration of a DRAM is increased, the size of each of memory cells decreases, and a frequency of data errors in the memory cells increases. Accordingly, various error correction techniques for correcting errors in a DRAM device are being developed.

SUMMARY

Embodiments of the present disclosure provide an error correction code having improved reliability, but with simplified structure, and a memory device including the error correction code, and an operating method of the error correction code.

According to an embodiment, a memory device includes a memory cell array and an error correction code (ECC) circuit that corrects an error of a data code read out from the memory cell array. The ECC circuit includes a syndrome calculating unit that operates with a plurality of syndromes based on the data code and an H-matrix, an error location detecting unit that generates an error vector based on the plurality of syndromes, and an error correcting unit that corrects an error of the data code based on the error vector and to output corrected data. The error location detecting unit is configured to generate a 0-th error vector element corresponding to a 0-th field element by performing a 0-th error location operation on the 0-th field element among a plurality of field elements based on an error location polynomial, and to generate a first error vector element corresponding to a first field element based on a result of the 0-th error location operation.

According to an embodiment, an ECC circuit configured to correct an error of a data code stored in a memory device includes a syndrome generating unit that generates a plurality of syndromes based on the data code read out from the memory device and a H-matrix, an error location detecting unit that generates an error vector based on the plurality of syndromes and a plurality of field elements of the H-matrix, and an error correcting unit that corrects an error of the data code based on the error vector. The error location detecting unit includes a coefficient calculator that generates a plurality of coefficients used in an error location polynomial based on the plurality of syndromes, and an error vector generator that generates the error vector based on the plurality of coefficients. The error vector generator includes a plurality of pair checkers configured to perform an error location operation on a plurality of pairs. The plurality of pairs includes at least two field elements among the plurality of field elements. The at least two field elements included in each of the plurality of pairs may satisfy a predetermined condition.

According to an embodiment, an operating method of an ECC circuit includes generating a plurality of syndromes based on a data code, generating an error vector based on the plurality of syndromes, and correcting an error of the data code based on the error vector. The generating of the error vector includes generating a first error vector element corresponding to a first field element by performing an error location operation on the first field element based on the plurality of syndromes and generating a second error vector element corresponding to a second field element based on a result of an error location operation on the first field element. The first field element and the second field element may be set to satisfy a predetermined rule.

According to an embodiment, a configuring method of an ECC circuit includes determining a H-matrix composed of a plurality of field elements based on a length of a data code and an error correction capability, configuring the plurality of field elements of the H-matrix into a plurality of pairs based on a predetermined rule, and configuring an error location detecting unit based on the plurality of pairs. Each of the plurality of pairs includes at least two field elements among the plurality of field elements, and the at least two field elements included in each of the plurality of pairs are determined to satisfy the predetermined rule. The error location detecting unit includes a plurality of pair checkers configured to generate at least two error vector elements corresponding to each of the plurality of pairs.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure.

FIG. 2 is a block diagram showing a memory device of FIG. 1.

FIG. 3 is a diagram for describing an operation of the ECC circuit of FIG. 2.

FIG. 4 is a block diagram for describing a configuration of the ECC circuit of FIG. 3.

FIG. 5A shows an example of a Galois field for designing a code used by the ECC circuit of FIG. 4.

FIG. 5B shows an example of an H-matrix used by the ECC circuit of FIG. 4.

FIG. 6 is a block diagram showing an error location detecting unit of FIG. 4.

FIGS. 7A to 7C are diagrams showing a configuration of the error vector generator of FIG. 6.

FIG. 8 is a block diagram showing a structure of an error vector generator of FIG. 6.

FIG. 9 is a block diagram showing a pair checker of FIG. 8.

FIG. 10 is a diagram for describing field elements respectively operated by a plurality of pair checkers of FIG. 8.

FIG. 11 is a block diagram showing an error location detecting unit of FIG. 6.

FIG. 12 is a block diagram showing one of a plurality of pair checkers of FIG. 11.

FIGS. 13 and 14 are block diagrams showing a pair checker included in an error vector generator of FIG. 6.

FIG. 15 is a flowchart illustrating an operation of a memory device of FIG. 2.

FIG. 16 is a flowchart showing a method for designing an ECC decoder, according to an embodiment of the present disclosure.

FIG. 17 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure.

FIG. 18 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure.

FIG. 19 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure.

FIG. 20 is a diagram showing some examples of a memory package, according to an embodiment of the present disclosure.

FIG. 21 is a diagram showing some examples of a memory package, according to an embodiment of the present disclosure.

FIG. 22 is a block diagram illustrating a memory module to which a memory device according to an embodiment of the present disclosure is applied.

FIG. 23 is a diagram showing a system to which a storage device according to an embodiment of the present disclosure is applied.

DETAILED DESCRIPTION

The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components. In addition, the term “unit” may include hardware circuitry for performing respective functions of a semiconductor system and/or device, and/or include one or more computer readable programs for performing respective functions herein.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure. Referring to FIG. 1, a memory system 10 may include a memory controller 11 and a memory device 100. In an embodiment, the memory system 10 may be one of information processing devices, which are configured to process a variety of information and to store the processed information, such as a personal computer (PC), a laptops, a server, a workstation, a smartphone, a tablet PC, a digital camera, and a black box. Alternatively, the memory system 10 may be a storage medium such as a solid state drive (SSD), and the memory device 100 may be used as a buffer memory of the SSD. However, the scope of the present disclosure is not limited thereto, and the memory system 10 may be implemented in various forms.

The memory controller 11 may store data in the memory device 100 or may read out data stored in the memory device 100. For example, the memory controller 11 may transmit a clock signal CK and a command/address signal CA to the memory device 100 and may exchange a data signal DQ and a data strobe signal DQS with the memory device 100. In an embodiment, through the data signal DQ and the data strobe signal DQS, data DATA may be transmitted from the memory controller 11 to the memory device 100 or may be transmitted from the memory device 100 to the memory controller 11. In an embodiment, the memory controller 11 and the memory device 100 may communicate with each other based on a DDR interface or an LPDDR interface, but the scope of the present disclosure is not limited thereto.

The memory device 100 may operate under control of the memory controller 11. In an embodiment, the memory device 100 may be a dynamic random access memory (DRAM) device, but the scope of the present disclosure is not limited thereto. For example, the memory device 100 may include a volatile memory such as an SRAM or a non-volatile memory such as a flash memory, a PRAM, and/or an RRAM.

In an embodiment, the memory device 100 may include an error correction code (ECC) circuit 110. The ECC circuit 110 may be configured to detect and correct an error(s) within data stored in the memory device 100. For example, the ECC circuit 110 may generate parity data by performing ECC encoding on first data received from the memory controller 11. The memory device 100 may store first data received from the memory controller 11 and parity data generated by the ECC circuit 110 together. While the memory device 100 is running, an error may occur in the first data stored in the memory device 100 due to various factors. When a read request for the first data is generated by the memory controller 11, the ECC circuit 110 may correct an error generated in the first data by performing ECC decoding based on the first data and the parity data corresponding to the first data. The memory device 100 may transmit the corrected first data to the memory controller 11.

In an embodiment, the ECC circuit 110 may correct errors within a predetermined error correction capability. When an error(s) occurring within data exceeds the error correction capability of the ECC circuit 110, the errors may not be corrected. As an example, an ECC circuit included in a DRAM device is configured to correct a 1-bit error. On the other hand, as the size of a DRAM device continues to become smaller, the number of error bits occurring in the DRAM device is increasing. Accordingly, the error correction capability of the ECC circuit 110 needs to be improved; however, when the error correction capability of the ECC circuit 110 is improved, the structure of the ECC circuit 110 may become too complicated.

In the present disclosure, an ECC circuit 110 having improved error correction capability and a relatively simple structure is provided. Embodiments of the ECC circuit 110 according to an embodiment of the present disclosure will be described with reference to the following drawings.

FIG. 2 is a block diagram showing a memory device of FIG. 1. Referring to FIGS. 1 and 2, the memory device 100 includes the ECC circuit 110, a memory cell array 120, a command/address (CA) buffer 130, an address decoder 140, a command decoder 150, a sense amplifier and write driver (S/A & W/D) 160, and an I/O circuit 170. The ECC circuit 110 may generate parity data by performing ECC encoding on data to be stored in the memory cell array 120. Alternatively, the ECC circuit 110 may correct an error of the data by performing ECC decoding based on the data and the parity data, which are read from the memory cell array 120. A configuration and an operation of the ECC circuit 110 will be more fully described with reference to the following drawings.

The memory cell array 120 may include a plurality of memory cells. The plurality of memory cells may be connected with a plurality of word lines and a plurality of bit lines. In an embodiment, the plurality of word lines may be driven by an X-decoder (or a row decoder) (X-DED), whereas the plurality of bit lines may be driven by a Y-decoder (or a column decoder) (Y-DEC). The CA buffer 130 may be configured to receive command/address signals CA and to temporarily store or buffer the received signals. The address decoder 140 may decode address signals ADDR stored in the CA buffer 130. The address decoder 140 may control the X-decoder and the Y-decoder based on the decoding result.

The command decoder 150 may decode a command CMD stored in the CA buffer 130. The command decoder 150 may control components of the memory device 100 based on the decoded result. For example, when a command signal stored in the CA buffer 130 is a write command (i.e., when a command received from the memory controller 11 is a write command), the command decoder 150 may control (i.e., perform ECC encoding) the ECC circuit 110 and may control (i.e., activate a write driver) an operation of the S/A & W/D 160 such that the data DATA received through the I/O circuit 170 is written into the memory cell array 120. In contrast, when a command signal stored in the CA buffer 130 is a read command (i.e., when a command received from the memory controller 11 is a read command), the command decoder 150 may control (i.e., preform ECC decoding) the ECC circuit 110 and may control (i.e., activate a sense amplifier) an operation of the S/A & W/D 160 such that data stored in the memory cell array 120 is read.

Under control of the command decoder 150, the S/A & W/D 160 may read out data from the memory cell array 120 through a plurality of bit lines or may write data into the memory cell array 120 through the plurality of bit lines. On the basis of the data signal DQ and the data strobe signal DQS, the I/O circuit 170 may receive the data DATA from the memory controller 11 or may transmit the data DATA to the memory controller 11.

FIG. 3 is a diagram for describing an operation of the ECC circuit of FIG. 2. For the sake of brevity and for ease of description, components that are unnecessary for describing an operation of the ECC circuit 110 are omitted to avoid redundancy. Referring to FIGS. 2 and 3, the ECC circuit 110 may include an ECC encoder ECC-ENC and an ECC decoder ECC-DEC. The ECC encoder ECC-ENC may generate the parity data PRT by performing ECC encoding on write data WDT to be stored in the memory cell array 120. For example, with regard to the write data WDT of 128 b, the ECC encoder ECC-ENC may generate the parity data PRT of 8 b by using basis bits BB of 8 b. The write data WDT and the parity data PRT may be stored in the memory cell array 120 through the S/A & W/D 160. In contrast, the ECC decoder ECC-DEC may output read data RDT_COR, in which an error is corrected, by performing ECC decoding based on read data RDT and the previously generated parity data PRT, which are read from the memory cell array 120.

FIG. 4 is a block diagram for describing a configuration of the ECC circuit of FIG. 3. Hereinafter, for convenience of description, it is assumed that the ECC circuit 110 may correct a 2-bit error. It is assumed that the ECC circuit 110 operates based on a Bose-Chaudhuri-Hocquenghem (BCH) code. However, the scope of the present disclosure is not limited thereto.

Referring to FIGS. 3 and 4, the ECC circuit 110 may include a syndrome calculating unit 111, an error location detecting unit 112, and an error correcting unit 113. The syndrome calculating unit 111 may calculate a syndrome S_y based on the read data RDT and the parity data PRT, which are read from the memory cell array 120. For example, the syndrome calculating unit 111 may generate the syndrome S_y by multiplying an H-matrix H-MAT by a data code including the read data RDT and the parity data PRT. In an embodiment, the syndrome S_y may include vectors or bit columns including a plurality of bits depending on an implementation method of the ECC circuit 110. In an embodiment, according to the implementation method of the ECC circuit 110, there may be a plurality of syndromes S_y.

The error location detecting unit 112 may detect an error location generated in the read data RDT and the parity data PRT based on the syndrome S_y and the H-matrix H-MAT and may generate an error vector ERV based on the detected error location. For example, the error location detecting unit 112 may generate an error location polynomial based on the syndrome S_y. The error location detecting unit 112 may extract a plurality of field elements from the H-matrix H-MAT and may determine a solution of the error location polynomial from the plurality of field elements. The error location detecting unit 112 may generate the error vector ERV based on the solution of the error location polynomial.

The error correcting unit 113 may be configured to correct an error of the read data RDT based on the error vector ERV and to output the corrected read data RDT_COR. In an embodiment, the error location detecting unit 112 may be configured to search for or calculate the solution of the error location polynomial based on a Chien-search algorithm. In this case, the error location detecting unit 112 according to an embodiment of the present disclosure may be configured to generate a pair for the plurality of field elements and to search for, or calculate, the solution of the error location polynomial in units of pair thus generated. In this case, the structure may be simplified without degrading the performance of the error location detecting unit 112 (i.e., the ECC circuit 110 or ECC decoder). Hereinafter, the error location detecting unit 112 according to embodiments of the present disclosure will be more fully described with reference to the following drawings.

FIG. 5A shows an example of a Galois field for designing or forming a code used by the ECC circuit of FIG. 4. FIG. 5B shows an example of an H-matrix used by the ECC circuit of FIG. 4. In an embodiment, the ECC circuit 110 configured to correct a 2-bit error may use a BCH code. In this case, the H-matrix H-MAT used in the ECC circuit 110 that is capable of correcting a 2-bit error may be designed or formed based on field elements of a Galois field. For example, when a code having a code length of 31 bits is designed, field elements defined by a Galois field GF(2⁵) may be used. FIG. 5A shows an example of field elements α⁰ to α³¹ defined by the Galois field GF(2⁵). The Galois field GF(2⁵) shown in FIG. 5A may be defined by a formula of “x⁵+x²+1”. In an embodiment, field elements α⁰ to α³¹ of the Galois field GF(2⁵) shown in FIG. 5A are provided as examples for describing embodiments of the present disclosure, and the scope of the present disclosure is not limited thereto.

As shown in FIG. 5A, one field element (e.g., each of α⁰ to α³¹) may be expressed as a 5-bit binary vector [b4, b3, b2, b1, b0]. In this case, a binary vector of each field element may be determined by a field value shown in FIG. 5A. According to an embodiment, the H-matrix H-MAT may be generated or designed by using the field elements α⁰ to α³¹ of the Galois field GF(2⁵) as shown in FIG. 5A. For example, the H-matrix H-MAT for a data code having a length of 31 bits may be designed as shown in FIG. 5B. As shown in FIG. 5B, the H-matrix H-MAT may include an upper portion matrix H_U and a lower portion matrix H_L. The upper portion matrix H_U may have a structure in which the field elements α⁰ to α³¹ of the Galois field GF(2⁵) are sequentially arranged in a column direction.

The lower portion matrix H_L may be designed based on the upper portion matrix H_U. For example, each column of the lower portion matrix H_L may be designed based on the corresponding column of the upper portion matrix H_U. In more detail, the 0-th field element α⁰ is arranged in the 0-th column of the upper portion matrix H_U. The 0-th field element α⁰ is arranged in the 0-th column of the lower portion matrix H_L. The first field element α¹ is arranged in the first column of the upper portion matrix H_U. The third field element α³ is arranged in the first column of the lower portion matrix H_L. The second field element α² is arranged in the second column of the upper portion matrix H_U. The sixth field element α⁶ is arranged in the second column of the lower portion matrix H_L. The i-th field element αⁱ is arranged in the i-th column of the upper portion matrix H_U. The 3i-th field element α³ⁱ is arranged in the i-th column of the lower portion matrix H_L. The 30th field element α³⁰ is arranged in the 30th column of the upper portion matrix H_U. A 90th field element α⁹⁰ is arranged in the 30th column of the lower portion matrix H_L.

In an embodiment, as shown in FIG. 5A, the 31st field element α³¹ is the same as the 0-th field element α⁰. That is, field elements after the 31st field element α³¹ may be determined to circulate the 0-th to 30th field elements α⁰ to α³⁰ (e.g., α³¹=α⁰, α³²=α¹, α³³=α², or the like). Thus, based on this example, the 90th field element α⁹⁰ may correspond to the 28th field element α²⁸.

The Galois field GF(2⁵) and the H-matrix H-MAT described with reference to FIGS. 5A and 5B are simple examples for easily describing embodiments of the present disclosure, and the scope of the present disclosure is not limited thereto. It will be understood that the design of the H-matrix H-MAT may be modified in various ways depending on the implementation method of the ECC circuit 110, an error correction capability, a length of a data code, or the like.

FIG. 6 is a block diagram showing an error location detecting unit of FIG. 4. FIGS. 7A to 7C are diagrams showing a configuration of the error vector generator of FIG. 6. Referring to FIGS. 4 to 7C, the error location detecting unit 112 may include a coefficient calculator 112a and an error vector generator 112b.

The coefficient calculator 112a may receive the syndrome S_y from the syndrome calculating unit 111 and may calculate a plurality of coefficients C_x based on the received syndrome S_y. The plurality of coefficients may be variously modified depending on the error correction capability of the ECC circuit 110, a configuration of the H-matrix, an error location polynomial, or the like.

The error vector generator 112b may generate the error vector ERV based on the plurality of coefficients C_x. For example, the error vector generator 112b may include a plurality of checkers. Each of the plurality of checkers may be configured to search for, detect, or calculate a solution of an error location polynomial such as Equation 1.

L ₂(x)=C₂x²+C₁x+C₀

C₂=S₁,

C₁=S₁²,

C ₀ =S ₁ ³ +S ₃   [Equation 1]

Referring to Equation 1, ‘x’ may denote a field element corresponding to a bit location of a data code; L₂(x) may denote an error location polynomial for determining whether a bit of a location corresponding to the field element of x is an error; S₁ may denote a first syndrome corresponding to a product of the data code (i.e., the read data RDT and the parity data PRT) and the upper portion matrix H_U of the H-matrix; and, S₃ may denote a third syndrome corresponding to a product of a data code (i.e., the read data RDT and the parity data PRT) and the lower portion matrix H_L of the H-matrix. In an embodiment, ‘x’ may be a field element (one of α⁰ to α³¹) defined by the H-matrix H-MAT.

In an embodiment, a bit corresponding to the field element ‘x’ satisfying “L₂(x)=0” may be an error bit in the data code. That is, the error vector ERV indicating the error location of the data code may be generated by searching for, detecting, or calculating the field element ‘x’ (or the solution of an error location polynomial) satisfying “L₂(x)=0”. In an embodiment, there may be up to two field elements satisfying “L₂(x)=0”. That is, the error location polynomial of L₂(x) may be used to detect two error bit locations.

In more detail, as shown in FIG. 7A, a checker CHK may be configured to calculate whether the k-th field element α^k is a solution of the error location polynomial. For example, the checker CHK may include a 1st order term calculator CA1, a 2nd order term calculator CA2, a bit-wise XOR logic XOR, and a determiner circuit DET. Herein, the determiner circuit DET may be referred to as a determine DET. The 1st order term calculator CA1 may be configured to receive a first coefficient C₁ from the coefficient calculator 112a and to calculate a 1st order term C₁α^k for the k-th field element α^k. In an embodiment, the first coefficient C₁ may indicate S₁² (i.e., the square of the first syndrome S₁). In an embodiment, each of the first coefficient C₁ and the 1st order term C₁α^k may be a 5-bit binary vector.

The 2nd order term calculator CA2 may be configured to receive a second coefficient C₂ from the coefficient calculator 112a and to calculate a 2nd order term C₂(α^k)² for the k-th field element α^k. In an embodiment, the second coefficient C₂ may indicate S₁ (i.e., the first syndrome S₁). In an embodiment, each of the second coefficient C₂ and the 2nd order term C₂(α^k)² may be a 5-bit binary vector.

The bit-wise XOR logic XOR may receive the 1st order term C₁α^k for the k-th field element α^k from the 1st order term calculator CA1, the 2nd order term C₂(α^k)² for the k-th field element α^k from the 2nd order term calculator CA2, and the 0-th coefficient C₀ from the coefficient calculator 112a. In an embodiment, the 0-th coefficient C₀ may correspond to “S₁³+S₃” (i.e., the sum of the cube of the first syndrome S₁ and the third syndrome S₃). The 0-th coefficient C₀ may be a 5-bit binary vector. The bit-wise XOR logic XOR may perform a bit-wise XOR operation on received signals. The operation result of the bit-wise XOR logic XOR is provided to the determiner DET. In an embodiment, the operation result of the bit-wise XOR logic XOR may be L₂(α^k) and may be a 5-bit binary vector.

The determiner DET may determine whether an operation result L₂(α^k) of the bit-wise XOR logic XOR is all zero. When, the operation result L₂(α^k) of the bit-wise XOR logic XOR is all zero, then that means the k-th field element α^k is a solution of an error location polynomial (i.e., in the data code, the bit of a location corresponding to the k-th field element α^k is an error). In this case, the determiner DET may output a bit value of “e_k” as a k-th error vector element e_k. In contrast, when the operation result L₂(α^k) of the bit-wise XOR logic XOR is not all zero (i.e., at least one bit is “1”), the k-th field element α^k may not be the solution of the error location polynomial. In this case, the determiner DET may output a bit value of “e_k” as a k-th error vector element e_k.

As described above, the checker CHK may search for, detect, determine, or calculate whether the k-th field element α^k is a solution of an error location polynomial. In an embodiment, a data code may include a plurality of bits, and there may be a plurality of field elements respectively corresponding to locations of the plurality of bits. In this case, to search for, detect, determine, or calculate whether each of the plurality of field elements is a solution of an error location polynomial, the error vector generator 112b may include a plurality of checkers.

In an embodiment, the error vector generator 112b may be configured to search for the solution of the error location polynomial described above based on the Chien-search algorithm and to generate the error vector ERV. In an embodiment, the Chien-search algorithm may be performed in a partial parallel method or a full parallel method.

For example, it is assumed that 2-bit error correction for data of 16 bits is performed. In this case, because the data code is a total of 26 bits (data of 16 bits and parity of 10 bits), 26 columns are selected from the H-matrix H-MAT of FIG. 5B. In this case, the selected 26 columns have full-rank characteristics. The 26 field elements may be determined by the selected 26 columns, and the 26 field elements may correspond to locations of bits included in the data code, respectively. For convenience of description, it is assumed that the 26 field elements are α⁰ to α²⁵.

As shown in FIG. 7B, the error vector generator 112b may include four checkers CHK0 to CHK3. The four checkers CHK0 to CHK3 may be configured to search for or calculate a solution that satisfies the error location polynomial among the 26 field elements α⁰ to α²⁵. In this case, because there are the 26 field elements α⁰ to α²⁵ and the four checkers CHK0 to CHK3, the error vector generator 112b may perform an operation on the 26 field elements α⁰ to α²⁵ seven times in units of four.

In more detail, in a first stage (a=1), the 0-th checker CHK0 may determine whether the 0-th field element α⁰ is an error location polynomial solution (i.e., L₂(α⁰)==0) and may output a 0-th error vector element e₀ based on the determination result. Likewise, in the first stage (a=1), the first to third checkers CHK1 to CHK3 may respectively determine whether the first to third field elements α¹ to α³ are solutions of the error location polynomial (i.e., L₂(α¹)==0, L₂(α²)==0, and L₂(α³)==0) and may respectively output first to third error vector elements e₁ to e₃ based on the determination result.

After the first stage (a=1) is completed, in a second stage (a=2), the 0-th to third checkers CHK0 to CHK3 may respectively determine whether the fourth to seventh field elements α⁴ to α⁷ are solutions of the error location polynomial (i.e., L₂(α⁴)==0, L₂(α⁵)==0, L₂(α⁶)==0, and L₂(α⁷)==0), and may respectively output fourth to seventh error vector elements e₄ to e₇ based on the determination result. Likewise, in a seventh stage (a=7), the 0-th and first checkers CHK0 and CHK1 may respectively determine whether the 24th and 25th field elements α²⁴ and α²⁵ are solutions of the error location polynomial (i.e., L₂(α²⁴)==0 and L₂(α²⁵)==0) and may respectively output 24th and 25th error vector elements e₂₄ and e₂₅ based on the determination result. The plurality of checkers CHK0 to CHK3 may output the error vector elements e₀ to e₂₅ by repeating the above-mentioned operation seven times during the first to seventh stages (“a=1” to “a=7”). A combination of the 0-th to 25th error vector elements e₀ to e₂₅ may be output as the error vector ERV.

As shown in FIG. 7C, the error vector generator 112b may include 26 checkers CHK0 to CHK25. The 26 checkers CHK0 to CHK25 may determine whether each of the 26 field elements α⁰ to α²⁵ is a solution of an error location polynomial. In this case, because the number of checkers CHK0 to CHK25 is the same as the number of field elements α⁰ to α²⁵, the error vector elements e₀ to e₂₅ (or the error vector ERV) may be generated through a one-time operation (or one stage).

As described above, an embodiment of FIG. 7B is a configuration based on a Chien-search algorithm in a partial parallel method, and an embodiment of FIG. 7C is a configuration based on a Chien-search algorithm in a full parallel method. In this case, in the Chien-search algorithm in the partial parallel method, because the error vector generator 112b includes checkers, of which the number is smaller than the number of bits of data code, the error vector generator 112b may have a relatively simple structure. However, because a process of searching for or calculating the solution of an error location polynomial is repeated, a calculation time may increase. On the other hand, in the Chien-search algorithm in the full parallel method, because the error vector generator 112b includes checkers, of which the number is the same as the number of bits of data code, the error vector generator 112b may quickly generate an error vector. However, as the number of checkers increases, the structure may become complex.

FIG. 8 is a block diagram showing a structure of an error vector generator of FIG. 6. Hereinafter, for convenience of description, a reference symbol of “α^pX” is used. This is provided to describe a pair configuration of field elements according to an embodiment of the present disclosure. The index number or order indicated by “α^pX” may not match the index number or order of the Galois field GF(2⁵) or the field element of the H-matrix H-MAT. For example, field elements of “α^p0” and “α^p1” may be field elements included in a pair calculated by the 0-th pair checker pCHK0 according to an embodiment of the present disclosure. Each of field elements of “α^p0” and “α^p1” may be one of the field elements α⁰ to α³⁰ of the H-matrix H-MAT described above. In this case, the field elements of “α^p0” and “α^p1” may be an adjacent field element among the field elements α⁰ to α³⁰ of the H-matrix H-MAT, but may not be adjacent to each other. That is, it will be understood that the field elements of “α^p0” and “α^p1” may be variously modified depending on a design method of the present disclosure. However, the field elements of “α^p0” and “α^p1” may have a specific condition or a specific rule, which will be described in more detail below.

Referring to FIGS. 6 and 8, the error vector generator 112b may be configured to generate the error vector ERV by searching for, or calculating, a solution of an error location polynomial. The error vector generator 112b may include a plurality of multi-checkers pCHK0 to pCHK12. Each of the plurality of multi-checkers pCHK0 to pCHK12 may be configured to output at least two error vector elements by performing an error location operation on at least two field elements. In an embodiment, an error location operation may indicate an operation of calculating whether a condition of “L₂(x)=0” is satisfied or an operation of calculating the solution of the error location polynomial, by substituting a field element into the error location polynomial described with reference to Equation 1.

For example, the 0-th pair checker pCHK0 may perform an error location operation on the p0-th field element α^p0 and the p1-st field element α^p1 and may output a p0-th error vector element e_p0 and a p1-st error vector element e_p1 based on the operation result, respectively. The first pair checker pCHK1 may perform an error location operation for a p2-nd field element α^p2 and a p3-th field element α^p3, and may output a p2-nd error vector element e_p2 and a p3-th error vector element e_p3 based on the operation result, respectively. The second pair checker pCHK2 may perform an error location operation for a p4-th field element α^p4 and a fifth field element α^p5 and may output a p4-th error vector element e_p4 and a p5-th error vector element e_p5 based on the operation result, respectively. The m-th pair checker pCHKm may perform an error location operation for a p2m-th field element α^p2m and a (p(2m+1))-th field element α^p(2m+1) and may output a p2m-th error vector element e_p2m and a (p(2m+1))-th error vector element e_p(2m+1) based on the operation result, respectively. Likewise, the twelfth pair checker pCHK12 may perform an error location operation for a p24th field element α^p24 and a 25th field element α^p25 and may output a p24-th error vector element e_p24 and a p25-th error vector element e_p25 based on the operation result, respectively.

As described above, each of the plurality of pair checkers pCHK0 to pCHK12 may be configured to perform an error location operation on two field elements and to output two error vector elements. As such, compared to the embodiment of FIG. 7B (i.e., a partial-parallel method), because all error vector elements are calculated and/or generated through one stage, an error vector generation time may be shortened. Moreover, compared to embodiment of FIG. 7C (i.e., a full parallel method), because the number of checkers is reduced by half, a structure of the ECC circuit 110 may be simplified. That is, according to embodiments of the present disclosure, a duration of an error calculation operation may be shortened and, at the same time, the structure of the ECC circuit 110 may be simplified.

In an embodiment, two field elements (e.g., α^p2m and α^p(2m+1)) calculated by one pair checker (e.g., pCHK0) are referred to as a “pair”. In this case, the pair may be composed of at least two field elements. Pairs used by each of the plurality of pair checkers pCHK0 to pCHK12 include different field elements. That is, each of the field elements operated by each of the plurality of pair checkers pCHK0 to pCHK12 may be an independent binary vector. Each of field elements included in each of pairs operated by each of the plurality of pair checkers pCHK0 to pCHK12 corresponds to one of columns included in the H-matrix and does not overlap each other. Field elements included in each of the pairs may be designed to satisfy a predetermined rule.

For example, the m-th pair operated by the m-th pair checker pCHKm may include the p2m-th field element α^p2m and the (p(2m+1))-th field element α^p(2m+1). In this case, the p2m-th field element α^p2m and the (p(2m+1))-th field element α^p(2m+1) may satisfy the relationship of Equation 2.

α^p(2m+1)=α^p2m+α^j   [Equation 2]

Referring to Equation 2, α^j may indicate one of field elements of the Galois field GF(2⁵) described with reference to FIG. 5A. That is, field elements operated by one pair checker may be designed to satisfy a specific rule or specific condition as described above. In this case, an error location polynomial, to which the field elements α^p2m and α^p(2m+1) included in the m-th pair are reflected, may be expressed as in Equation 3.

L ₂(α^p(2m))=S₁(α^p(2m))²+S₁²α^2m+S₁³+S₃

L ₂(α^p(2m+1))=L₂(α^p2m+α^j)=S₁(α^p2m+α^j)²+S₁²(α^p2m+α^j)+S₁³+S₃    [Equation 3]

Variables of Equation 3 are described above, and thus a detailed description thereof will be omitted to avoid redundancy. For ease of explanation of an embodiment of the present disclosure, it is assumed that α^j is α⁰ (i.e., 1). In this case, the error location polynomial of L₂(α^p(2m+1)) may be expressed as in Equation 4.

$\begin{array}{cc}\begin{array}{c}{L}_2\left({\alpha }^{p\left(2m+1\right)}\right)=L_2\left({\alpha }^{\mathrm{p2}m}+1\right)\\ ={S_1\left({\alpha }^{\mathrm{p2}m}+1\right)}^2+S_1^2\left({\alpha }^{p2m}+1\right)+S_1^3+S_3\\ =S_1\left({\left({\alpha }^{\mathrm{p2}m}\right)}^2+1\right)+S_1^2\left({\alpha }^{p2m}+1\right)+S_1^3+S_3,\left(\mathrm{note}\mathrm{that}2{\alpha }^{p2m}=0\right)\end{array}& \left[\mathrm{Equation}4\right]\end{array}$

Variables of Equation 4 are described above, and thus a detailed description thereof will be omitted to avoid redundancy. As expressed in Equation 4, the error location polynomial of L₂(α^p(2m+1)) may be expressed as a polynomial for α^p2m. In this case, L₂(α^p(2m+1)) may be expressed as in Equation 5.

$\begin{array}{cc}{L}_2\left({\alpha }^{p\left(2m+1\right)}\right)=L_2\left({\alpha }^{p2m}+1\right)& \left[\mathrm{Equation}5\right]\end{array}$

Variables of Equation 5 are described above, and thus a detailed description thereof will be omitted to avoid redundancy. As described above, when the field elements α^p2m and α^p(2m+1) included in the m-th pair satisfy a condition described in Equation 2, as expressed in Equation 5, the error location polynomial L₂(α^p(2m+1)) for the (p(2m+1))-th field element α^p(2m+1) may be expressed as the error location polynomial L₂(α^p2m) for the p2m-th field element α^p2m and a common coefficient (S₁+S₁²). In this case, because a separate decoding design for the error location polynomial L₂(α^p(2m+1)) for the (p(2m+1))-th field element α^p(2m+1) is not required, the structure of the ECC circuit 110 may be simplified.

In an embodiment, pairs of field elements operated by the plurality of pair checkers pCHK0 to pCHK12 may be designed to each satisfy the same rule (e.g., a rule according to Equation 2). In this case, a common coefficient (e.g., a common coefficient (S₁+S₁²) in Equation 5) used by each of the plurality of pair checkers pCHK0 to pCHK12 is the same, and thus the design structure for a coefficient operation may be simplified. As described above, pairs of field elements operated by the plurality of pair checkers pCHK0 to pCHK12 may be designed based on the same rules as each other, but the scope of the present disclosure is not limited thereto. For example, pairs of field elements operated by the plurality of pair checkers pCHK0 to pCHK12 may be designed based on different rules from one another. In more detail, some (e.g., pCHK0 to pCHK5) of the plurality of pair checkers pCHK0 to pCHK12 may use pairs that satisfy a first condition (or a first rule), and the others (e.g., pCHK6 to pCHK12) of the plurality of pair checkers pCHK0 to pCHK12 may use pairs that satisfy a second condition (or a second rule). In this case, pair checkers that use pairs satisfying the same condition (or the same rule) may use the same common coefficient. That is, some pair checkers (e.g., pCHK0 to pCHK5) that use pairs satisfying the first condition (or the first rule) may use the first common coefficient in common, and other pair checkers (e.g., pCHK6 to pCHK12) that use pairs satisfying the second condition (or the second rule) may use the second common coefficient in common.

FIG. 9 is a block diagram showing a pair checker of FIG. 8. For convenience of description, a schematic structure of the m-th pair checker pCHKm is described with reference to FIG. 8. In this case, it is assumed that the m-th pair checker pCHKm may perform an error location operation on each of the p2m-th field element α^p2m and the (p(2m+1))-th field element α^p(2m+1), and the p2m-th field element α^p2m and the (p(2m+1))-th field element α^p(2m+1) satisfy a rule (i.e., α^p2m+1=α^p2m+1) according to Equation 4.

Referring to FIGS. 6, 8, and 9, the m-th pair checker pCHKm may include the 1st order term calculator CA1, the 2nd order term calculator CA2, a first bit-wise XOR logic XOR1, a first determiner DET1, a second bit-wise XOR logic XOR2, and a second determiner DET2.

The 1st order term calculator CA1 may receive the first coefficient C₁ from the coefficient calculator 112a. In an embodiment, the first coefficient C₁ may be S₁³, but the scope of the present disclosure is not limited thereto. The 1st order term calculator CA1 may output a 1st order term S₁²α^p2m based on the first coefficient C₁ and the p2m-th field element α^p2m. Each of the first coefficient C₁, the p2m-th field element α^p2m, and the 1st order term S₁²α^p2m may be a 5-bit binary vector.

The 2nd order term calculator CA2 may receive the second coefficient C₂ from the coefficient calculator 112a. The second coefficient C₂ may be S₁, but the scope of the present disclosure is not limited thereto. The 2nd order term calculator CA2 may output the 2nd order term S₁(α^p2m)² based on the second coefficient C₂ and the p2m-th field element α^p2m. Each of the second coefficient C₂, the p2m-th field element α^p2m, and the 2nd order term S₁(α^p2m)² may be a 5-bit binary vector.

The first bit-wise XOR logic XOR1 may receive the 1st order term S₁²α^p2m from the 1st order term calculator CA1, may receive the 2nd order term S₁(α^p2m)² from the 2nd order term calculator CA2, and may receive the 0-th coefficient C₀ from the coefficient calculator 112a. In an embodiment, the 0-th coefficient C₀ may be “S₁³+S₃”, but the scope of the present disclosure is not limited thereto. The first bit-wise XOR logic XOR1 may perform a bit-wise XOR operation on the received signals. The operation result (i.e., L₂(α^p2m)) of the first bit-wise XOR logic XOR1 is provided to the first determiner DET1. The 0-th coefficient C₀ and the operation result (i.e., L₂(α^p2m)) may be a 5-bit binary vector.

The first determiner DET1 may determine whether an operation result (i.e., L₂(α^p2m)) of the first bit-wise XOR logic XOR1 is all zero, and may output a p2m-th error vector element e_p2m based on the determination result. Because an operation of the first determiner DET1 is similar to that of the determiner DET described with reference to FIG. 7A, a detailed description thereof will be omitted to avoid redundancy.

The second bit-wise XOR logic XOR2 may receive an operation result (i.e., L₂(α^p2m)) from the first bit-wise XOR logic XOR1 and may receive a common coefficient C_cm from the coefficient calculator 112a. In an embodiment, as described with reference to Equation 5, the common coefficient C_cm may be “S₁+S₁²”, but the scope of the present disclosure is not limited thereto. The second bit-wise XOR logic XOR2 may perform a bit-wise XOR operation on the received signals. The operation result of the second bit-wise XOR logic XOR2 may be “L₂(α^p2m)+S₁+S₁²”. In this case, as described with reference to Equation 5, “L₂(α^p2m)+S₁+S₁²” is the same as L₂(α^p(2m+1)). That is, the operation result of the second bit-wise XOR logic XOR2 may be “L₂(α^p(2m+1))”.

The second determiner DET2 may receive the operation result L₂(α^p(2m+1)) of the second bit-wise XOR logic XOR2 and may determine whether the received signal is all zero. The second determiner DET2 may output a (p(2m+1))-th error vector element e_p(2m+1) based on the determination result.

As described above, one pair checker (e.g., the m-th pair checker pCHKm) may perform an error location operation on at least two field elements designed to satisfy a predetermined rule. In this case, a circuit structure for performing an error location operation may be simplified. For example, in a case of the checker CHK described with reference to FIG. 7A, because the error location operation is performed on one field element, two checkers CHK, each of which is described with reference to FIG. 7A, are required to perform the error location operation on two field elements. In this case, there is a need for two 1st order term calculators, two 2nd order term calculators, two bit-wise XOR logics, and two determiners. On the other hand, the pair checker pCHKm of FIG. 9 may perform an error location operation on two field elements, and includes one 1st order term calculator, one 2nd order term calculator, one bit-wise XOR logics, and two determiners. That is, the pair checker pCHKm of FIG. 9 may provide the same calculation performance by using calculators or logics, of which the number is reduced compared to the checker CHK of FIG. 7A.

FIG. 10 is a diagram for describing field elements respectively operated by a plurality of pair checkers of FIG. 8. Referring to FIGS. 8 and 10, the 0-th to twelfth pair checkers pCHK0 to pCHK12 may perform error location operations on 0-th to twelfth pairs, respectively. In this case, field elements included in each of the 0-th to twelfth pairs may be designed as shown in FIG. 10.

For example, it is assumed that the m-th pair used in the m-th pair checker pCHKm includes α^p2m and α^p(2m+1), and satisfies “α^p(2m+1)=α^p2m+1”. In this case, the 0-th pair may include the first and eighteenth field elements α¹ and α¹⁸; the first pair may include the second and fifth field elements α² and α⁵; the second pair may include the third and 29th field elements α³ and α²⁹; the third pair may include the fourth and tenth field elements α⁴ and α¹⁰; the fourth pair may include the sixth and 27th field elements α⁶ and α²⁷; the fifth pair may include the seventh and 22nd field elements α⁷ and α²²; the sixth pair may include the eighth and twentieth field elements α⁸ and α²⁰; the seventh pair may include the ninth and sixteenth field elements α⁹ and α¹⁶; the eighth pair may include the eleventh and nineteenth field elements α¹¹ and α¹⁹; the ninth pair may include the twelfth and 23rd field elements ≢¹² and α²³; the tenth pair may include thirteenth and fourteenth field elements α¹³ and α¹⁴; the eleventh pair may include the fifteenth and 24th field elements α¹⁵ and α²⁴; and the twelfth pair may include seventeenth and 30th field elements α¹⁷ and α³⁰. The field elements included in the above-mentioned pairs are simple examples, and the field elements included in each of the pairs may be variously modified according to a rule between field elements, which are included in each of the pairs, and a design method of the H-matrix.

FIG. 11 is a block diagram showing an error location detecting unit of FIG. 6. For convenience of description, detailed descriptions associated with the components described above will be omitted to avoid redundancy. Referring to FIGS. 6 and 11, the error location detecting unit 112 may include the plurality of pair checkers pCHK0 to pCHK8. Each of the plurality of pair checkers pCHK0 to pCHK8 may be configured to output at least two error vector elements by performing an error location operation on at least two field elements. In an embodiment, in the embodiments described with reference to FIGS. 8 to 10, one pair checker may perform an error location operation on two field elements. That is, in the embodiment described with reference to FIGS. 8 to 10, one pair is composed of two field elements. On the other hand, in an embodiment of FIG. 11, one pair checker may perform an error location operation on three field elements.

For example, in the embodiment of FIG. 11, the 0-th pair checker pCHK0 may output the p0-th error vector element e_p0, the p1-st error vector element e_p1, and the p2-nd error vector element e_p2 by performing an error location operation on the p0-th field element α^p0, the p1-st field element α^p1, and the p2-nd field element α^p2; the first pair checker pCHK1 may output the p3-th error vector element e_p3, the p4-th error vector element e_p4, and the p5-th error vector element e_p5 by performing an error location operation on the p3-th field element α^p3, the p4-th field element α^p4, and the p5-th field element α^p5; the m-th pair checker pCHKm may output the p3m-th error vector element e_p3m, the (p(3m+1)-th error vector element e_p(3m+1), and the (p(3m+2)-th error vector element e_p(3m+2) by performing an error location operation on the p3m-th field element α^p3m, the (p(3m+1)-th field element α^p(3m+1), and the (p(3m+2)-th field element α^p(3m+2); the seventh pair checker pCHK7 may output the p21-st error vector element e_p21, the p22-nd error vector element e_p22, and the p23-th error vector element e_p23 by performing an error location operation on the p21-st field element α^p21, the p22-nd field element α^p22, and the p23-th field element α^p23; and, the eighth pair checker pCHK8 may output the p24-th error vector element e_p24 and the p25-th error vector element e_p25 by performing an error location operation on the p24-th field element α^p24 and the p25-th field element α^p25.

In an embodiment, as in the above description, a pair of three field elements operated by one pair checker may be designed to have a specific rule. For example, the three field elements calculated by the m-th pair checker pCHKm may be α^p3m, α^p(3m+1), and α^p(3m+2). In this case, the three field elements α^p3m, α^p(3m+1), and α^p(3m+2) may be designed to have a rule such as Equation 6.

α^p(3m+1)=α^p3m+α^k

α^p(3m+2)=α^p3m+α_j   [Equation 6]

Referring to Equation 6, because α^k may be one of a plurality of field elements included in the Galois field GF(2⁵) of FIG. 5A, and the other variables are similar to those described above, a detailed description thereof is omitted to avoid redundancy. According to Equation 6, when the three field elements α^p3m, α^p(3m+1), and α^p(3m+2) are designed, the result of the error location operation on the three field elements α^p3m, α^p(3m+1), and α^p(3m+2) may be as shown in Equation 7. In this case, for convenience of description, it is assumed that ‘k’ is 0 and ‘j’ is 1.

$\begin{array}{cc}\begin{array}{c}{L}_2\left({\alpha }^{p\left(3m\right)}\right)={S_1\left({\alpha }^{p\left(3m\right)}\right)}^2+S_1^2{\alpha }^{3m}+S_1^3+S_3\\ L_2\left({\alpha }^{p\left(3m+1\right)}\right)=L_2\left({\alpha }^{p3m}+1\right)\\ ={S_1\left({\alpha }^{p\left(3m\right)}\right)}^2+S_1^2{\alpha }^{3m}+S_1^3+S_3+S_1+S_1^2\\ L_2\left({\alpha }^{p\left(3m+1\right)}\right)=L_2\left({\alpha }^{p3m}+{\alpha }^1\right)\\ ={S_1\left({\alpha }^{p\left(3m\right)}\right)}^2+S_1^2{\alpha }^{3m}+S_1^3+S_3+S_1{\alpha }^1+S_1^2{\alpha }^1\end{array}& \left[\mathrm{Equation}7\right]\end{array}$

Variables of Equation 7 are similar to those described above, and thus a detailed description thereof is omitted to avoid redundancy. As described in Equation 7, a result (i.e., L₂(α^p(3m+1))) of an error location operation on α^p(3m+1) may be expressed as the sum of a result (i.e., L₂(α^p3m)) of an error location operation on α^p3m and the first common coefficient (S₁+S₁²). A result (i.e., L₂(α^p(3m+2))) of an error location operation on α^p(3m+2) may be expressed as the sum of a result (i.e., L₂(α^p3m)) of the error location operation on α^p3m and the second common coefficient (S₁α+S₁²α). That is, an error location operation on two field elements among the three field elements is performed by using the result of an error location operation on the other field element, and thus a structure of the error location detecting unit 112 may be simplified.

FIG. 12 is a block diagram showing one of a plurality of pair checkers of FIG. 11. For convenience of description, detailed descriptions associated with the components described above will be omitted to avoid redundancy. Referring to FIGS. 11 and 12, a m-th pair checker pCHKm−1 may perform an error location operation on three field elements (e.g., α^p3m, α^p(3m+1), and α^p(3m+2)). In this case, the three field elements (e.g., α^p3m, α^p(3m+1), and α^p(3m+2)) may satisfy a rule (i.e., α^p(3m+1)=α^p3m+1 and α^p(3m+2)=α^p3m+α) described with reference to Equation 7.

The m-th pair checker pCHKm−1 may include the 1st order term calculator CA1, the 2nd order term calculator CA2, the first bit-wise XOR logic XOR1, the first determiner DET1, the second bit-wise XOR logic XOR2, the second determiner DET2, a third bit-wise XOR logic XOR3, and a third determiner DET3. The configurations and operations of the 1st order term calculator CA1, the 2nd order term calculator CA2, the first bit-wise XOR logic XOR1, and the first determiner DET1 are similar to those described with reference to FIGS. 7A and 9, and thus a detailed description thereof is omitted to avoid redundancy.

The second bit-wise XOR logic XOR2 may receive an operation result (i.e., L₂(α^p3m)) from the first bit-wise XOR logic XOR1 and may receive a first common coefficient C_cm1 from the coefficient calculator 112a. In an embodiment, as described with reference to Equation 7, the first common coefficient C_cm1 may be “S₁+S₁²”, but the scope of the present disclosure is not limited thereto. The second bit-wise XOR logic XOR2 may perform a bit-wise XOR operation on the received signals. The operation result of the second bit-wise XOR logic XOR2 may be “L₂(α^p3m)+S₁+S₁²”. In this case, as described with reference to Equation 7, “L₂(α^p3m)+S₁+S₁²” is the same as L₂(α^p(3m+1)). That is, the operation result of the second bit-wise XOR logic XOR2 may be “L₂(α^p(3m+1))”.

The second determiner DET2 may receive the operation result L₂(α^p(3m+1)) of the second bit-wise XOR logic XOR2 and may determine whether the received signal is all zero. The second determiner DET2 may output a (p(3m+1))-th error vector element e_p(3m+1) based on the determination result.

The third bit-wise XOR logic XOR3 may receive an operation result (i.e., L₂(α^p3m)) from the first bit-wise XOR logic XOR1 and may receive a second common coefficient C_cm2 from the coefficient calculator 112a. In an embodiment, as described with reference to Equation 7, the second common coefficient C_cm2 may be “S₁α+S₁²α”, but the scope of the present disclosure is not limited thereto. The third bit-wise XOR logic XOR3 may perform a bit-wise XOR operation on the received signals. The operation result of the third bit-wise XOR logic XOR3 may be “L₂(α^p3m)+S₁α+S₁²α”. In this case, as described with reference to Equation 7, “L₂(α^p3m)+S₁α+S₁²α” is the same as L₂(α^p(3m+2)). That is, the operation result of the third bit-wise XOR logic XOR3 may be “L₂(α^p(3m+2)”.

The third determiner DET3 may receive the operation result L₂(α^p(3m+2)) of the third bit-wise XOR logic XOR3 and may determine whether the received signal is all zero. The third determiner DET3 may output a (p(3m+2))-th error vector element e_p(3m+2) based on the determination result.

As described above, the ECC circuit 110 according to an embodiment of the present disclosure may include a pair checker capable of performing an error location operation on at least two field elements simultaneously or in parallel. In this case, as described above, the error vector generation time may be shortened and, at the same time, the structure of the ECC circuit 110 may be simplified.

FIGS. 13 and 14 are block diagrams showing a pair checker included in an error vector generator of FIG. 6. In the above-described embodiments, it is described that the ECC circuit 110 corrects the maximum of a 2-bit error. However, the scope of the present disclosure is not limited thereto. For example, the ECC circuit 110 may be configured to correct errors of 3 bits or more.

For example, it is assumed that the ECC circuit 110 corrects the maximum of a 3-bit error. In this case, an error location polynomial operated by the error vector generator 112b may be expressed as Equation 8.

L ₃(x)=C₃x³+C₂x²+C₁x¹+C₀   [Equation 8]

Referring to Equation 8, L₃(x) may be an error location polynomial for detecting a location of a 3-bit error in a data code. C₃ may be a coefficient of the 3rd order term for a field element of ‘x’ and may be “S₁³+S₃”; C₂ may be a coefficient of the 2nd order term for the field element of ‘x’, and may be “(S₁³+S₃)S₁”; C₁ may be a coefficient of the 1st order term for the field element of ‘x’, and may be “S₁²S₃+S₅”; and, C₀ may be a 0-th coefficient (i.e., a constant term) and may be “(S₁³+S₃)²+S₁(S₁²S₃+S₅)”. Each of S₁, S₃, and S₅ may be a syndrome S_y operated by the syndrome calculating unit 111 (see FIG. 4). C₀, C₁, C₂, and C₃ may be calculated by the coefficient calculator 112a based on the syndrome S_y.

When the ECC circuit 110 corrects the maximum of a 3-bit error, as in the above description, one pair checker pCHK may perform an error location operation on two field elements included in one pair. For example, it is assumed that two field elements (e.g., α^p2m and α^p(2m+1)) included in one pair satisfy a condition of “α^p(2m+1)=α^p2m+1”. In this case, a result of the error location operation on two field elements (e.g., α^p2m and α^p(2m+1)) included in one pair may be expressed as in Equation 9.

$\left[\mathrm{Equation}9\right]$ ${\alpha }^{p\left(2m+1\right)}={\alpha }^{p2m}+1$ $L_3\left({\alpha }^{p2m}\right)={C_3\left({\alpha }^{p2m}\right)}^3+{C_2\left({\alpha }^{p2m}\right)}^2+C_1\left({\alpha }^{p2m}\right)+C_0$ $L_3\left({\alpha }^{p\left(2m+1\right)}\right)=C_3\left({\left({\alpha }^{p2m}\right)}^3+{\left({\alpha }^{p2m}\right)}^2+{\alpha }^{p2m}+1\right)+C_1\left({\left({\alpha }^{p2m}\right)}^2+1\right)+C_1\left({\alpha }^{p2m}+1\right)+C_0=L_3\left({\alpha }^{p2m}\right)+{C_3\left({\alpha }^{p2m}\right)}^2+C_3{\alpha }^{p2m}+C_3+C_2+C_1$

Variables of Equation 9 are described above, and thus a detailed description thereof will be omitted to avoid redundancy. As described in Equation 9, a result of error location operation on “α^p(2m+1)” may be calculated by using a result of an error location operation on “α^p2m”, and such a structure may be similar to that of the above-described embodiments.

For example, as illustrated in FIG. 13, the pair checker pCHKm−2 may include the 1st order term calculator CA1, a first 2nd order term calculator CA2-1, a 3rd order term calculator CA3, the first bit-wise XOR logic XOR1, the first determiner DET1, a second 2nd order term calculator CA2-2, the second bit-wise XOR logic XOR2, and the second determiner DET2.

The 1st order term calculator CA1 may receive the first coefficient C₁ from the coefficient calculator 112a and may calculate a 1st order term C₁α^p2m by using the first coefficient C₁. The first coefficient C₁ and the 1st order term C₁α^p2m may be a 5-bit binary vector. In an embodiment, the 1st order term C₁α^p2m may be a 1st order term for the p2m-th field element α^p2m of the error location polynomial L₂(x).

The first 2nd order term calculator CA2-1 may receive the second coefficient C₂ from the coefficient calculator 112a and may calculate a 2nd order term C₂(α^p2m)² by using the second coefficient C₂. The second coefficient C₂ and the 2nd order term C₂(α^p2m)² may be a 5-bit binary vector. (C₂(α^p2m)²) may be a 2nd order term for the p2m-th field element α^p2m of the error location polynomial L₂(x).

The 3rd order term calculator CA3 may receive a third coefficient C₃ from the coefficient calculator 112a and may calculate a 3rd order term C₃(α^p2m)³ by using the third coefficient C₃. The third coefficient C₃ and the 3rd order term C₃(α^p2m)³ may be a 5-bit binary vector.

The first bit-wise XOR logic XOR1 may respectively receive the 1st order term C₁α^p2m, the 2nd order term C₂(α^p2m)², and the 3rd order term C₃(α^p2m)³ from the 1st order term calculator CA1, the first 2nd order term calculator CA2-1, and the 3rd order term calculator CA3 and may receive the 0-th coefficient C₀ from the coefficient calculator 112a. The first bit-wise XOR logic XOR1 may perform a bit-wise XOR operation on the received signals. The operation result L₃(α^p2m) is provided to the first determiner DET1. The first determiner DET1 may output a p2m-th error vector element e_p2m based on the operation result L₃(α^p2m) of the first bit-wise XOR logic XOR1.

As described with reference to Equation 9, an error location operation result of α^p(2m+1) included in a pair together with α^p2m may be calculated by using L₃(α^p2m). In other words, the second 2nd order term calculator CA2-2 may receive the third coefficient C₃ from the coefficient calculator 112a and may calculate the 2nd order term C₃{(α^p2m)²+α^p2m} by using the third coefficient C₃.

The second bit-wise XOR logic XOR2 may receive the 2nd order term C₃{(α^p2m)²+α^p2m} from the second 2nd order term calculator CA2-2 and may receive the common coefficient C_cm from the coefficient calculator 112a. The common coefficient C_cm may correspond to the sum of C₁, C₂, and C₃. The second bit-wise XOR logic XOR2 may perform a bit-wise XOR operation on the received signals. The operation result may be L₃(α^p(2m+1)) and may be provided to the second determiner DET2. The second determiner DET2 may output the (p(2m+1))-th error vector element e_p(2m+1) based on the operation result L₃(α^p(2m+1)).

In an embodiment, two field elements (e.g., α^p2m and α^p(2m+1)) included in one pair may satisfy a condition of “α^p(2m+1)=α^p2m+α^j”. In this case, a result of an error location operation of two field elements (e.g., α^p2m and α^p(2m+1)) included in one pair may be expressed as in Equation 10.

$\left[\mathrm{Equation}10\right]$ ${\alpha }^{p\left(2m+1\right)}={\alpha }^{p2m}+{\alpha }^j$ $L_3\left({\alpha }^{p2m}\right)={C_3\left({\alpha }^{p2m}\right)}^3+{C_2\left({\alpha }^{p2m}\right)}^2+C_1\left({\alpha }^{p2m}\right)+C_0$ $L_3\left({\alpha }^{p\left(2m+1\right)}\right)=C_3\left({\left({\alpha }^{p2m}\right)}^3+{\left({\alpha }^{p2m}\right)}^2{\alpha }^j+{{\alpha }^{p2m}\left({\alpha }^j\right)}^2+{\left({\alpha }^j\right)}^3\right)+C_1\left({\left({\alpha }^{p2m}\right)}^2+{\left({\alpha }^j\right)}^2\right)+C_1\left({\alpha }^{p2m}+{\alpha }^j\right)+C_0=L_3\left({\alpha }^{p2m}\right)+{C_3\left({\alpha }^{p2m}\right)}^2{\alpha }^j+C_3{{\alpha }^{p2m}\left({\alpha }^j\right)}^2+C_3{\alpha }^j+C_2{\alpha }^j+C_1{\alpha }^j$

Referring to Equation 10, α^j may indicate one of the field elements of the Galois field GF(2⁵) (i.e., a Galois field required to design the H-matrix H-MAT) described with reference to FIG. 5A. The remaining variables are described above, and thus a detailed description thereof will be omitted to avoid redundancy.

As described in Equation 10, a result of error location operation on “α^p(2m+1)” may be calculated by using a result of an error location operation on “α^p(2m+1)”, and such a structure may be similar to that of the above-described embodiments.

For example, as illustrated in FIG. 14, the pair checker pCHKm−3 may include the 1st order term calculator CA1, the first 2nd order term calculator CA2-1, the 3rd order term calculator CA3, the first bit-wise XOR logic XOR1, the first determiner DET1, the second 2nd order term calculator CA2-2, the second bit-wise XOR logic XOR2, and the second determiner DET2.

The configurations and operations of the 1st order term calculator CA1, the first 2nd order term calculator CA2-1, the 3rd order term calculator CA3, the first bit-wise XOR logic XOR1, and the first determiner DET1 are similar to those described with reference to FIG. 13, and thus a detailed description thereof is omitted to avoid redundancy. The second 2nd order term calculator CA2-2, the second bit-wise XOR logic XOR2, and the second determiner DET2 are similar to those described above except that the 2nd order term C₃{(α^p2m)²α^j+(α^j)²α^p2m}, which is calculated, and the common coefficient C_cm (i.e., C_cm=C₃(α^j)³+C₂(α^j)²+C₁α^j) are different from those of FIG. 13, and thus a detailed description thereof is omitted to avoid redundancy.

As described above, according to embodiments of the present disclosure, the ECC circuit 110 may configure a plurality of field elements, which indicate locations of the data code, into pairs so as to satisfy a predetermined rule or a predetermined condition and may perform an error location operation on each pair (i.e., at least two field elements) by using one pair checker. In this case, faster decoding than an ECC decoder based on a Chien-search algorithm in a partial-parallel method is possible. Moreover, a simpler structure than the ECC decoder based on a Chien-search algorithm in a full-parallel method is possible.

FIG. 15 is a flowchart illustrating an operation of a memory device of FIG. 2. Referring to FIGS. 2 and 15, in operation S110, the memory device 100 may receive a read command from the memory controller 11. In operation S120, the memory device 100 may read out raw data from the memory cell array 120. For example, the read command received from the memory controller 11 may include information about a read address. The memory device 100 may read out data (i.e., raw data) corresponding to the read address from the memory cell array 120.

In operation S130, the memory device 100 may generate a syndrome. For example, data corresponding to the read address may be a data code including user data and parity data. The ECC circuit 110 of the memory device 100 may generate a plurality of syndromes based on the data code and the H-matrix H-MAT.

In operation S140, the memory device 100 may generate an error vector by using pair checkers. For example, the ECC circuit 110 of the memory device 100 may be implemented as described with reference to FIGS. 1 to 14. That is, a plurality of field elements corresponding to a plurality of bits of the data code may be divided into pair units based on a predetermined rule. In this case, each of the pair checkers of the ECC circuit 110 may perform an error location operation on each pair, and an error vector may be generated based on the operation result of the pair checkers. Operation S140 is described with reference to FIGS. 1 to 14, and thus, an additional description thereof will be omitted to avoid redundancy.

In operation S150, the memory device 100 may correct errors of the raw data based on the error vector. In operation S160, the memory device 100 may transmit the corrected data to the memory controller 11. In an embodiment, when error correction fails by the ECC circuit 110 of the memory device 100 (i.e., when ECC decoding fails), the memory device 100 may notify the memory controller 11 of decoding failure by using information such as a decoding status flag DSF.

FIG. 16 is a flowchart showing a method for designing an ECC decoder, according to an embodiment of the present disclosure. In an embodiment, a flowchart shown in FIG. 16 may be performed by a separate ECC design tool or a memory device design tool. Referring to FIG. 16, in operation S210, the H-matrix H-MAT is determined or designed. For example, the H-matrix H-MAT may be implemented in various forms depending on an error correction capability of the ECC circuit 110 and the length of a data code.

In operation S220, pairs of field elements in the H-matrix may be determined or designed based on predefined rules or predefined conditions. For example, the H-matrix H-MAT may be composed of a plurality of field elements. The plurality of field elements may respectively correspond to locations of a plurality of bits included in the data code. The plurality of field elements may be classified or determined in pair units (i.e., a unit of at least two field elements) based on the method described with reference to FIGS. 1 to 15. In an embodiment, field elements included in one pair may be set to satisfy a predefined rule or a predefined condition. In an embodiment, all field elements included in all pairs may be independent of each other.

In operation S230, an error location detector may be configured based on the determined pairs. For example, when it is determined that a first pair includes a first field element and a second field element, a pair checker that performs an error location operation on the first pair may be configured to search for, detect, determine, or calculate whether the first field element and the second field element are solutions of an error location polynomial. A configuration of a pair checker is described with reference to FIGS. 1 to 15, and thus, an additional description thereof will be omitted to avoid redundancy.

FIG. 17 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure. Referring to FIG. 17, a memory system 1000 may include a memory controller 1100, an ECC circuit 1200, and a memory device 1300. The memory controller 1100 may store data in the memory device 1300 or may read out data stored in the memory device 1200.

In an embodiment, the ECC circuit 1200 may be located on a data path between the memory controller 1100 and the memory device 1300. The ECC circuit 1200 may be configured to correct an error of data transmitted and received between the memory controller 1100 and the memory device 1300. In an embodiment, the ECC circuit 1200 may operate based on the operating method described with reference to FIGS. 1 to 16.

FIG. 18 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure. Referring to FIG. 18, a memory system 2000 may include a memory controller 2100 and a memory device 2200. The memory controller 2100 may include an ECC circuit 2110. The ECC circuit 2110 may be configured to generate parity data for data to be stored in the memory device 2200 or to correct an error of data read out based on the data and the parity data read from the memory device 2200. The ECC circuit 2110 may operate based on the method described with reference to FIGS. 1 to 16.

FIG. 19 is a block diagram illustrating a memory system, according to an embodiment of the present disclosure. Referring to FIG. 19, a memory system 3000 may include a memory controller 3100 and a memory device 3200. The memory controller 3100 may include a controller ECC circuit 3110. The controller ECC circuit 3110 may generate a first parity for write data to be stored in the memory device 3200 and may correct an error of read data based on the read data and the first parity that are received from the memory device 3200.

The memory device 3200 may include a memory ECC circuit 3210. The memory ECC circuit 3210 may generate a second parity for the write data and the first parity, which are received from the memory controller 3100, and may correct errors of the read data and the first parity based on the read data, the first parity, and the second parity, which are stored in the memory device 3200.

In an embodiment, each of the controller ECC circuit 3110 and the memory ECC circuit 3210 may operate based on the method described with reference to FIGS. 1 to 15. In another embodiment, in the embodiments described with reference to FIGS. 1 to 15, the ECC circuit 110 has been described as an on-die ECC (OD-ECC) circuit included in the memory device 100, but the scope of the present disclosure is not limited thereto. For example, as described with reference to FIGS. 17 to 19, the ECC circuit may be located inside or outside a memory device or within a memory controller.

FIG. 20 is a diagram showing some examples of a memory package, according to an embodiment of the present disclosure. Referring to FIG. 20, a memory package 4000 may include a plurality of memory dies 4110 to 4140 and a buffer die 4200. Each of the plurality of memory dies 4110 to 4140 may be a DRAM device. The plurality of memory dies 4110 to 4140 and the buffer die 4200 may be implemented in a stacked structure and may be electrically connected to each other through a through silicon via TSV to communicate with each other.

In an embodiment, the memory package 4000 may be provided as a single semiconductor package by being packaged in a manner such as package on package (POP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flatpack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), or the like.

The buffer die 4200 may communicate with an external host device (or a memory controller). The buffer die 4200 may be configured to temporarily store data to be stored in the plurality of memory dies 4110 to 4140 or to temporarily store data read out from the plurality of memory dies 4110 to 4140. In an embodiment, the buffer die 4200 may include an ECC circuit 4210. The ECC circuit 4210 may generate a parity for data to be stored in the memory dies 4110 to 4140 or may correct errors of data read out from the memory dies 4110 to 4140. In an embodiment, the ECC circuit 4210 may be implemented or may operate based on the method described with reference to FIGS. 1 to 15.

FIG. 21 is a diagram showing some examples of a memory package,

according to an embodiment of the present disclosure. Referring to FIG. 21, a memory package 5000 may include a plurality of memory dies 5110 to 5140 and a host die 5200. The plurality of memory dies 5110 to 5140 may be electrically connected to each other through a micro bump MCB, may have a stacked structure, and may be directly stacked on the host die 5200. The host die 5200 may be an SoC, a CPU, or a GPU. In an embodiment, each of the plurality of memory dies 5110 to 5140 or the host die 5200 may include the ECC circuit described with reference to FIGS. 1 to 15.

FIG. 22 is a block diagram illustrating a memory module 6000 to which a memory device according to an embodiment of the present disclosure is applied. Referring to FIG. 22, the memory module 6000 may include a register clock driver RCD 6100, a plurality of memory devices 6210 to 6290, and a plurality of data buffers DB.

The RCD 6100 may receive a command/address CA and a clock signal CK from an external device (e.g., a host or a memory controller). On the basis of the received signals, the RCD 6100 may deliver the command/address CA to the plurality of memory devices 6210 to 6290 and may control the plurality of data buffers DB.

The plurality of memory devices 6210 to 6290 may be respectively connected with the plurality of data buffers DB through memory data lines MDQ.

In an embodiment, each of the plurality of memory devices 6210 to 6290 includes the ECC circuit described with reference to FIGS. 1 to 16 and may operate based on the method described with reference to FIGS. 1 to 16. The plurality of data buffers DB may exchange data with an external device (e.g., a host or a memory controller) through a plurality of data lines DQ.

In an embodiment, the memory module 6000 illustrated in FIG. 22 may have the form factor of a load reduced dual in-line memory module (LRDIMM). However, the scope of the present disclosure is not limited thereto. For example, the memory module 6000 may have the form factor of a registered DIMM (RDIMM) in which the plurality of data buffers DB are not included.

In an embodiment, the memory module 6000 may further include an ECC circuit located outside the plurality of memory devices 6210 to 6290, and the ECC circuit may be configured to operate based on the method described with reference to FIGS. 1 to 16.

In an embodiment, one of the plurality of memory devices 6210 to 6290 may be configured to store parity data. The parity data may be provided from an external device (e.g., a host or a memory controller). In this case, the external device may include the ECC circuit described with reference to FIGS. 1 to 16 or may operate based on the method described with reference to FIGS. 1 to 16.

FIG. 23 is a diagram of a system 7000 to which a storage device is applied, according to an embodiment. The system 7000 of FIG. 23 may basically be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IOT) device. However, the system 7000 of FIG. 23 is not necessarily limited to the mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

Referring to FIG. 1, the system 7000 may include a main processor 7100, memories (e.g., 7200a and 7200b), and storage devices (e.g., 7300a and 7300b). In addition, the system 7000 may include at least one of an image capturing device 7410, a user input device 7420, a sensor 7430, a communication device 7440, a display 7450, a speaker 7460, a power supplying device 7470, and a connecting interface 7480.

The main processor 7100 may control all operations of the system 7000, more specifically, operations of other components included in the system 7000. The main processor 7100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 7100 may include at least one CPU core 7110 and further include a controller 7120 configured to control the memories 7200a and 7200b and/or the storage devices 7300a and 7300b. In some embodiments, the main processor 7100 may further include an accelerator 1130, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor 7100.

The memories 7200a and 7200b may be used as main memory devices of the system 7000. Although each of the memories 7200a and 7200b may include a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), each of the memories 7200a and 7200b may include non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories 7200a and 7200b may be implemented in the same package as the main processor 7100.

The storage devices 7300a and 7300b may serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have larger storage capacity than the memories 7200a and 7200b. The storage devices 7300a and 7300b may respectively include storage controllers (STRG CTRL) 7310a and 7310b and NVM (Non-Volatile Memory)s 7320a and 7320b configured to store data via the control of the storage controllers 7310a and 7310b. Although the NVMs 7320a and 7320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 7320a and 7320b may include other types of NVMs, such as PRAM and/or RRAM.

The storage devices 7300a and 7300b may be physically separated from the main processor 7100 and included in the system 7000 or implemented in the same package as the main processor 7100. In addition, the storage devices 7300a and 7300b may have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system 100 through an interface, such as the connecting interface 7480 that will be described below. The storage devices 7300a and 7300b may be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, but without being limited thereto.

The image capturing device 7410 may capture still images or moving images. The image capturing device 7410 may include a camera, a camcorder, and/or a webcam. The user input device 7420 may receive various types of data input by a user of the system 7000 and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone. The sensor 7430 may detect various types of physical quantities, which may be obtained from the outside of the system 7000, and convert the detected physical quantities into electric signals. The sensor 7430 may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor. The communication device 7440 may transmit and receive signals between other devices outside the system 7000 according to various communication protocols. The communication device 7440 may include an antenna, a transceiver, and/or a modem. The display 7450 and the speaker 7460 may serve as output devices configured to respectively output visual information and auditory information to the user of the system 7000. The power supplying device 7470 may appropriately convert power supplied from a battery (not shown) embedded in the system 7000 and/or an external power source, and supply the converted power to each of components of the system 7000. The connecting interface 7480 may provide connection between the system 7000 and an external device, which is connected to the system 7000 and capable of transmitting and receiving data to and from the system 7000. The connecting interface 7480 may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface. In an embodiment, the memories 7200a and 7200b are the memory device including the ECC circuit described in FIGS. 1 to 16, and may operate based on the operation method described in FIGS. 1 to 16.

The above description refers to detailed embodiments for carrying out the present disclosure. Embodiments in which a design is changed simply or which are easily changed may be included in the present disclosure as well as an embodiment described above. In addition, technologies that are easily changed and implemented by using the above embodiments may be included in the present disclosure. While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

According to an embodiment of the present disclosure, it is possible to provide an error correction code, which has improved reliability, improved performance, and a simple structure as a decoding circuit configuration of an error correction code circuit is simplified, a memory device including the error correction code, and an operating method of the error correction code.

While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A memory device, comprising: a memory cell array; andan error correction code (ECC) circuit configured to correct an error in a data code read out from the memory cell array, the ECC circuit comprising: a syndrome calculating circuit configured to operate a plurality of syndromes based on the data code and an H-matrix;an error location detecting circuit configured to:generate an error vector based on the plurality of syndromes; andgenerate an 0-th error vector element corresponding to a 0-th field element by performing a 0-th error location operation on the 0-th field element among a plurality of field elements based on an error location polynomial, and a first error vector element corresponding to a first field element based on a result of the 0-th error location operation; and an error correcting circuit configured to correct an error within the data code based on the error vector, and output corrected data.

2. The memory device of claim 1, wherein the error location detecting circuit comprises: a coefficient calculator circuit configured to generate a plurality of coefficients based on the plurality of syndromes; andan error vector generator circuit configured to generate the error vector based on the plurality of coefficients from the coefficient calculator circuit.

3. The memory device of claim 2, wherein the error vector generator circuit comprises: a 0-th pair checker configured to generate the 0-th error vector element corresponding to the 0-th field element and the first error vector element corresponding to the first field element, based on the plurality of coefficients.

4. The memory device of claim 3, wherein the 0-th field element and the first field element satisfy Equation 1: αp1=αp0+αj, where αp0 denotes the 0-th field element, αp1 denotes the first field element, and αj denotes one of the plurality of field elements of a Galois field to form the H-matrix.

5. The memory device of claim 4, wherein the 0-th pair checker comprises: a first order term calculator configured to generate a first order term for the 0-th field element in the error location polynomial based on a first coefficient among the plurality of coefficients;a second order term calculator configured to generate a second order term for the 0-th field element in the error location polynomial based on a second coefficient among the plurality of coefficients;a 0-th bit-wise XOR logic configured to output a 0-th result of the error location polynomial for the 0-th field element by performing a bit-wise XOR operation on a 0-th coefficient among the plurality of coefficients, the first order term, and the second order term;a 0-th determiner circuit configured to generate the 0-th error vector element based on the 0-th result;a first bit-wise XOR logic circuit configured to output a first result of the error location polynomial for the first field element by performing a bit-wise XOR operation on a first common coefficient among the plurality of coefficients and the 0-th result; anda first determiner circuit configured to generate the first error vector element based on the first result.

6. The memory device of claim 5, wherein the first coefficient corresponds to a square of a first syndrome; wherein the second coefficient corresponds to the first syndrome; wherein the 0-th coefficient corresponds to a sum of a cube of the first syndrome and a third syndrome; wherein the first common coefficient corresponds to a sum of a product of the αj and the first syndrome, and a product of a square of the first syndrome and the αj; wherein the first syndrome corresponds to a product of the data code and an upper portion matrix of the H-matrix; and wherein the third syndrome corresponds to a product of the data code and a lower portion matrix of the H-matrix.

7. The memory device of claim 5, wherein the error vector generator further comprises: a first pair checker configured to generate a second error vector element corresponding to a second field element and a third error vector element corresponding to a third field element, based on the plurality of coefficients; andwherein the second field element and the third field element satisfy Equation 2:αp3=αp2+αj, where αp2 denotes the second field element, αp3 denotes the third field element, and αj denotes the one of the plurality of field elements of the Galois field to form the H-matrix.

8. The memory device of claim 7, wherein each of the 0-th field element, the first field element, the second field element, and the third field element correspond to one of a plurality of columns of the H-matrix; and wherein the 0-th field element, the first field element, the second field element, and the third field element are binary vectors independent of each other.

9. The memory device of claim 7, wherein the first pair checker comprises: a first order term calculator configured to generate a first order term for the second field element in the error location polynomial based on the first coefficient;a second order term calculator configured to generate a second order term for the 0-th field element in the error location polynomial based on the second coefficient;a second bit-wise XOR logic circuit configured to output a second result of the error location polynomial for the second field element by performing a bit-wise XOR operation on the 0-th coefficient, a first order term for the second field element, and a second order term for the second field element;a second determiner circuit configured to generate the second error vector element based on the second result;a third bit-wise XOR logic circuit configured to output a third result of the error location polynomial for the third field element by performing a bit-wise XOR operation on the first common coefficient and the second result; anda third determiner circuit configured to generate the third error vector element based on the third result.

10. The memory device of claim 5, wherein the 0-th pair checker is configured to generate a second error vector element for a second field element.

11. The memory device of claim 10, wherein the 0-th field element and the second field element satisfy Equation 3: αp2=αp0+αk, where αp0 denotes the 0-th field element, αp2 denotes the second field element, and αk denotes one, which is different from the αj, from among the plurality of field elements of the Galois field to form the H-matrix.

12. The memory device of claim 11, wherein the 0-th pair checker further comprises: a second bit-wise XOR logic circuit configured to output a second result of the error location polynomial for the second field element by performing a bit-wise XOR operation on the first common coefficient and the 0-th result; anda second determiner circuit configured to generate the second error vector element based on the second result.

13. The memory device of claim 5, wherein the 0-th pair checker comprises: a third order term calculator configured to generate a third order term for the 0-th field element in the error location polynomial based on a third coefficient among the plurality of coefficients; andwherein the 0-th bit-wise XOR logic circuit is configured to output a 0-th result of the error location polynomial for the 0-th field element by performing a bit-wise XOR operation on the 0-th coefficient, the first order term, the second order term, and the third order term.

14. The memory device of claim 1, further comprising: a command/address (CA) buffer configured to receive and buffer CA signals from an external device;an address decoder configured to receive an address signal from the CA buffer and to decode the address signal;a command decoder configured to receive a command signal from the CA buffer and to decode the command signal;a row decoder configured to control a plurality of word lines connected to the memory cell array depending on the address decoding result of the address decoder;a column decoder configured to control a plurality of bit lines connected to the memory cell array depending on the address decoding result of the address decoder; anda sense amplifier and write driver configured to read out the data code stored in the memory cell array under control of the command decoder.

15. The memory device of claim 14, further comprising: an I/O circuit configured to output data, in which the error is corrected by the ECC circuit, to the external device in synchronization with a data strobe signal.

16. An ECC circuit configured to correct an error in a data code stored in a memory device, comprising: a syndrome generating circuit configured to generate a plurality of syndromes based on the data code read out from the memory device and a H-matrix;an error location detecting circuit configured to generate an error vector based on the plurality of syndromes and a plurality of field elements of the H-matrix, the error location detecting circuit including a coefficient calculator configured to generate a plurality of coefficients used in an error location polynomial based on the plurality of syndromes, and an error vector generator configured to generate the error vector based on the plurality of coefficients; andan error correcting circuit configured to correct an error of the data code based on the error vector;wherein the error vector generator includes a plurality of pair checkers configured to perform an error location operation on a plurality of pairs;wherein the plurality of pairs includes at least two field elements among the plurality of field elements; andwherein the at least two field elements included in each of the plurality of pairs satisfy a predetermined condition.

17. The ECC circuit of claim 16, wherein a length of the data code is a first number of bits, and a number of the plurality of pair checkers is a second number, and wherein the second number is a natural number less than the first number of bits.

18. The ECC circuit of claim 16, wherein a m-th pair among the plurality of pairs includes a 2m-th field element and a (2m+1)-th field element among the plurality of field elements, where m is a non-negative integer; andwherein the 2m-th field element and the (2m+1)-th field element satisfy Equation 4:αp2m+1=αp2m+αj, where αp2m denotes the 2m-th field element, αp2m+1 denotes the (2m+1)-th field element, and αj denotes one of the plurality of field elements of a Galois field to form the H-matrix.

19. The ECC circuit of claim 18, wherein a m-th pair checker among the plurality of pair checkers includes: a first order term calculator configured to generate a first order term for the 2m-th field element in the error location polynomial based on a first coefficient among the plurality of coefficients;a second order term calculator configured to generate a second order term for the 2m-th field element in the error location polynomial based on a second coefficient among the plurality of coefficients;a 2m-th bit-wise XOR logic circuit configured to generate a 2m-th result of the error location polynomial for the 2m-th field element by performing a bit-wise XOR operation on a 0-th coefficient among the plurality of coefficients, the first order term, and the second order term;a 2m-th determiner circuit configured to generate a 2m-th error vector element among a plurality of error vector elements of the error vector based on the 2m-th result;a (2m+1)-th bit-wise XOR logic circuit configured to generate a (2m+1)-th result of the error location polynomial for the (2m+1)-th field element by performing a bit-wise XOR operation on a common coefficient among the plurality of coefficients and the 2m-th result; anda (2m+1)-th determiner circuit configured to generate a (2m+1)-th error vector element among the plurality of error vector elements of the error vector based on the (2m+1)-th result.

20. An operating method of an ECC circuit, comprising: generating a plurality of syndromes based on a data code;generating an error vector based on the plurality of syndromes, by generating a first error vector element corresponding to a first field element by performing an error location operation on the first field element based on the plurality of syndromes, and generating a second error vector element corresponding to a second field element based on a result of an error location operation on the first field element; andcorrecting an error in the data code based on the error vector.

21. (canceled)