The present disclosure generally relates to semiconductor manufacturing, and specifically relates to semiconductor manufacturing using extreme ultraviolet (EUV) lithography.
EUV photomasks work by reflecting light. A typical EUV photomask (also referred to as a mask or reticle) is a complex stack of multilayered silicon and molybdenum. Photomasks are essential in generating the transistor and metal trace patterns on the wafer (e.g., silicon/III-V wafer). An advanced technology node like 14 nm or 7 nm may require about 50 to 100 photomasks, with each photomask typically costing between $350k and $750k. Thus, there is a significant investment needed from a technology development perspective to optimize the manufacturing process before moving into high volume. OPC (optical proximity correction) is a critical aspect of photomask development that optimizes the pattern on the mask depending on the light wavelength, diffraction compensation, etc. If done incorrectly, a redesign of the mask may be needed, and the cost and time taken to design and make new masks may be very high.
Embodiments of the present disclosure present a polymer crystal-based photomask which allows for the users to optimize the OPC (or other pattern related issues) during the lithography process. The photomask can be modified in-situ depending on the OPC, angle of EUV light used, and the type of pattern to be transferred on the wafer with photoresist.
In one aspect, the present disclosure relates to a photomask for EUV lithography. The photomask may include: a substrate; and one or more pixel units formed over the substrate. Each pixel unit may include: at least one polymer crystal element configured to interact with extreme ultraviolet (EUV) light based on an orientation of the polymer crystal element; and a plurality of electrodes configured to control the orientation of the polymer crystal element by applying voltage across the polymer crystal element. Each pixel unit is controlled by the respective plurality of electrodes independently, and the one or more pixel units generate a pattern for lithography upon exposure to the EUV light.
In another aspect, the present disclosure relates to a method for EUV lithography. The method may include receiving an instruction comprising a target photomask design; generating an OPC-adjusted mask pattern based on the photomask design; determining a pixel pattern based on the OPC-adjusted mask pattern; and configuring one or more pixel units of a polymer crystal-based photomask based on the determined pixel pattern. Each of the one or more pixel units may include at least one polymer crystal element configured to interact with extreme ultraviolet (EUV) light based on an orientation of the polymer crystal element; and a plurality of electrodes configured to control the orientation of the polymer crystal element by applying voltage across the polymer crystal element. Each pixel unit may be controlled by the respective plurality of electrodes independently, and the one or more pixel units generate the determined pixel pattern for lithography upon exposure to the EUV light.
The Figures (FIGS.) and the following description describe certain embodiments by way of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods may be employed without departing from the principles described. Wherever practicable, similar or like reference numerals identify similar or identical structural elements or identify similar or like functionality. Where elements share a common numeral followed by a different letter, the elements are similar or identical. The numeral alone refers to any one or any combination of such elements.
Embodiments relate to an EUV photomask having a pixel array with polymer crystals (such as liquid crystals) that change from absorbance to reflectance of EUV light by changing the polymer crystals' orientation. The pixel array includes a plurality of pixel units that are controlled by electrodes. By using the pixel units that are able to selectively absorb or reflect the EUV light, the photomask that can be modified in-situ depending on OPC, angle of EUV light used, the type of pattern to be transferred on the wafer with photoresist, or some combination thereof. The proposed design would enable rapid prototyping without the need for a semiconductor mask house, as the polymer crystal based photomask may allow for OPC related issues to be rectified and corrected by adjusting the electrodes (e.g., thin film transistors) that control the orientations of the crystals, rather than undergoing a very expensive redesign of the mask. In addition, the need for multiple masks is reduced, since the polymer crystal-based photomask can be programmed to display different layers, enabling a reduction in time needed for mask swapping.
Optical Proximity Correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. Due to the limitations of light to maintain the edge placement integrity of the original design, after processing, the projected images (i.e., the etched images on the wafer) may appear with irregularities such as line widths that are narrower or wider than designed. Such distortions, if not corrected for, may significantly alter the electrical properties of what was being fabricated. The OPC may correct these errors by changing the pattern on the photomask used for imaging, for example, by moving edges or adding extra polygons to the pattern written on the photomask. The objective is to reproduce on the wafer, as well as possible, the original layout drawn by the designer. During the OPC, design level elements are represented as a set of polygons that are carved onto a pixelated template which is the mask. The design of the mask can be adjusted based on the incident angle of light, diffraction, interference, divergence, wavelength, etc., to ensure the desired pattern is printed on the wafer (and quality degradation is addressed to avoid distortions). For example,
For advanced lithography processes, a large number of EUV photomasks may be needed, e.g., for 5 nm technology nodes, approximately 50 EUV photomasks may be needed. In another example, multiple masks are required to generate a fin field-effect transistor (FinFET) or a back end of line (BEOL). Approximately 10 to 15 layers of metal lines form the logic trace for the 14 nm node. Different types of masks, such as, metallization mask, Ohmic contact mask, emitter diffusion mask, base diffusion mask, isolation diffusion mask, buried layer mask, etc., may be used. In some embodiments, each layer requires several masks to ensure the desired pattern is etched properly in the photoresist. In addition, defects in a photomask (e.g., due to amplitude defects, phase defects, OPC not done right) may require a photomask to be redesigned, further increasing costs. Embodiments of the present disclosure present a polymer crystal-based photomask which allows for the users to optimize the OPC during the lithography process. By controlling the electrical field applied to the polymer crystal elements in the photomask, the polymer crystals elements can change their orientations to reflect or absorb the incident EUV light. In this way, a desired pattern of photomask can be achieved and adjusted during the lithography process without need to create a new mask.
Each pixel unit 310 may include at least one polymer crystal element 312 and a plurality of electrodes 314. In some embodiments, the plurality of electrodes 314 are configured to divide the photomask 300 into arrays and/or individual pixel units 310. The polymer crystal element 312 may be a liquid crystal element configured to interact with the EUV light based the orientation of the polymer crystal elements 312. In some embodiments, each pixel unit 310 may include a plurality of polymer crystal elements 312 that are formed in arrays and/or stacked on multiple layers. For example, the photomask 300 may include a plurality of layers of pixel units 310 stacking on the substrate 302, and each layer of pixel units 310 may be configured to interact with the EUV light at a different wavelength. The plurality of electrodes 314 are connected to the circuitries in the active layer 304. In some embodiments, the photomask 300 may further include one or more thin film transistors (TNTs) that are coupled with the electrodes 314 for controlling the orientations of the polymer crystal elements 312. The electrodes 314 are configured to be electrically connected to the polymer crystal elements 312 to control the orientations of the polymer crystal elements 312 by applying voltages. Each pixel unit 310 may be controlled by the respective plurality of electrodes 314 independently. Alternatively, adjacent pixel units 310 may share at least a portion of the electrodes 314, and some of the pixel units 310 may form into a plurality of groups. The pixel units 310 in each group may be controlled by the same electrodes 314 collectively.
In some embodiments, the polymer crystal element 312 may be a cholesteric liquid crystal (CLC) material. The CLC materials can be used for selective reflectance, where the reflectance change may be voltage induced (e.g., based on voltage applied at set angle relative to helical axes of the polymer). In some embodiments, other possible stimuli, such as heat, mechanical compression/shear, or another wavelength of light (e.g., for CLC materials containing azobenzene chiral dye) may be used to control the selective reflectance of the CLC material. In some embodiments, because the orientation of helical axes of the polymer crystals may affect how the polymer crystal elements reflect different wavelengths of light, multiple layers of CLCs may be used to interact with multiple different wavelengths.
The pellicle layer 306 may be a thin, transparent membrane that covers the photomask 300 during the lithography process. For example, the pellicle layer 306 may be made of polysilicon. The pellicle layer 306 is a dust cover, as it prevents particles and contaminates from falling on the photomask 300. The pellicle layer 306 is positioned on the pixel units 310 and exposed to the incident EUV light. In some embodiments, the pixel unit 310 may further include an alignment layer 316 that is configured to ensure correct mask orientation and check alignment accuracy.
In some embodiments, the photomask 500 may include one or more backplates 530, as shown in
In some embodiments, the photomask 500 may further include slider rails along X and Y axes. As shown in
The photomask disclosed herein uses pixels of polymer material (e.g., liquid crystal) to enable rapid prototyping of test wafers and reduced time to manufacture, significantly reducing investment in mask development and mask house. For example, in some embodiments a single polymeric material-based photomask can be programmed to display different patterns, reducing expenses related to replacement or redesign of conventional photomasks. The disclosed photomask may also allow for fast optimization of layer thicknesses based on performance, where layer thicknesses in FinFETs and advanced technology nodes can be optimized without the need for expensive mask redesign. In some embodiments, micro lenses and waveguides can be prototyped, tested, and manufactured in significantly less time and reduced monetary investment.
The machine may be a server computer, a client computer, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a smartphone, a tablet, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions 724 (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute instructions 124 to perform any one or more of the methodologies discussed herein.
The example computer system 700 includes a processor 702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), one or more application specific integrated circuits (ASICs), one or more radio-frequency integrated circuits (RFICs), or any combination of these), a main memory 704, and a static memory 706, which are configured to communicate with each other via a bus 708. The computer system 700 may further include visual display interface 710. The visual interface may include a software driver that enables displaying user interfaces on a screen (or display). The visual interface may display user interfaces directly (e.g., on the screen) or indirectly on a surface, window, or the like (e.g., via a visual projection unit). For ease of discussion the visual interface may be described as a screen. The visual interface 710 may include or may interface with a touch enabled screen. The computer system 700 may also include alphanumeric input device 712 (e.g., a keyboard or touch screen keyboard), a cursor control device 714 (e.g., a mouse, a trackball, a joystick, a motion sensor, or other pointing instrument), a storage unit 716, a signal generation device 718 (e.g., a speaker), and a network interface device 720, which also are configured to communicate via the bus 708.
The storage unit 716 includes a machine-readable medium 722 on which is stored instructions 724 (e.g., software) embodying any one or more of the methodologies or functions described herein. The instructions 724 (e.g., software) may also reside, completely or at least partially, within the main memory 704 or within the processor 702 (e.g., within a processor's cache memory) during execution thereof by the computer system 700, the main memory 704 and the processor 702 also constituting machine-readable media. The instructions 724 (e.g., software) may be transmitted or received over a network 726 via the network interface device 720.
While machine-readable medium 722 is shown in an example embodiment to be a single medium, the term “machine-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) able to store instructions (e.g., instructions 724). The term “machine-readable medium” shall also be taken to include any medium that is capable of storing instructions (e.g., instructions 724) for execution by the machine and that cause the machine to perform any one or more of the methodologies disclosed herein. The term “machine-readable medium” includes, but not be limited to, data repositories in the form of solid-state memories, optical media, and magnetic media.
The foregoing description of the embodiments has been presented for illustration; it is not intended to be exhaustive or to limit the patent rights to the precise forms disclosed. Persons skilled in the relevant art can appreciate that many modifications and variations are possible considering the above disclosure.
Some portions of this description describe the embodiments in terms of algorithms and symbolic representations of operations on information. These algorithmic descriptions and representations are commonly used by those skilled in the data processing arts to convey the substance of their work effectively to others skilled in the art. These operations, while described functionally, computationally, or logically, are understood to be implemented by computer programs or equivalent electrical circuits, microcode, or the like. Furthermore, it has also proven convenient at times, to refer to these arrangements of operations as modules, without loss of generality. The described operations and their associated modules may be embodied in software, firmware, hardware, or any combinations thereof.
Any of the steps, operations, or processes described herein may be performed or implemented with one or more hardware or software modules, alone or in combination with other devices. In one embodiment, a software module is implemented with a computer program product comprising a computer-readable medium containing computer program code, which can be executed by a computer processor for performing any or all the steps, operations, or processes described.
Embodiments may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, and/or it may comprise a general-purpose computing device selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non transitory, tangible computer readable storage medium, or any type of media suitable for storing electronic instructions, which may be coupled to a computer system bus. Furthermore, any computing systems referred to in the specification may include a single processor or may be architectures employing multiple processor designs for increased computing capability.
Embodiments may also relate to a product that is produced by a computing process described herein. Such a product may comprise information resulting from a computing process, where the information is stored on a non transitory, tangible computer readable storage medium and may include any embodiment of a computer program product or other data combination described herein.
Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the patent rights. It is therefore intended that the scope of the patent rights be limited not by this detailed description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of the embodiments is intended to be illustrative, but not limiting, of the scope of the patent rights, which is set forth in the following claims.
This application claims the benefit of U.S. Provisional Application No. 63/257,363, filed Oct. 19, 2021, which is incorporated by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
63257363 | Oct 2021 | US |