Patent Application
20160005680
This disclosure relates to integrated circuit (IC) packaging. More particularly, this disclosure relates to QFN or other exposed-pad non-leaded packaging, having an exposed heat sink upon which a device die is affixed.
The electronics industry continues to rely upon advances in semiconductor technologies to realize higher-function devices in more compact areas. For many applications realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
Many varieties of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor field-effect transistors (MOSFET), such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors. Such MOSFET devices include an insulating material between a conductive gate and silicon-like substrate; therefore, these devices are generally referred to as IGFETs (insulated-gate FET).
Having manufactured a number of electronic devices on a wafer substrate, a particular challenge is to package these devices for their given purpose. As the complexity of portable systems increases, there is a commensurate need to reduce the size of the individual components which make up the system; the system often is laid out on a printed circuit substrate. One way to reduce the size of individual components is through techniques that reduce the size of packages which contain these devices. A package, often used, is the QFN (quad flat no-leads) package to reduce the vertical profile of the devices attached to the system printed circuit substrate. However, some applications may require the QFN device handle sufficient power that may thermally stress the device die and packaging. Consequently, a heat sink is required to dissipate any excess heat; yet, the heat sink cannot add appreciably to the vertical profile. There is a need for a QFN or similar package that can accommodate a device die with a heat sink with an acceptable profile.
The present disclosure addresses the challenge of making a QFN semiconductor having a lower vertical profile with enhanced thermal performance. A plurality of device die are attached to a heat sink array. The plurality of device die are singulated into individual devices attached to a heat sink portion. These individual device die/heat sink assemblies are placed on a carrier tape along with a lead frame array. The device die are wire bonded to the lead frame array. The assemblies are encapsulated in a molding compound. The molded assemblies are singulated into individual devices. The devices have exposed electrical contacts and heat sink on its underside. The exposed heat sink provides enhanced thermal coupling from the device to the printed circuit board (PCB) to which it is mounted.
In addition, the present disclosure addresses a long-felt need to decouple the die-bonding conditions from their detrimental effects on lead frame and/or carrier. For high-temperature die-bonding, these effects can include oxidation of the lead frame surface, causing problems with mold adhesion or wire bonding, or adhesive decomposition in the case of a tape-based carrier.
Furthermore, the exposed heat sink underside provides for a high-integrity electrical connection between the device die and printed circuit board (PCB) to which it is soldered.
In an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface, the heat sink array having die placement areas on the top-side surface, die bonding a plurality of active device die onto the die placement areas on the heat sink array, and singulating the plurality of active device die into an individual heat sink device die having a heat sink portion attached to its underside.
In an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises, providing a heat sink array having a top-side surface and an under-side surface, the heat sink array having die placement areas on the top-side surface, the heat sink array having notches on the under-side surface, the notches defining a separation among one another of the die placement areas. A plurality of active device die are die bonded, with a die attach material, onto the die placement areas on the heat sink array, the die bonding is at a predetermined elevated-temperature. The plurality of active device are singulated into an individual heat sink device die having a heat sink portion attached to its underside, the heat sink array being singulated about the middle of the notches. The method further provides a lead frame with bond pad landings, the bond pad landings having upper surfaces and opposite lower surfaces, the bond pad landings surrounding a die placement area. The lead frame is mounted, on the lower surface, onto an adhesive carrier tape. In the die placement area, the heat sink device die is placed, with its under-side surface onto the adhesive carrier tape. The heat sink device die is conductively bonded to the bond pad landings. The conductively bonded heat sink device die and lead frame are encapsulated in a molding compound. Removing the adhesive carrier tape, exposes the under-side surface of the heat sink device die and the opposite lower surfaces of the bond pads.
In an example embodiment, there is an integrated circuit (IC) having enhanced heat dissipation. The IC comprises an active device die of having a top-side surface and an under-side surface. A bondable die-attach layer is on the under-side surface of the active device die. A heat sink assembly has a top-surface and an opposite under-side surface to accommodate the active device die, and wherein the active device die is bonded to the top-side surface of the heat sink assembly via the bondable die-attach layer.
The above summaries of the present invention are not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follow.
The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
The present disclosure has been found useful in enhancing the heat dissipation characteristics a FET device assembled in a QFN package. These devices may be expected to dissipate about 100 mW to about 5 W, or more.
In an example process the wafers are ground down to about 200 μm to prepare the device die that will ultimately be assembled onto the heat sink. To further reduce vertical profile, in another example process, the back grind thickness may be reduced down to 50 μm, after this process the back side metallization is applied. This metallization is in the order of a few micro-meters. One, or more metallization deposition techniques may be applied or even a combination of them (e.g., initial sputter layer which is increased in thickness by a plating process). The metallization provides for sufficient adhesion of the device die as it is attached to the heat sink.
The present disclosure obviates the need to attach a separate heat sink to the QFN package in that the underside of the package is in direct contact with the PCB; the PCB provides a large area in which heat may be dissipated. Having prepared the underside of the devices, the attaching of the device die to the heat sink portion prior to assembly in a QFN lead frame, provides for better heat spreading that for a device die packaging in a conventional QFN configuration.
Making reference to
In another example process, the device die having a bondable underside surfaces may be prepared, in advance, in a separate process or from a third party. The prepared device die are then appropriate for bonding to the heat sink array, as described in the present disclosure.
As determined by the device die type, a heat sink array is prepared 125. Having prepared the heat sink array, device die are bonded in die-attach areas on the heat sink array 130. The device die having solderable undersides may be re-flow soldered onto the die attach areas of the heat sink array 125.
The present disclosure permits the use of high-temperature die-bonding. The lead frame is spared from deleterious effects of the process temperatures, the effects including lead frame oxidation which may result in poor molding compound adhesion or wire-bonding problems. The user may make use of higher-temperature die-attach techniques which may include, but are not necessarily limited to, solder, eutectic, silver (Ag)-sinter, conductive adhesive, etc. For example, Ag-sinter is performed at about 200° C. to about 300° C., Pb-solder at about 350° C., eutectic at about 400° C., conductive adhesive at 150° C. to 250° C.
Further, the high temperatures may not be compatible with use of adhesive carrier tape; the high temperatures degrade the tape.
The heat sink array with attached device die is singulated into individual assemblies 135. For the type of device die/heat sink assembly, a suitable lead frame array is selected 140. Onto carrier tape, the lead frame array along with the device die/heat sink assemblies are placed 145. The device die/heat sink assemblies are surrounded by bond pad areas of the lead frame array. Devices are wire bonded to the bond pad areas on the lead frame array 150. The array of device die/heat sink assemblies and the lead frame array are encapsulated 155.
In another example embodiment, the use of wire bonds may not be appropriate, especially were minimizing interconnect inductance and/or resistance is critical. Ribbon bonding may often be used. For a given application, a wire bond may have a given diameter of about 25.4 μm (0.001 in) and a ribbon bond may have a cross-section of about 25.4 μm×76.2 μm (0.001 in×0.003 in). Interconnect inductance can cause impedance mismatches, ringing, distortion pulses. For high speed circuits, excess inductance results in reduced bandwidth. Because of this need for reduced inductance, ribbon bonding may often specified instead of wire bonding. This is especially true for wide band components where parameters such as group delay must be controlled over a very wide bandwidth. Ribbon bonds may be preferred because a typical ribbon bond has two to three times less inductance than that of a wire bond. The increased cross-sectional area serves to lower the resistance of typical ribbon bonds compared to typical wire bonds, which in turn lowers RDSon in relevant electrical pathways. More detailed information may be found in “Quick Reference Guide: Ribbon Bond vs. Wire Bond.” NATEL Engineering Co., Inc., Chatsworth, Calif., USA, pp.4.
In another example embodiment, a clip bonding technique may be used. Further information may be found in U.S. patent application titled, “Exposed Die Clip Bond Power Package” of Leonardus van Gemert and Emil Israel, Docket No. 81626917US01 (Application No. ##/###,###). This application is incorporated by reference in its entirety.
The device die/heat sink assemblies may be configured as strips, for example, 50 mm×150 mm or 100 mm×300 mm. Die sizes which may be used range from about 1 mm×1 mm to about 10 mm×10 mm. The number of device pins may range from 2 to 50.
After encapsulation, the carrier tape is removed. The assembled array of encapsulated devices is then sawed apart into individual assembled devices whose lead frame contacts are exposed, as well, as the exposed heat sink 160; these exposed contact areas would be coplanar. The heat sink and exposed lead frame contacts would be prepared appropriately so that they have surfaces with a sufficient affinity to solder.
In an example embodiment, as depicted in
Refer to
The mounted and wire bonded device die/heat sink assemblies 235 are encapsulated in a molding compound 270. After molding, the carrier tape 250 is removed (See
In example processes, carrier ring apparatus may be used. For example, the carrier ring apparatus may be 50 mm'200 mm or 80 mm×300 mm, though other sizes may be available owing to the particular assembly equipment used. If the lead frame is mechanically robust, a carrier ring is not required. Equivalently, a carrier plate of glass, ceramic, or metal can be used.
The number of fabricated devices can range from several hundred to even several thousand pieces. QFN package sizes may range from millimeters on a side down to about 0.5 mm×1 mm. Other leadless (metal-based) packages may include, but are not necessarily limited to, aQFN (advanced quad flat no lead), LLGA (leadless land grid array), TLA (thermal leadless array), EFLGA (electroforming type land grid array), and TLEM (transcription lead of electroforming method), etc. The embodiments in the present disclosure may also be implemented in exposed-pad leaded devices such as HSOP (heat slug outline package), HQFP (heatsink quad flat pack) or other similar package types.
Making reference to
Having been able to apply higher temperature processing to the die attach process in the die attaching of the device die onto the heat sink portion, a QFN device has been assembled having a greater power dissipation performance and improved reliability. The die attach process occurs separately and thus, QFN lead frame or carrier is spared from the effects of the die attach process.
Various exemplary embodiments are described in reference to specific illustrative examples. The illustrative examples are selected to assist a person of ordinary skill in the art to form a clear understanding of, and to practice the various embodiments. However, the scope of systems, structures and devices that may be constructed to have one or more of the embodiments, and the scope of methods that may be implemented according to one or more of the embodiments, are in no way confined to the specific illustrative examples that have been presented. On the contrary, as will be readily recognized by persons of ordinary skill in the relevant arts based on this description, many other configurations, arrangements, and methods according to the various embodiments may be implemented.
To the extent positional designations such as top, bottom, upper, lower have been used in describing this disclosure, it will be appreciated that those designations are given with reference to the corresponding drawings, and that if the orientation of the device changes during manufacturing or operation, other positional relationships may apply instead. As described above, those positional relationships are described for clarity, not limitation.
The present disclosure has been described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto, but rather, is set forth only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, for illustrative purposes, the size of various elements may be exaggerated and not drawn to a particular scale. It is intended that this disclosure encompasses inconsequential variations in the relevant tolerances and properties of components and modes of operation thereof. Imperfect practice of the invention is intended to be covered.
Where the term “comprising” is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g. “a” “an” or “the”, this includes a plural of that noun unless something otherwise is specifically stated. Hence, the term “comprising” should not be interpreted as being restricted to the items listed thereafter; it does not exclude other elements or steps, and so the scope of the expression “a device comprising items A and B” should not be limited to devices consisting only of components A and B. This expression signifies that, with respect to the present disclosure, the only relevant components of the device are A and B.
Numerous other embodiments of the disclosure will be apparent to persons skilled in the art without departing from the spirit and scope of the disclosure as defined in the appended claims.
