BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to one embodiment of the present invention during a fabrication step thereof;
FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 1;
FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 2;
FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 3;
FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 4;
FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 5;
FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 6;
FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 7;
FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 8;
FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 9;
FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 10;
FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 11;
FIG. 13 is a fragmentary cross-sectional view of a semiconductor device according to First Comparative Example during a fabrication step thereof;
FIG. 14 is a fragmentary cross-sectional view of the semiconductor device of First Comparative Example during a fabrication step following that of FIG. 13;
FIG. 15 is a fragmentary cross-sectional view of the semiconductor device of First Comparative Example during a fabrication step following that of FIG. 14;
FIG. 16 is a schematic view illustrating a treatment for equalizing the thickness distribution of an insulating film deposited on the main surface of a semiconductor wafer;
FIG. 17 is a schematic view of the control of the moving speed of an etchant nozzle which moves on a semiconductor wafer;
FIG. 18 is a graph showing the deposition thickness distribution of an insulating film when it is deposited on the main surface of a semiconductor wafer;
FIG. 19 is a graph showing the position of an etchant nozzle;
FIG. 20 is a graph showing a change rate of the deposition thickness of an insulating film in a radial direction of the main surface of a semiconductor wafer and a moving speed of an etchant nozzle;
FIG. 21 is a graph showing an etching amount of an insulating film in the treatment for equalizing the thickness distribution of an insulating film deposited on the main surface of a semiconductor wafer;
FIG. 22 is a graph showing the thickness distribution of an insulating film which has been deposited on the main surface of a semiconductor wafer and subjected to the treatment for equalizing the film thickness distribution;
FIG. 23 is a schematic view showing the equation representing an etching time of an insulating film;
FIG. 24 is a fragmentary cross-sectional view of a semiconductor device according to the one embodiment of the present invention during a fabrication step thereof;
FIG. 25 is a fragmentary cross-sectional view of a semiconductor device during a fabrication step following that of FIG. 24;
FIG. 26 is a fragmentary cross-sectional view of a semiconductor device during a fabrication step following that of FIG. 25;
FIG. 27 is a schematic view illustrating the treatment for equalizing the thickness distribution of an insulating film deposited on the main surface of a semiconductor wafer;
FIG. 28 is a graph showing the deposition thickness distribution of an insulating film when it is deposited on the main surface of a semiconductor wafer;
FIG. 29 is a graph showing the position of a rinse solution nozzle;
FIG. 30 is a graph showing a change rate of the deposition thickness of an insulating film in a radial direction of the main surface of a semiconductor wafer and a moving speed of a rinse solution nozzle;
FIG. 31 is a graph showing an etching amount of an insulating film deposited on the main surface of a semiconductor wafer in the treatment for equalizing the thickness distribution of the insulating film;
FIG. 32 is a graph showing the thickness distribution of an insulating film deposited on the main surface of a semiconductor wafer after the treatment for equalizing the film thickness distribution;
FIG. 33 is a schematic view showing the equation representing the etching time of an insulating film;
FIG. 34 is a schematic view illustrating the treatment for equalizing the deposition distribution of an insulating film deposited on the main surface of a semiconductor wafer;
FIG. 35 is a graph showing the deposition thickness distribution of an insulating film when it is deposited on the main surface of a semiconductor wafer;
FIG. 36 is a graph showing the positions of an etchant nozzle and rinse solution nozzle;
FIG. 37 is a graph showing the moving speed of each of an etchant nozzle and rinse solution nozzle;
FIG. 38 is a graph showing the etching amount of an insulating film deposited on the main surface of a semiconductor wafer in the treatment for equalizing the thickness distribution of the insulating film;
FIG. 39 is a graph showing the thickness distribution of an insulating film deposited on the main surface of a semiconductor wafer after the treatment for equalizing the thickness distribution of the insulating film;
FIG. 40 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a fabrication step thereof;
FIG. 41 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 40;
FIG. 42 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 41;
FIG. 43 is a fragmentary cross-sectional view of a semiconductor device according to Second comparative example during a fabrication step thereof;
FIG. 44 is a fragmentary cross-sectional view of the semiconductor device of Second comparative example during a fabrication step following that of FIG. 43;
FIG. 45 is a graph showing a size of an insulating film pattern at each position of a semiconductor wafer and an effective gate length of a gate electrode formed using the insulating film pattern having the size;
FIG. 46 is a fragmentary cross-sectional view of a semiconductor device according to a further embodiment of the present invention during its manufacturing step;
FIG. 47 is a fragmentary cross-sectional view of the semiconductor device during a fabrication step following that of FIG. 46;
FIG. 48 is a graph showing the etching amount of an insulating film pattern; and
FIG. 49 is a graph showing the size of an insulating film pattern at each position on the main surface of a semiconductor wafer and an effective gate length of a gate electrode formed using the insulating film pattern having the size.