The present invention relates to integrated circuits, and more particularly to circuits using nitrided silicon oxide.
The double peak structure can be obtained as follows. First, layer 140 is formed of pure silicon dioxide. Then layer 140 is nitrided using remote plasma nitridation (RPN) or decoupled plasma nitridation (DPN). RPN and DPN are described in U.S. Patent Application published as no. 2004/0185647 on Sep. 23, 2004, filed by Zhong Dong et al., entitled “Floating Gate Nitridation”, incorporated herein by reference. The plasma nitridation is followed by a thermal anneal. The anneal and subsequent thermal processing disadvantageously cause some of the nitrogen to diffuse from regions 140t, 140i into oxide bulk 140b.
Plasma nitridation can be replaced by an anneal in the presence of ammonia (NH3), or by heating the wafer in nitric oxide (NO). These steps can be followed by additional oxidation. See the aforementioned U.S. Pat. No. 5,939,763.
This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference.
In some embodiments of the present invention, a nitrided silicon oxide layer is formed on the silicon substrate's surface, possibly by prior art techniques, to provide a high nitrogen concentration near the substrate/oxide interface. Then a portion of the silicon oxide layer is etched away, leaving a thin layer of nitrided silicon oxide with a high nitrogen concentration. Then an oxidation step is performed (e.g. Rapid Thermal Oxidation, or RTO) to oxidize some of the silicon below the silicon oxide layer. Much of the nitrogen remains near the top surface of the silicon oxide layer, thus providing a sharp peak at the top surface (the top surface will be located near the polysilicon when the polysilicon is deposited). The high RTO temperature (1000-1100° C. in some embodiments) serves to bind the nitrogen with the silicon and oxygen atoms. Consequently, the nitrogen diffusion will be minimal in subsequent steps, insuring a high nitrogen concentration near the polysilicon and a low nitrogen concentration in the oxide bulk.
If desired, additional nitridation is performed (e.g. thermal nitridation) to increase the nitridation concentration near the silicon substrate. This nitridation step can be performed by prior art techniques. Nitrogen provided by a gaseous source (e.g. NO or N2O) will diffuse towards the substrate/oxide interface. The nitridation temperature is below the RTO temperature of the oxidation step in order to minimize disturbance of the nitrogen atoms present at the top surface during the RTO.
The invention is not limited to the embodiments described above. In some embodiments, a nitrogen containing layer is formed on a silicon containing region. Then a portion of the nitrogen containing layer is removed. Then thermal oxidation is performed. The invention is not limited to polysilicon or monocrystalline silicon. The invention can be used in non-volatile memories to form dielectric separating floating gates from control gates, select gates, and/or other elements of integrated circuits. The control and select gates can be formed side by side with the floating gates (rather than one on top of another). The MOS gates, the floating gates, and other elements do not have to be formed above the channel regions but can be formed in trenches or with other geometry, known or to be invented. The invention is not limited to the features or advantages described above. Other features are described below. The invention is defined by the appended claims.
The embodiments described in this section illustrate but do not limit the invention. Dimensions, process parameters, and other details are given for illustration and not to limit the invention. The invention is defined by the appended claims.
Thermal nitridation of oxide 210 results in formation of a nitrided silicon oxide layer 210N (
For simplicity,
Comment on the charts of
The thermal nitridation of oxide 210 can be replaced by plasma nitridation.
Then oxide 210 is partially etched down (
The wafer is heated in an oxygen containing atmosphere to grow silicon oxide under the layer 210N. See
If desired, oxide 140 can be nitrided to increase the nitrogen concentration in a sub-region 140i (
The fabrication can be completed with known techniques. For example, polysilicon 150 (
The invention is not limited to the embodiments described above. The invention is not limited to polysilicon or monocrystalline silicon, or to any dimensions, concentrations or doping levels. The invention is not limited to the data shown in the figures or in the tables. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
The present application is a division of U.S. patent application Ser. No. 11/248,705 filed on Oct. 11, 2005, incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
Parent | 11248705 | Oct 2005 | US |
Child | 11677768 | Feb 2007 | US |