The present application is based on Japanese priority application No. 2006-031317 filed on Feb. 8, 2006, the entire contents of which are hereby incorporated by reference.
The present invention generally relates to fabrication of semiconductor devices and more particularly to a method of fabricating a semiconductor device having a shallow trench isolation (STI) structure and a semiconductor device fabricated by such a method.
In the technical field of semiconductor devices, there is a known technology of device isolation called trench isolation. In the trench isolation technology, a device isolation trench is formed on a surface of a semiconductor substrate, and the device isolation trench thus formed is filled with an insulator film or a polysilicon film.
Historically, this method of trench isolation has been used in the semiconductor integrated circuit devices that include bipolar transistors. In the semiconductor integrated circuit devices that include bipolar transistors, a deep device isolation region has been needed for achieving the desired device isolation.
On the other hand, in recent years, the technology of trench isolation is used also in the semiconductor integrated circuit devices that include MOS transistors.
With the semiconductor integrated circuit devices that include MOS transistors, it is not necessary to provide the device isolation trench to have a depth as deep as in the case of the semiconductor integrated circuit devices that use bipolar transistors, but a relatively shallow trench of the depth of 0.1-1.0 μm is sufficient for achieving the desired device isolation. Such a structure is claimed Shallow Trench Isolation (STI) structure.
First, explanation will be made about the formation process of an STI device isolation structure with reference to
Referring to
Further, in the step of
Next, in the step of
Further, in the step of
Further, in the step of
Next, in the step of
Next, in the step of
Next, the surface of the silicon substrate 11 is subjected to a thermal oxidation processing, and there is formed a sacrifice silicon oxide film 22 as shown in
Next, as shown in
Further, in the step of
Further, sidewall insulation films SW are formed on the respective sidewall surfaces of the gate electrode 23G, and ion implantation of the impurity element of the conductivity type opposite to the conductivity type of the well region 10 is conducted again into the well region 10 while using the gate electrode 23G and the sidewall insulation films SW as a mask. After conducting activation, a source region 11c and a drain region 11d of high impurity concentration level are formed in the well region 10 at respective outer sides of the sidewall insulation films SW.
With the structure of
Meanwhile, with the semiconductor device of the structure of
When a compressive stress acting parallel to the substrate surface is applied to the device region, there is caused a significant decrease of electron mobility in the active region of the silicon substrate 11, and as a result, there is caused decrease in the saturation drain current. It should be noted that the effect of such a compressive stress is increased when the active region is miniaturized with miniaturization of the semiconductor device.
In order to suppress the occurrence of such compressive stress and to prevent occurrence of hump in the device characteristics or deterioration of leakage characteristics, there is a proposal of the technology that forms a silicon nitride film having a tensile stress on the inner wall surface of device isolation trench 16 via an intervening silicon oxide film. However, the problem of deterioration of saturation drain current in the n-channel MOS transistors, originating from the compressive stress exerted by the oxide film filling the device isolation trench, is becoming a serious problem with decrease of the gate width associated with device miniaturization.
Further, associated with the device miniaturization there is caused an increase in the aspect ratio of device isolation trench 16, and it is becoming difficult to fill the device isolation trench 16 by the insulation film 19. As a result, there arises a problem such as formation of seam (joint) in the insulation film 19 or formation of pores (void) in the insulation film 19. When there exists such a seam or void in the insulation film 19, there may be caused problems such as exposure of the void as a result of etching or anomaly in the shape of the insulator in the device isolation trench, while such a problem may cause various adversary effects in the later process steps of the semiconductor device.
Thus, importance of filling the device isolation trench 16 with the burying insulator film 19 is increasing while the difficulty of filling the device isolation trench 16 with the insulation film 19 is also increasing.
Conventionally, there is a proposal, as the means for reducing the compressive stress originating from the device isolation insulator film, of forming the device isolation insulator film by an SOG film or a pyrolytic CVD process that uses a source gas mixture of an O3-TEOS system.
Generally, the film formed from these materials has a poor film quality in the state immediately after film formation, and there is a need of conducting a thermal annealing process at the temperature of 900° C. or higher for achieving sufficient durability against the wet etching process.
On the other hand, because the insulation film 19 is formed primarily by a silicon oxide film, the film undergoes transformation to a film accumulating therein a compressive stress of the order of 100-200 MPa when a thermal annealing process is conducted at high temperature. It should be noted that the compressive stress is caused as a result of difference of thermal expansion coefficient between the film and Si. Such transformation to compressive film occurs even when the original film accumulates therein a tensile stress in the as-deposited state. Thus, decrease of the compressive stress cannot be attained by utilizing the internal stress accumulated in the film.
On the other hand, such an SOG film or O3-TEOS film contains a large amount of OH group inside the film, and thus, there is caused shrinkage in the film when a dehydration processing is applied to the film in the form of high temperature annealing process.
Thus, there is a report of decreasing the compressive stress in an insulation film filling a device isolation trench by inducing shrinkage in the insulation film after filling the device isolation trench. Thereby, there is caused a strong tensile stress in the insulation film with regard to the device isolation trench.
On the other hand, in the case of filling the device isolation trench with an SOG film, there arises a problem, from the coating characteristics of an SOG film, in that the amount of SOG held in the device isolation trench changes depending on the density of the device isolation trench patterns on the substrate. Thereby, there arises a problem in that it is difficult to control the film thickness of the SOG film formed on the substrate to cover different device isolation trench patterns. Further, because the film thickness changes depending on the density of patterns in the case of an SOG film, it becomes difficult to remove the insulation film from the substrate surface completely with such a structure by using a CMP process.
While it is possible to form the device isolation insulator film by using an O3-TEOS film, such an approach raises also a problem in that a thick film deposition takes place for the part where the device isolation trench patterns are formed with high density, contrary to the case of using a high-density plasma CVD process, and thus, there is caused the problem that the film thickness changes depending on the pattern density. Thereby, there is a need of etching back the thick deposition film by a dry etching process, while such an etch-back process requires additional mask processes that increases the cost of manufacturing the semiconductor devices. Further, the production yield of the semiconductor device is deteriorated.
Japanese Laid-Open Patent Application 2003-31650 Official Gazette discloses a construction that combines SOG with an oxide film formed by a conventional high density plasma CVD process. However, with a logic device that includes therein a complex pattern layout, the amount of the SOG film held in the device isolation trench varies inevitably depending on the location as noted before, and it is difficult to avoid the foregoing problem of change of film thickness on the semiconductor substrate.
When it is possible to form a buried oxide film for the device isolation insulator film by a high-density plasma CVD process in such a manner that the buried oxide film causes shrinkage when applied with a thermal annealing process, it would become possible to improve the operational speed of the semiconductor device while suppressing the variation of film thickness depending on the pattern density. Further, such a process would be advantageous for reducing the number of process steps and for improving the production yield of semiconductor devices.
Unfortunately, an oxide film formed by a conventional high-density plasma CVD process shows little film shrinkage even when a thermal annealing process is conducted at high temperature such as 900-1000° C.
In one aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of:
forming an isolation trench in a semiconductor substrate;
depositing a silicon oxide film over said semiconductor substrate by a high-density plasma CVD process such that said silicon oxide film fills said isolation trench and such that said silicon oxide film contains water with such an amount that there is caused a shrinkage in said silicon oxide film when a dehydration process is applied to said silicon oxide film;
causing a shrinkage in said silicon oxide film by dehydrating said silicon oxide film; and
removing said silicon oxide film deposited on said silicon substrate by a chemical mechanical polishing process.
In another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of:
forming an isolation trench in a substrate surface;
depositing a silicon oxide film over said semiconductor substrate surface at a temperature of 290° C. or less;
dehydrating said silicon oxide film; and
removing said silicon oxide film deposited on said silicon substrate by a chemical mechanical polishing process.
In another aspect of the present invention, there is provided a semiconductor device, comprising:
a semiconductor substrate;
an isolation trench formed in said semiconductor substrate so as to define a device region;
an insulator film filling said device isolation trench; and
an active device formed over said semiconductor substrate in said device region,
wherein said insulator film comprises lamination of plural oxide films formed parallel with each other.
According to the present invention, it becomes possible to fill a device isolation trench, when forming an STI device isolation structure, by a silicon oxide film that causes shrinkage upon dehydration process, while using a high-density plasma CVD process. Thus, by causing dehydration and shrinkage in such a silicon oxide film, it becomes possible to form a device isolation insulator film in the device isolation trench such that the device isolation insulator film accumulates therein a tensile stress.
With such a construction, a tensile stress acting in the gate width direction is applied to the channel region of the semiconductor device and the operational characteristics of the semiconductor device is improved.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.
In the investigation constituting the foundation of the present invention, the inventor of the present invention has discovered that it is possible to conduct deposition of a silicon oxide film by using a high-density plasma CVD method in such a manner that the film contains a large amount of silanol group (Si—OH bond). This means that such a silicon oxide film contains a large amount of water therein, and thus, it is possible to induce a large shrinkage in the film by causing discharge of the water with such a silicon oxide film.
More specifically, the inventor of the present invention has conducted a deposition experiment of silicon oxide film on a silicon substrate by using a commercially available high-density plasma CVD apparatus of induction-coupling type at the substrate temperature of 250° C. while supplying a silane (SiH4) gas, an oxygen gas and a hydrogen gas with respective flow rates of 40 sccm, 80 sccm and 480-2000 sccm. In the experiment, a high frequency power of 5000 W is supplied to a coil wound around a ceramic dome forming the processing vessel with a frequency of 400 kHz, and a high frequency power of 1200 W is supplied to a stage holding the substrate at the frequency of 13.56 MHz. Thereby, deposition of the silicon oxide film was conducted to the thickness of 450 nm.
Further, the inventor of the present invention has measured the variation of film thickness of the silicon oxide film thus formed by annealing in a nitrogen gas ambient at the temperature of 1000° C. for 30 minutes. Here, “shrinkage film” is defined as the film that showed shrinkage of 0.6% or more in view of the error (±0.3 μm) of the instrument used for measurement of the film thickness. In the foregoing experiment, the substrate temperature was controlled by holding the substrate to be processed on the stage by an electrostatic chuck and causing to flow a helium gas at the rear side of the stage.
Typically, a device isolation insulator film of STI structure has been formed in the conventional art, when using a high-density plasma CVD apparatus, by supplying a silane gas with the flow rate of 120 sccm, an oxygen gas with a flow rate of 160 sccm, and a hydrogen gas with a flow rate of 500 sccm, while supplying a high-frequency power of 2000 W to the coil wound around a processing vessel at the frequency of 400 kHz and further supplying a high-frequency power of 3000 W to the stage at the frequency of 13.56 MHz. Thereby, deposition has been made by setting the substrate temperature to about 650° C.
In this conventional art, the substrate is not fixed upon the stage by an electrostatic chuck and the substrate is heated to the foregoing temperature of about 650° C. as a result of exposure to the plasma.
As compared with the foregoing conventional condition, it will be noted that the proportion of the hydrogen gas in the source gas mixture is increased significantly and the substrate temperature is decreased significantly with the film formation condition of the present invention.
Referring to
Further,
The result of
Referring to
In the case the proportion of the hydrogen gas flow rate is increased beyond 0.8, on the other hand, the shrinkage rate of the film increases generally linearly, and it can be seen that a shrinkage rate of as large as 4.5% is attained when the proportion of the hydrogen gas flow rate is set to 0.95.
Further, as can be seen in
Historically, silicon oxide film formed by a high-density plasma CVD process has been used for burying Al interconnection patterns, and thus, a deposition temperature of 300-400° C. has been used in relation to the thermally resistant temperature of Al. From the result of
Thus, the present invention uses a silicon oxide film formed by a high-density plasma CVD process such that the silicon oxide film causes shrinkage upon thermal annealing process for the device isolation insulator film of the STI structure, in the prospect of reducing the compressive stress applied to the device region from the device isolation insulator film or converting the compressive stress to a tensile stress.
From the shrinkage rate, it is evaluated that the stress accumulated in the device isolation insulator film is a compressive stress having the magnitude of 300 MPa for the case of the conventional film where the shrinkage rate is 0%, while in the case of the film of the present invention that shows the shrinkage rate of 4.5%, it is evaluated that the foregoing compressive stress is changed to a tensile stress of the magnitude of 100 MPa. Detailed stress calculation for actual device structure will be presented later in relation to the next embodiment.
In the experiment of
Referring to
Next, the resist pattern 44 is removed in the step of
Here, it should be noted that this liner silicon nitride film 48 functions to prevent formation of silicon oxide film accumulating therein a compressive stress on the surface of the device isolation trench 46 at the time of filling the device isolation trench 46 with the device isolation insulator film in the later process. It should be noted that such unwanted silicon oxide film of compressive stress may be formed by the oxidation of wall surface of the device isolation trench by the water released from the device isolation insulator film or by the oxidation of the wall surface of the device isolation trench caused by the process conducted later in high temperature oxidation ambient.
Next, in the step of
In the step of
Next, in the step of
Next, in the step of
Further, with the step of
Here, it should be noted that the thermal annealing process of the oxide film 49b is not limited to the step of
The inventor of the present invention has evaluated the stress underneath the gate electrode for the substrate having the actual STI structure in which there is formed a gate electrode on the device region via the gate insulation film 51, for the case the device isolation insulator film 49 is formed by the conventional high-density plasma CVD process and for the case the device isolation insulator film 49 is formed by the high-density plasma CVD process of the present invention, by using a convergence electron beam diffraction method.
Referring to
From
On the silicon substrate formed with such an STI device isolation structure, it is possible to form a semiconductor device similar to the one shown in
As explained with reference to
When such a liner silicon nitride film 48 is provided, on the other hand, there is a tendency that cracking takes place at the interface between the liner silicon nitride film 48 and the silicon oxide film 49b when the silicon oxide film 49b is subjected to dehydration and shrinking process by way of thermal annealing process.
In order to avoid such cracking, the foregoing embodiment provided the buffer silicon oxide film 49a, formed by the high-density plasma CVD process of ordinary condition, between the liner nitride film 48 and the silicon oxide film 49b. Because the film 49a is formed by the ordinary high-density plasma CVD process, the silicon oxide film 49a accumulates therein a compressive stress.
The inventor of the present invention has discovered, in the investigation that constitutes the foundation of the present invention, that there are cases in which the liner silicon nitride film 48 and the buffer silicon oxide film 49a can be omitted and the silicon oxide film 49b can be formed directly on the liner silicon oxide film 47, by conducting the dehydration processing of the silicon oxide film 49b in plasma.
Referring to
With the present embodiment, the device isolation trench 46 is filled in the step of
Next, with the present embodiment, the structure of
For example, such a dehydration processing is conducted by supplying a He gas with the flow rate of 2000 sccm and driving the high frequency coil wound around a ceramic dome that constitutes the processing vessel of the high-density plasma CVD apparatus with a high frequency power of 7000 W at the frequency of 400 kHz. Thereby, the plasma exposure process is conducted for 120 seconds.
During this process, the substrate is not fixed upon the stage of the substrate processing apparatus by an electrostatic chuck, or the like, and thus, there occurs an increase of substrate temperature to about 550° C.
As a result of the plasma anneal processing conducted at such a relatively low temperature, the OH group or silanol group forming water in the silicon oxide film 49b is released to outside of the film, and the silicon oxide film 49b undergoes shrinking.
Referring to
In the case dehydration and shrinking of the silicon oxide film 49b is thus conducted at low temperature, it was observed that there occurs no cracking at the interface between the liner silicon oxide film 47 and the silicon oxide film 49b or at the interface between the liner silicon oxide film 47 and the sidewall surface of the device isolation trench 46, while this indicates that excellent adherence is realized at these interfaces.
Further, it should be noted that the plasma anneal processing of the silicon oxide film 49b, formed by the high-density plasma CVD process in such a manner to contain OH group or silanol group with large amount, provides a beneficial side effect of suppressing re-oxidation of the surface of the silicon substrate 41 exposed at the device isolation trench 46 at the time of conducting a high temperature thermal annealing process during the process of forming a semiconductor device on the device region defined by the device isolation structure thus formed.
Next, in the step of
Further, in the step of
In the present embodiment, it should be noted that the plasma anneal processing that causes shrinking in the silicon oxide film 49b is not limited to the step of
In the case such a plasma anneal processing is conducted after the CMP process, in the step of
For example, a silicon oxide film formed by a conventional high-density plasma CVD process at the temperature of 650° C. has an etching rate, with regard to an etchant of 1% HF, of 1.4 times as large as the etching rate for the case of etching a thermal oxide film by the same etchant, when a thermal annealing process is applied in a nitrogen gas ambient at 900° C. for 30 seconds after the CMP process.
On the other hand, in the case a silicon oxide film is formed by a high-density plasma CVD process under the deposition condition of the present invention at the temperature of 250° C., for example, the silicon oxide film has an etching rate of 1.6 times as large as the etching rate of thermal oxide film, when etched by an etchant of 1% HF.
Now, when a plasma anneal processing is applied to such a silicon oxide film at the temperature of about 550° C. for 120 seconds in an induction coupled plasma processing apparatus having a dome-shaped ceramic processing vessel by supplying a He gas with the flow rate of 2000 sccm and by feeding a high frequency power of 7000 W to the coil would around the processing vessel at the frequency of 13.56 MHz, it was confirmed that the etching rate of the silicon oxide film by the etchant of 1% HF becomes 1.4 times as large as the etching rate for the case of etching a thermal oxide film by the same etchant.
Thus, it was confirmed that the etching durability of the film is improved for the silicon oxide film of the present invention to the degree comparable with the silicon oxide film formed by the conventional high-density plasma CVD process of 650° C. and annealed subsequently at 900° C.
Referring to
Further, low-resistance silicide layers 54S, 54D and 54G of NiSi, CoSi2, or the like, are formed on respective surfaces of the diffusion regions 41a, 41b and the gate electrode 53G.
On the silicon substrate 41, there is formed a stressor film 55 of silicon nitride such that the stressor film 55 covers continuously the silicide layers 51S and 51D and the gate electrode 53G including the sidewall insulation films 53A and 53B. In the case the semiconductor device 40 is an n-channel MOS transistor and the diffusion regions 41a and 41b and the gate electrode 53G are all doped to n-type, the stressor film 55 accumulates a tensile stress, and a compressive stress is applied to the channel region right underneath the gate electrode 53G in the direction perpendicular to the substrate surface.
On the other hand, in the case the semiconductor device 40 is a p-channel MOS transistor and the diffusion regions 41a and 41b and the gate electrode 53G are doped to p-type, the stressor film 55 accumulates a compressive stress, and thus, a tensile stress acting perpendicular to the substrate surface is applied to the channel region right underneath the gate electrode 53G.
On the silicon nitride film 55, there is deposited an interlayer insulation film 56 of silicon oxide, or the like, and contact plugs 57A and 57B of tungsten, or the like, are formed in the interlayer insulation film 56 respectively in contact with the silicide regions 54A and 54D.
In
Referring to
ΔIon
while in the case the MOS transistor is a p-channel MOS transistor, the change of On-current is given as
ΔIon
wherein εxx represents the strain component in the gate length direction (L-direction), εyy represents the strain component in the depth direction (D-direction), and εzz represents the strain component in the gate width direction (W-direction).
In any of the p-channel and n-channel MOS transistors, contribution of the first two terms is trifle with regard to the change of the On-current, while the contribution of the third term is material and predominant.
With the cross-section of
On the other hand, in the region right underneath the gate electrode 53G, the device isolation insulator film 49 is protected by the gate electrode 53G and there occurs no subsiding. Thus, in the cross-section of
In the preceding embodiments, explanation has been made for the case the device isolation trench 46 has a width of 140 nm and a depth of 350 nm, while there exists a demand of reducing the width of the device isolation trench 46 to 110 nm or less in relation to the miniaturization of semiconductor device.
However, when the width of the device isolation trench is reduced and the aspect ratio is increased, it becomes difficult to fill the device isolation trench by a high-density plasma CVD process of low temperature of typically of 280° C. or less used with the present invention, and there arises a substantial risk that defects or voids are formed in the device isolation insulator film 49.
It should be noted that this difficulty arises because it becomes difficult for the active species of the source material that cause the CVD reaction to reach the inner part of the device isolation trench 46 of large aspect ratio and because it becomes difficult to cause deposition of the silicon oxide film 49b consecutively from the bottom of the trench due to the low substrate temperature and hence deteriorated reactivity of the active species. When such defects or voids are formed in the device isolation insulator film 49, there arise problems such as disconnection of the interconnection pattern formed on the device isolation insulator film 49, while this leas to the problem of degradation of production yield of the semiconductor device.
Thus, with the present embodiment, formation of the silicon oxide film 49b of
In one example, the deposition process of the silicon oxide film 49b is conducted by using an induction coupled high-density plasma CVD apparatus in plural steps with the film thickness of 50 nm in each step while conducting an intervening the plasma etching process of
The plasma etching process is conducted in the same processing vessel by supplying an NF3 gas, a He gas and a hydrogen gas with respective flow rates of 150 sccm, 100 sccm and 500 sccm and energizing the high frequency coil would around the processing vessel with the high frequency power of 3500 W at the frequency of 400 kHz and at the same time supplying a high frequency power of 1200 W to the stage holding the substrate at the frequency of 13.56 MHz.
With this plasma etching process, the silicon oxide film 49b thus deposited is etched by the thickness of about 10 nm in each of the foregoing plural steps. Thereby, it is preferable to conduct the deposition process and the etching process at the same substrate temperature with the present embodiment, and thus, the difference of substrate temperature between the deposition mode and the etching mode is maintained within 100° C.
In the case there appears a temperature difference exceeding 100° C. between the deposition process and the etching process, it is also possible to use a cluster-type substrate processing apparatus such that the substrate deposited with the silicon oxide film is cooled in a cooling chamber or a substrate transfer chamber and introduce to the etching chamber thereafter.
Referring to
It should be noted that such a lamination structure of the device isolation insulator film 49 corresponds to the density difference existing in the device isolation insulator film 49 and can be confirmed by observation of the device cross-section by a transmission electron microscope.
With such a construction, it becomes possible to fill the device isolation trench with the device isolation insulator film by using the high-density plasma CVD process of the present invention conducted at low temperature, even when the device isolation trench is the one having a large aspect ratio.
It should be noted that such a step-by-step formation of the device isolation insulator film 49 is not limited to the process recipe explained previously with reference to
Further, with the example of
While the present invention has been explained heretofore for the case of using an induction-coupled high-density plasma processing apparatus for the high-density plasma CVD apparatus, it will be understood from the principle of the present invention that the present invention is not limited by the specific type of the high-density plasma processing apparatus. Thus, it is also possible to use an ECR plasma processing apparatus or a high-density plasma processing apparatus that uses a helicon wave.
Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.
Number | Date | Country | Kind |
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2006-031317 | Feb 2006 | JP | national |