Claims
- 1. A read-biasing circuit for sensing the binary state of a floating-gate memory device and having an input line and an output line, comprising:
a quick-charging circuit operatively coupled to the input line and the output line which quickly raises the potential of the input line to a predetermined first voltage if the device is in one binary state and to a predetermined second voltage if the device is in its other binary state and the potential of the output line to a predetermined third voltage if the device is in one binary state and to a predetermined fourth voltage if the device is in its other binary state; and a feedback circuit operatively coupled to the input line which prevents the potential of the input line from considerably exceeding a predetermined overshoot voltage.
- 2. The read-biasing circuit of claim 1, further comprising a loading circuit operatively coupled to the input line which provides a predetermined load voltage to the input line.
- 3. The read-biasing circuit of claim 1, further comprising an enable circuit having an enable line and operatively coupled to the feedback circuit which prevents the read-biasing circuit from sensing the binary state of a floating-gate memory device unless the potential of the enable line substantially equals a predetermined enable voltage.
- 4. The read-biasing circuit of claim 1, wherein the quick-charging circuit comprises a p-channel MOSFET transistor.
- 5. The read-biasing circuit of claim 1, wherein the quick-charging circuit comprises an n-channel MOSFET transistor.
- 6. The read-biasing circuit of claim 1, wherein the feedback circuit comprises a p-channel MOSFET transistor, a first n-channel MOSFET transistor, and a second n-channel MOSFET transistor.
- 7. The read-biasing circuit of claim 2, wherein the loading circuit comprises a p-channel MOSFET transistor.
- 8. A high-speed sensor for sensing the binary state of a floating-gate memory device, comprising:
a differential amplifying circuit having a first input line, a second input line, and an output line which amplifies the difference between a potential at the first input line and a potential at the second input line; a memory array which stores a plurality of binary states and having a column line; a quick-discharge circuit operatively coupled to the column line of said memory array which quickly discharges the column line to a predetermined voltage; a read-biasing circuit having an input line and an output line, the output line operatively coupled to the first input line of said differential amplifying circuit and the input line operatively coupled to the column line of said memory array which quickly senses the potential at the column line after discharge; and a sense-reference circuit operatively coupled to the second input line of said differential amplifying circuit which provides a predetermined sense-reference potential.
- 9. The high-speed sensor of claim 8, wherein the memory array comprises a plurality of floating-gate memory devices ordered in columns and rows and selectively coupled to the column line.
- 10. The high-speed sensor of claim 8, wherein the quick-discharge circuit comprises a transistor with a drain operatively coupled to the column line of said memory array, a source operatively coupled to ground, and a gate operatively coupled to an external clock signal.
- 11. The high-speed sensor of claim 8, wherein the read-biasing circuit further comprises:
a quick-charging circuit operatively coupled to the input line and the output line which quickly raises the potential of the input line to a predetermined first voltage if the device is in one binary state and to a predetermined second voltage if the device is in its other binary state and the potential of the output line to a predetermined third voltage if the device is in one binary state and to a predetermined fourth voltage if the device is in its other binary state; and a feedback circuit operatively coupled to the input line which prevents the potential of the input line from considerably exceeding a predetermined overshoot voltage.
- 12. The high-speed sensor of claim 8, wherein the sense-reference circuit comprises:
a quick-charging circuit operatively coupled to the input line and the output line which quickly raises the potential of the input line to a predetermined first sense-reference voltage and the potential of the output line to a predetermined second sense-reference voltage; a feedback circuit operatively coupled to the input line which prevents the potential of the input line from considerably exceeding a predetermined overshoot voltage; a quick-charging transistor operatively coupled to the second input line of said differential amplifying circuit; and a reference memory device storing the sense-reference potential and operatively coupled to the second input line of said differential amplifying circuit.
- 13. A method for sensing the binary state of a floating-gate memory device, comprising the steps of:
discharging the device to a predetermined voltage; sensing the potential at the device after discharge; amplifying the sensed potential at the device; comparing the sensed potential at the device with an amplified predetermined sense-reference potential; and amplifying the difference between the sensed potential at the device and the amplified predetermined sense-reference potential.
- 14. A computer, comprising:
a microprocessor; a timing unit; an I/O interface module; a volatile memory array; a non-volatile memory array comprised of a plurality of selectively ordered floating gate memory devices and having an input line and an output line; a quick-charging circuit operatively coupled to the input line and the output line which quickly raises the potential of the input line to a predetermined first voltage if the device is in one binary state and to a predetermined second voltage if the device is in its other binary state and the potential of the output line to a predetermined third voltage if the device is in one binary state and to a predetermined fourth voltage if the device is in its other binary state; and a feedback circuit operatively coupled to the input line which prevents the potential of the input line from considerably exceeding a predetermined overshoot voltage.
- 15. A read-biasing and amplifying circuit, comprising:
an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output;
wherein the second load comprises a fourth control device; wherein the node of the second load is a signal input of the fourth control device; and wherein the first load is a fifth control device, a control input of the fourth control device is coupled to a control input of the fifth control device, and a control input of the third control device is coupled to the output.
- 16. A read-biasing and amplifying circuit, comprising:
an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output;
wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to the output, and a the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 17. A read-biasing and amplifying circuit, comprising:
an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output;
wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to a controlled signal output of the third control device, and the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 18. A circuit, including:
an input; an output; quick-charging means for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised; a load for a memory device being sensed, and a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
- 19. The circuit of claim 18, wherein the input is adapted to be operatively coupled to the bit line.
- 20. The circuit of claim 18, wherein the output is adapted to be operatively coupled to a microprocessor.
- 21. The circuit of claim 18, wherein the quick-charging means is operatively coupled to the input and the output.
- 22. The circuit of claim 18, wherein the load is distinct from the quick-charging means.
- 23. The circuit of claim 22, wherein the load is a resistive load.
- 24. The circuit of claim 23, wherein the resistive load is a p-channel MOSFET.
- 25. The circuit of claim 18, wherein the feedback means is operatively coupled to the input.
- 26. The circuit of claim 25, wherein the feedback means includes a p-channel MOSFET operatively coupled to a first n-channel MOSFET, and a second n-channel MOSFET operatively coupled to the first n-channel MOSFET.
- 27. The circuit of claim 25, wherein the feedback means includes an n-channel MOSFET operatively coupled to a first p-channel MOSFET, and a second p-channel MOSFET operatively coupled to the first p-channel MOSFET.
- 28. A circuit, including:
an input; an output; quick-charging means for simultaneously raising potentials of a bit line and the output; a load for a memory device being sensed, and a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
- 29. The circuit of claim 28, wherein the quick-charging means includes means for continuing to raise the potential of the output when the potential of the bit line is no longer being raised.
- 30. The circuit of claim 28, wherein the load is distinct from the quick-charging device.
- 31. The circuit of claim 30, wherein the load is a resistive load.
- 32. The circuit of claim 31, wherein the resistive load is a p-channel MOSFET.
- 33. The circuit of claim 28, wherein the feedback means is operatively coupled to the input.
- 34. The circuit of claim 33, wherein the feedback means includes a p-channel MOSFET operatively coupled to a first n-channel MOSFET, and a second n-channel MOSFET operatively coupled to the first n-channel MOSFET.
- 35. The circuit of claim 33, wherein the feedback means includes an n-channel MOSFET operatively coupled to a first p-channel MOSFET, and a second p-channel MOSFET operatively coupled to the first p-channel MOSFET.
- 36. A circuit, comprising:
an input; an output; a first transistor including a source and a well both connected to a first voltage, the first transistor including a gate and a drain; a second transistor including a source and a well both connected to the first voltage, the second transistor including a gate and a drain, wherein the second transistor gate is connected to the first transistor gate and a second voltage; a third transistor including a source and a well both connected to the first voltage, the third transistor including a gate and a drain both connected to the output; a fourth transistor including a source connected to the second voltage, a gate connected to the input, and a drain connected the first transistor drain; and a fifth transistor including a source connected to the input, a gate connected to the fourth transistor drain, and a drain connected to the output.
- 37. The circuit of claim 36, wherein at least one of the first transistor, second transistor, and third transistor is a p-channel transistor.
- 38. The circuit of claim 36 wherein at least one of the third transistor and fourth transistor is an n-channel transistor.
- 39. The circuit of claim 36, wherein the first, second, and third transistors are p-channel transistors, and the fourth and fifth transistors are n-channel transistors.
- 40. The circuit of claim 36, wherein the first voltage is Vcc.
- 41. The circuit of claim 36, wherein the second voltage is Vss.
- 42. The circuit of claim 36, wherein the third transistor is a quick-charging device adapted to operate in a saturated region for quick charging of a bit line and adapted to be in an off state during sensing of a bit line.
- 43. The circuit of claim 36, wherein the second transistor, during a sensing operation, operates in a linear region and provides current and acts as a load.
- 44. The circuit of claim 36, wherein the first transistor, fourth transistor, and third transistor operate as a feedback circuit during a sensing operation.
- 45. A circuit, comprising:
an input; an output; a first transistor including a source and a well both connected to a first voltage, the first transistor including a gate and a drain; a second transistor including a source and a well both connected to the first voltage, the second transistor including a gate and a drain, wherein the second transistor gate is connected to the first transistor gate and a second voltage; and a feedback biasing circuit, wherein the feedback biasing circuit consists of:
a third transistor including a source and a well both connected to the first voltage, the third transistor including a gate and a drain both connected to the output; a fourth transistor including a source connected to the second voltage, a gate connected to the input, and a drain connected the first transistor drain; and a fifth transistor including a source connected to the input, a gate connected to the fourth transistor drain, and a drain connected to the output.
- 46. The circuit of claim 45, wherein at least one of the first transistor, second transistor, and third transistor is a p-channel transistor.
- 47. The circuit of claim 45, wherein at least one of the third transistor and fourth transistor is an n-channel transistor.
- 48. The circuit of claim 45, wherein the first, second, and third transistors are p-channel transistors, and the fourth and fifth transistors are n-channel transistors.
- 49. The circuit of claim 45, wherein the first voltage is Vcc.
- 50. The circuit of claim 45, wherein the second voltage is Vss.
- 51. The circuit of claim 45, wherein the third transistor is a quick-charging device adapted to operate in a saturated region for quick charging of a bit line and adapted to be in an off state during sensing of a bit line.
- 52. The circuit of claim 45, wherein the second transistor, during a sensing operation, operates in a linear region and provides current and acts as a load.
- 53. A read-biasing and amplifying system, comprising:
a first read-biasing and amplifying circuit; a second read-biasing and amplifying circuit; and a differential amplifier connected between the first circuit and the second circuit.
- 54. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output;
wherein the second load comprises a fourth control device; wherein the node of the second load is a signal input of the fourth control device; and wherein the first load is a fifth control device, a control input of the fourth control device is coupled to a control input of the fifth control device, and a control input of the third control device is coupled to the output.
- 55. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output;
wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to the output, and a the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 56. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output; wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to a controlled signal output of the third control device, and the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 57. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; a first transistor including a source and a well both connected to a first voltage, the first transistor including a gate and a drain; a second transistor including a source and a well both connected to the first voltage, the second transistor including a gate and a drain, wherein the second transistor gate is connected to the first transistor gate and a second voltage; a third transistor including a source and a well both connected to the first voltage, the third transistor including a gate and a drain both connected to the output; a fourth transistor including a source connected to the second voltage, a gate connected to the input, and a drain connected the first transistor drain; and a fifth transistor including a source connected to the input, a gate connected to the fourth transistor drain, and a drain connected to the output.
- 58. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; a first transistor including a source and a well both connected to a first voltage, the first transistor including a gate and a drain; a second transistor including a source and a well both connected to the first voltage, the second transistor including a gate and a drain, wherein the second transistor gate is connected to the first transistor gate and a second voltage; and a feedback biasing circuit, wherein the feedback biasing circuit consists of:
a third transistor including a source and a well both connected to the first voltage, the third transistor including a gate and a drain both connected to the output; a fourth transistor including a source connected to the second voltage, a gate connected to the input, and a drain connected the first transistor drain; and a fifth transistor including a source connected to the input, a gate connected to the fourth transistor drain, and a drain connected to the output.
- 59. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; quick-charging means for simultaneously raising potentials of a bit line and the output; a load for a memory device being sensed, and a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
- 60. The system of claim 53, wherein at least one of the first circuit and the second circuit include:
an input; an output; quick-charging means for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised; a load for a memory device being sensed, and a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
- 61. A circuit, including:
a bit line input; an output; quick-charging means for raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised; a load for a memory device being sensed, and a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
- 62. A circuit, including:
an input; an output; quick-charging means, operatively coupled to the input and the output, for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised; a resistive load for a memory device being sensed, wherein the load is distinct from the quick-charging means; and a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
- 63. The circuit of claim 61, wherein the resistive load is a p-channel MOSFET.
- 64. A circuit, including:
an input adapted to be operatively coupled to the bit line; an output adapted to be operatively coupled to a microprocessor; quick-charging means, operatively coupled to the input and the output, for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised; a resistive load for a memory device being sensed, wherein the load is distinct from the quick-charging means; and a feedback means, operatively coupled to the input, for preventing the potential of the bit line from exceeding a read-bias potential, wherein the feedback means includes a p-channel MOSFET operatively coupled to a first n-channel MOSFET, and a second n-channel MOSFET operatively coupled to the first n-channel MOSFET.
- 65. The circuit of claim 64, wherein the resistive load is a p-channel MOSFET.
RELATED APPLICATIONS
[0001] This application is a Divisional of U.S. patent application Ser. No. 09/642,953, filed Aug. 21, 2000, which is a Divisional of U.S. patent application Ser. No. 09/136,909, filed Aug. 20, 1998, now issued as U.S. Pat. No. 6,108,237, which is a Continuation of U.S. patent application Ser. No. 08/895,618, filed Jul. 17, 1997, now issued as U.S. Pat. No. 5,835,411, which is a Continuation of U.S. patent application Ser. No. 08/804,951, filed Feb. 24, 1997, now issued as U.S. Pat. No. 5,862,077. All of these applications are incorporated herein by reference.
Divisions (2)
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Number |
Date |
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Parent |
09642953 |
Aug 2000 |
US |
Child |
10352419 |
Jan 2003 |
US |
Parent |
09136909 |
Aug 1998 |
US |
Child |
09642953 |
Aug 2000 |
US |
Continuations (2)
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Number |
Date |
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Parent |
08895618 |
Jul 1997 |
US |
Child |
09136909 |
Aug 1998 |
US |
Parent |
08804951 |
Feb 1997 |
US |
Child |
08895618 |
Jul 1997 |
US |