Claims
- 1. A read-biasing and amplifying circuit, comprising:an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output; wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to the output, and a controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 2. A read-biasing and amplifying circuit, comprising:an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output; wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to a controlled signal output of the third control device, and the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 3. The circuit of claim 1, wherein the input is connected to a bit line.
- 4. The circuit of claim 1, wherein the output is adapted to be operably connected to a microprocessor.
- 5. The circuit of claim 1, wherein the input is connected to a bit line, and wherein the output is adapted to be operably connected to a microprocessor.
- 6. The circuit of claim 1, wherein at least one of the third, fourth and sixth control devices is a p-channel transistor.
- 7. The circuit of claim 1, wherein each of the third, fourth and sixth control devices is a p-channel transistor.
- 8. A read-biasing and amplifying circuit, comprising:an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output; wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to both a control input of the sixth control device and a voltage Vss, a control input of the third control device is coupled to the output, and a controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 9. A read-biasing and amplifying circuit, comprising:an input; an output; a first load having a node connected to the output; a second load having a node, wherein the node of the second load is coupled to the output; a quick-charging transistor with its control input and signal input connected to the output; and a feedback biasing circuit connected to the input; wherein the feed back biasing circuit includes:a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; wherein the first load is a fifth control device, the control input of the third control device is coupled to a control input of the fifth control device, and a controlled signal output of the third control device is coupled to the controlled signal output of the first control device.
- 10. The circuit of claim 9, wherein the second load comprises a fifth control device, and wherein the node of the second load is a signal input of the fifth control device.
- 11. The circuit of claim 9, wherein the input is connected to a bit line.
- 12. The circuit of claim 9, wherein the output is adapted to be operably connected to a microprocessor.
- 13. The circuit of claim 9, wherein the input is connected to a bit line, and wherein the output is adapted to be operably connected to a microprocessor.
- 14. The circuit of claim 9, wherein the fast-acting transistor is a p-channel transistor.
- 15. The circuit of claim 9, wherein the first load is a p-channel transistor.
- 16. The circuit of claim 9, wherein the first control device and the second control device are both n-channel transistors.
- 17. A read-biasing and amplifying circuit, comprising:an input; an output; a first load having a node connected to the output; a second load having a node, wherein the node of the second load is coupled to the output; a quick-charging transistor with its control input and signal input connected to the output; and a feedback biasing circuit connected to the input; wherein the feed back biasing circuit consists essentially of:a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a third control device including a control input and a controlled signal output; and wherein the first load is a fifth control device, the control input of the third control device is coupled to a control input of the fifth control device, and a controlled signal output of the third control device is coupled to the controlled signal output of the first control device.
- 18. The circuit of claim 17, wherein the second load comprises a fifth control device, and wherein the node of the second load is a signal input of the fifth control device.
- 19. The circuit of claim 17, wherein the input is connected to a bit line.
- 20. The circuit of claim 17, wherein the output is adapted to be operably connected to a microprocessor.
- 21. The circuit of claim 17, wherein the input is connected to a bit line, and wherein the output is adapted to be operably connected to a microprocessor.
- 22. The circuit of claim 17, wherein the fast-acting transistor is a p-channel transistor.
- 23. The circuit of claim 17, wherein the first load is a p-channel transistor.
- 24. The circuit of claim 17, wherein the first control device and the second control device are both n-channel transistors.
- 25. A computer, comprising:a microprocessor; a mother board operably connected to the microprocessor; and a memory operably connected to the mother board; wherein the memory includes a read-biasing and amplifying circuit including: an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output; wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to the output, and a controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
- 26. A computer, comprising:a microprocessor; a mother board operably connected to the microprocessor; and a memory operably connected to the mother board; wherein the memory includes a read-biasing and amplifying circuit including: an input; an output; a first load having a node; a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load; a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output; a second load having a node, wherein the node of the second load is coupled to the output; a third control device having a signal input, wherein the signal input of the third control device is coupled to the output; a fourth control device including a control input and a controlled signal output; wherein the second load comprises a fifth control device; wherein the node of the second load is a signal input of the fifth control device; and wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to a controlled signal output of the third control device, and the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
Parent Case Info
This application is a Division of U.S. patent application Ser. No. 09/136,909, filed Aug. 20, 1998 U.S. Pat. No. 6,108,237, which is a Continuation of U.S. patent application Ser No. 08/895,618, filed Jul. 17, 1997, now issued as U.S. Pat. No. 5,835,411.
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Continuations (1)
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Number |
Date |
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Parent |
08/895618 |
Jul 1997 |
US |
Child |
09/136909 |
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US |