Claims
- 1. A one bit memory cell comprising a ferroelectric capacitor and an isolation transistor, said ferroelectric capacitor comprising:
- a bottom electrode;
- a dielectric layer comprising a ferroelectric material having a Curie Point less than 400.degree. C.;
- a top electrode, wherein said top and bottom electrodes sandwich said dielectric layer; and
- an oxygen barrier comprising an oxygen impermeable material, said oxygen barrier surrounding said dielectric layer such that said oxygen layer prevents oxygen from leaving or entering said dielectric layer; and
- said isolation transistor comprising an FET having a gate, source and drain, said drain being connected to said bottom electrode via a layer of titanium or titanium nitride.
Parent Case Info
This application is a continuation of application Ser. No. 08/661,597 filed Jun. 11, 1996, now U.S. Pat. No. 5,679,969.
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Continuations (1)
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Number |
Date |
Country |
Parent |
661597 |
Jun 1996 |
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