Patent Application
20220140146
This disclosure describes ferroelectric devices that include interface switching modulation (ISM) layers that enhance the operation of the devices. Specifically, ferroelectric transistors and tunnel junction devices include ISM layers such that material dipoles reinforce internal electric fields.
Many different types of transistors may be used to implement the basic components of neural networks and other modern systems. However, a specific family of devices known as ferroelectric devices have not been put into widespread use. A ferroelectric device is a logic/memory device that can maintain its logical/memory state even when power is removed. Ferroelectric devices may be similar to traditional metal oxide silicon (MOS) devices, except that the some of the dielectric material may be replaced with a ferroelectric material. The ferroelectric material may act like a dielectric that “remembers” or stores electric fields to which it has been exposed. In a ferroelectric device, a persistent dipole (or so-called “domain”) may be formed within the gate dielectric itself, thereby splitting the threshold voltage of the FeFET into stable states that can represent logic states. Because these stable states are persistent, the operation of a device may store state information as is done in a traditional charge-based Flash memory cell. Ferroelectric devices may also use a relatively small amount of power and may be scalable alongside traditional CMOS technologies. The read/write time is faster and the write/erase voltage is lower for ferroelectric devices than for traditional memories such as Flash NAND memory.
In some embodiments, a ferroelectric field-effect transistor that is enhanced by interface switching modulation may include a gate electrode, a silicon channel between a source and a drain of the transistor, a ferroelectric layer located between the gate electrode and the silicon channel; and one or more interface switching modulation (ISM) layers located between the gate electrode and the silicon channel. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide.
In any embodiments, any or all of the following features may be implemented in any combination and without limitation. The one or more ISM layers may be located between the gate electrode and the ferroelectric layer. The transistor may include second one or more ISM layers located between the ferroelectric layer and the silicon channel. The layer of hafnium oxide and the layer of silicon oxide in each of the one or more ISM layers may be approximately 2 nm thick. A work function of the gate electrode and a doping of the silicon channel may be designed to generate a predefined on-voltage in the transistor. The transistor may be one of a plurality of transistors forming connections in a neural network, where the transistor may include connections with other neural network nodes. The ferroelectric layer may include a plurality of ferroelectric dipoles with polarities that are controlled by a gate voltage, and each of the one or more ISM layers may include material dipoles with polarities that are controlled by the gate voltage.
In some embodiments, a ferroelectric tunnel junction device that is enhanced by interface switching modulation may include a first electrode, a second electrode, a ferroelectric layer located between the first electrode and the second electrode, and one or more interface switching modulation (ISM) layers located between the first electrode and the second electrode. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide.
In any embodiments, any or all of the following features may be implemented in any combination and without limitation. The ferroelectric layer may be approximately 10 nm thick. The ferroelectric layer may be located between the first electrode and the one or more ISM layers. The one or more ISM layers may be located between the ferroelectric layer and the second electrode. The one or more ISM layers may include a plurality of ISM layers. The one or more ISM layers include three ISM layers. The device may also include connections to a neural network. The ferroelectric layer may include a plurality of ferroelectric dipoles with polarities that are controlled by a voltage applied across the first electrode and the second electrode, and each of the one or more ISM layers may include material dipoles with polarities that are controlled by the voltage applied across the first electrode and the second electrode.
In some embodiments, a method of fabricating a ferroelectric device that is enhanced by interface switching modulation may include depositing a first electrode, depositing a second electrode, depositing a ferroelectric layer located between the first electrode and the second electrode, and depositing one or more interface switching modulation (ISM) layers located between the first electrode and the second electrode. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide.
In any embodiments, any or all of the following features may be implemented in any combination and without limitation. The first electrode may include a gate electrode of a ferroelectric transistor. The first electrode may include an electrode of a ferroelectric tunnel-junction device. The monolayer of titanium oxide may be deposited using a deposition process such that the monolayer of titanium oxide may include titanium ions that have not formed a crystal lattice. The layer of hafnium oxide and the layer of silicon oxide may generate oxygen ions in the one or more ISM layers, and the layer of titanium oxide may generate titanium ions in the one or more ISM layers, such that the oxygen ions and the titanium ions may form material dipoles in response to an applied voltage.
A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings, wherein like reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an
Solid-state drives (SSDs) repressing the majority of modern memory devices and may rely on Flash memory technology for their implementations. For example, SSDs may use three-dimensional (3-D) charge-trapping and floating gate NAND technologies. Flash was chosen because of its reliability and its ability to store multiple memory states instead of classical binary 0 and binary 1 states found in 1-bit memories. Multiple memory states has been enabled by the very wide memory window of Flash memory which enables multiple memory states to be “squeezed” into the memory window beyond the traditional binary 0 and 1 states of the 1-bit solutions. Memory technologies that can represent multiple bits of information in a single memory cell are becoming more important in emerging technologies, as they not only increase the storage density, but also reduce the fabrication cost per bit of the memory.
Despite the advantages of using Flash memory described above, certain technical problems still exist as modern use cases shift to lower-power and faster designs with higher array periphery area-efficiency requirements. Flash memory requires a relatively high voltage of approximately 25 V to program a single bit in the memory cell. Additionally, Flash memory uses relatively long voltage pulses during a programming operation. These pulses may last between 100 μs and a few milliseconds. While these voltage ranges and pulse lengths may be acceptable for long-term storage devices, they are acceptable for many modern memory applications that require fast, low-power memories. Additionally, additionally circuitry is usually required to provide 25 V signals for the program and erase voltages. For example, charge pumps are required to increase the biasing voltage level up to 25 V. These charge pumps consume area in the cell and result in a lower die utilization as the ratio of memory array to periphery circuits drops. This in turn increases the cost per bit to manufacture the memory array.
To solve the technical problems associated with the speed and voltage requirements presented by Flash memories, the embodiments described herein may use ferroelectric memory elements to implement relatively low-power, high-speed memory devices. The ferroelectric memory elements described herein may use as little as 2 V-4 V when programming individual bits, and the programming pulse lengths may be on the order of approximately 10 ns. Because the ferroelectric dipoles can switch so rapidly and readily using these fast low-voltage pulses, ferroelectric memory elements may be better suited for low-power, high-speed memory applications, such as neural networks and in-memory computing.
One existing problem that has previously prevented the widespread use of ferroelectric materials involves the width of the “memory window” that allows for multiple bit states to be saved in a single memory element. In case of the one-transistor, one-capacitor (1T-1C) realization of ferroelectric memory (i.e. an FRAM), the memory window may refer to a width of a hysteresis loop in the applied polarization/voltage curves associated with a memory element. The higher the polarization, the greater the ability to store additional polarization states that can be discreetly represented in the memory without significant overlap. In contrast to the 1T-1C realization, a single-transistor (1T) ferroelectric memory provides a memory window proportional to the thickness of ferroelectric material and the coercive field. The coercive field refers to the internal barrier that needs to be overcome to flip the state of the memory from one state to other (e.g. from a programmed state to an erased state). In a partial switching implementation, the memory window of a ferroelectric field effect transistor (FeFET) is proportional to the number of domains that are switched, which in turn alters the transistor's channel conductivity. For example, multiple voltage thresholds or multiple current states may be realized within a large memory window by applying pulses with either different voltage amplitudes or different pulse length s to the device. These applied voltages may result in intermediate states (i.e., partial switching of the dipoles) in the ferroelectric material. When the state of the ferroelectric device is read, the intermediate state may cause an intermediate voltage or current output that can be decoded as an intermediate state between a fully programmed and a fully erased state.
In
In this example, a negative voltage may be applied to the top of the gate in state 202. This negative voltage may cause dipoles in the ferroelectric material to be oriented with a positive polarity on top towards the top of the gate and a negative polarity on the bottom towards the silicon channel. This induces a positive charge accumulation (e.g., holes) in the p-type semiconductor, which is a Si channel in this example. This may be described as a reset or erase operation. In order to overcome the positive charge in the channel, a relatively high voltage may be applied to the gate to read the value of the memory element as illustrated in graph 210. When increasingly negative voltage pulses are applied to the gate of the device, the dipoles in the ferroelectric material may begin to switch and gradually transition the direction of those dipoles such that the negative polarity is oriented towards the top of the gate and the positive polarity is oriented towards the silicon channel. This induces an increasingly negative polarity in the channel by attracting minority carriers, which in a p-type Si-channel are electrons. This transition may be gradual, switching a few regions at a time in the ferroelectric material to progress through states 204, 206, and 208. As illustrated in graphs 212, 214, and 216, the voltage required to read the memory device as the ferroelectric material switches gradually becomes lower. This difference between VTH_high and VTH_low may represent the memory window of the device for a single bit cell where all 4 threshold states can implement a 2-bit memory device or 2-bit “digital” synapse.
For example, to model synaptic, analog behavior, a FeFET may be designed to have a comparatively larger area than the similar abovementioned “digital” synaptic devices, such that the gate electrode can be represented as a large plurality of domains, or physical regions that can independently switch in the gate electrode between logic states. Each of these domains is represented in
Beginning with the FeFET state 202 at the top of
This gradual transition of domains within the FeFET with a plurality of domains may provide the analog-like transition between states that is useful in modeling synaptic behavior. Before receiving any input pulses, state 202 represents a full logic 00 state for the FeFET. Conversely, after receiving a sufficient number of input pulses (e.g., at least three pulses), state 208 represents a full logic 11 state for the FeFET. As each of the domains switch independently, the conductivity of the channel in the FeFET may gradually change between a nonconductive state and a fully conductive state in a corresponding manner. This change in conductivity may cause the output of the synapse to also gradually increase/decrease as positive/negative input pulses are received to switch the corresponding domains.
In addition to representing neurons and synapses in an artificial neural network, the FeFET illustrated in
In addition to the ferroelectric dipoles, the ferroelectric device may also be affected by trapped charges within the device. Referred to as “charge trapping,” electrons trapped within the device's dielectric cause a shift of the threshold voltage of device toward more positive gate voltages. However, instead of traveling in a counterclockwise direction 302, the effect of the charge trapping may traverse the hysteresis curve in a clockwise direction.
One of the reasons for the smaller memory window in ferroelectric devices is the effect of parasitic charge trapping. Specifically, parasitic charge trapping may counteract the effect of the dipole created by the ferroelectric switching. Because these two effects tend to counteract each other, exerting influence in opposite directions, the width of the memory window in ferroelectric devices may be substantially reduced. Because charge trapping may result in a clockwise effect while ferroelectric switching may result in a counterclockwise effect, the memory window generated by the ferroelectric effect may be reduced. Added together, the net result is a counterclockwise effect due to ferroelectric switching that has a smaller hysteresis or threshold voltage shift and a cumulatively smaller ferroelectric memory window.
Some of the embodiments described herein may use a ferroelectric device combined with additional layers that provide interface switching modulation (ISM) effect to overcome these challenges by overcompensating for the parasitic charge trapping and creating a memory window in a hybrid ferroelectric device that is large enough to represent more than four states and enable the reliable operation of a memory device with more than a 2-bit capacity. The ISM layers that may be added to a ferroelectric device may create material dipoles that react to applied voltages in much the same way that ferroelectric dipoles react to applied voltages. However, the material dipoles in the ISM layers tend to interact constructively with the effect of the ferroelectric dipoles. Both the ferroelectric dipoles in the material dipoles have an effect that moves around the threshold voltage of device in a counterclockwise direction. Therefore, instead of the countering effect of the ferroelectric dipoles like the charge trapping phenomena described above, these embodiments instead increase the size of the memory window by additively combining the effects of the ferroelectric dipoles and the material dipoles.
In addition to additively increasing the memory window, the ISM material dipole described below is reversible, such that they may be both reset and set to represent binary 0 and binary 1 levels. The ISM materials may also follow the reversibility and reorientation of the ferroelectric dipole. The resulting dipoles caused by both the ferroelectric material and the ISM layers may generate individual internal electric fields oriented in the same direction. The individual electric fields may combine their effective strength additively to form an overall internal electric field within the active layers (ferroelectric and ISM) of the device. This overall internal electric field may be used for the development of enhanced ferroelectric tunnel junction devices (ISM e-FTJs) where the ISM layers are used as an enhancer of the polarization in the ferroelectric tunnel junction. These materials may also be used to form enhanced ferroelectric field effect transistors (ISM e-FeFETs) where the ISM layers enhance the internal field generated by polarization of the ferroelectric material within the FeFET.
The hafnium oxide 402 may have a strong affinity for oxygen ions. Therefore, the hafnium oxide may remove oxygen ions from the silicon oxide 406 such that the silicon oxide 406 becomes depleted. The result is an excess of oxygen ions in the ISM layers. Additionally, because the titanium oxide exists as a monolayer as ions, an excess of titanium ions may also roam freely in this area around the other materials. Therefore, the resulting material in the gate device has available titanium ions and oxygen ions.
When a negative voltage is applied to the gate 410, the positive titanium ions will be attracted to the top of the gate 410, while the negative oxygen ions will be repelled towards the bottom of the gate towards the channel 408. This effectively creates a dipole using the positive titanium ions and the negative oxygen ions. This dipole forms an electric field in the device and in turn changes the conductivity of the channel 408 to a positive polarity by attracting majority carriers and setting the device into an accumulation mode in the case of p-type semiconductors. In consequence, a threshold voltage shift toward higher gate voltages or a higher voltage may be need to be applied to a gate of the device to turn on the transistor.
Each of the individual layer combinations illustrated in
As the strength of the internal electric field 540 increases, its impact on inversion and accumulation of channel, and its effect on the memory window for the device may also increase. Not only is the electric field 540 strengthened, but the effect of the reversal of this internal electric field 540 during program/erase cycles is counterclockwise in the drain-current/gate voltage hysteresis diagram, which aligns with the counterclockwise effect of the ferroelectric dipoles described above.
Each combination of a hafnium oxide layer, a titanium oxide monolayer, and a silicon oxide layer may be referred to herein as an ISM layer. For example, layers 504, 520, and 512 may form a first ISM layer; layers 510, 522, and 508 may form a second ISM layer; and layers 506, 524, and 504 may form a third ISM layer. Throughout this disclosure, any instance of a single ISM layer may be replaced with multiple ISM layers. Single ISM layers are illustrated in most of the figures for the sake of clarity. However, in any embodiment and in any of the examples described herein, a single ISM layer may represent one or more ISM layers stacked on top of each other without limitation.
In additional to multiple ISM layers being present within the device 500 that are not specifically illustrated in
The vertical axis of the band diagram 700 illustrates the thickness of the various layers. In this embodiment, each of the layers is approximately 2 nm thick. Other embodiments may increase or decrease this thickness. For example, some embodiments may use silicon-based layers 512, 508, 504 that have a greater/lesser thickness than the hafnium-based layers 514, 510, 506, while other embodiments may be fabricated such that each of the silicon-based layers and hafnium-based layers are approximately the same thickness. The thickness of each layer may range from between approximately 1 nm and approximately 5 nm. Increasing the thickness of each of the layers beyond the 2 nm illustrated in
Although hafnium oxide, silicon oxide, and titanium oxide are used as examples for materials in the ISM, other materials having similar properties may be used as substitutes. In any embodiments, the hafnium oxide may be replaced with materials such as ZrOx, HfOx, ZrOx doped with various elements such as Si, Al, Y, Sr, Gd, N, La, and/or any combination of these materials.
When a negative voltage is applied to the gate 810, ferroelectric dipoles may form in the ferroelectric layer 802 as described above in
The electrode on the gate 810 may be manufactured from any metal conductor, such as titanium, platinum, aluminum, and other similar materials. The electrode metal may be more than approximately 3 nm thick. The ferroelectric layer 802 may be between approximately 2 nm and approximately 20 nm thick. The size of the memory window is proportional to the thickness of the ferroelectric layer 802, so increasing the size of the ferroelectric layer 802 may increase the size of the memory window. However, increasing the thickness of the ferroelectric layer 802 may also increase the operating voltage proportionally. Therefore, a trade-off exists between increasing the size of the memory window and minimizing the operating voltage. Some embodiments have used a ferroelectric layer 802 having a thickness of approximately 10 nm as an acceptable balance between these two factors.
As with most FET transistor implementations, a silicon oxide interfacial barrier layer 801 may be placed above the channel and the gate stack constituents. The silicon oxide barrier 801 may be approximately 0.8 nm or less in thickness. Some embodiments may also control the doping of the silicon substrate and/or the halo implant for the device along with the work function of the metal material used for the electrode on the gate 810. Adjusting these two parameters can be used to tune the location of the voltage required to change the state of the device. For example, the differential between the doping of the substrate and the work functions of the metal used on the gate may be used to generate an internal electric field that adjusts the Vi level of the device. The circuit designer may specify a predefined on-voltage for the device and adjust the work function of the gate electrode and the doping of the silicon channel to generate the predefined on-voltage.
To fabricate an ISM e-FTJ, one or more ISM layers may be added next to the ferroelectric layer of the device to further modulate the barrier and produce a tunneling improvement in the device. Just as the ISM layers amplified the effect of the ferroelectric dipoles to increase the memory window in the ISM e-FeFET, the material dipoles created by the ISM layer may amplify the band-bending effect produced by the ferroelectric dipoles in a two-terminal tunnel junction device and change the tunneling barrier and probability, which in turn enhances the memory window and distance between the ON and OFF currents.
An ISM e-FTJ may be fabricated by providing a top electrode 902 and a bottom electrode 908. These electrodes may also be referred to as first and second electrodes to distinguish them from each other. The top electrode 902 and the bottom electrode 908 may be fabricated using any conductive metal such as titanium, platinum, or other similar metals/alloys. In some embodiments, the top electrode 902 and/or the bottom electrode 908 may be fabricated using silicon, polysilicon, or highly doped Si or SiGe. In some embodiments, the materials used for the top electrode 902 and the bottom electrode 908 may be different. Each of these two materials may have different work functions, and the work function differential between these materials may generate an internal electric field that can be used to tune the current to turn on the device. The work function differential may also be used to tune retention tunneling for the device. For example, a work function differential may be created between the two electrodes 902, 908 of approximately 0.4 V-0.8 V to move the on-current to the desired level.
The device may also include a ferroelectric layer 904. The thickness of the ferroelectric layer 904 may be approximately 10 nm, and may be within the range of approximately 3 nm to approximately 20 nm. The ferroelectric layer 904 may be fabricated using a layer of hafnium oxide, a mixture of HfO2 and ZrO2, or other similar materials such as Sc:AlN, strained HfOx, HfOx, mixtures of HfOx and ZrOx, HZO, HfOx, or H2O doped with Si, Al, Y, Sr, Gd, N, La and/or other similar materials. Additionally, traditional ferroelectrics such as PZT, SBT, STO and BFO may also be used instead of transitional metal oxide ferroelectrics. Next to the ferroelectric layer 904, one or more ISM layers 906 may be fabricated. For example, some embodiments may use one ISM layer, two ISM layers, three ISM layers, or more ISM layers to amplify the band-bending affect. One exemplary embodiment has used three ISM layers to produce effective results. The thickness of the internal hafnium oxide and/or silicon oxide layers in each of the ISM layers 906 may be approximately 1 nm to approximately 3 nm in thickness.
The method may also include depositing a ferroelectric layer located between the first electrode and the second electrode/semiconductor (1204). The ferroelectric layer may be fabricated using any of the materials or techniques described above in this disclosure. The method may further include depositing one or more ISM layers also located between the first electrode and the second electrode/semiconductor. As described above, each of the ISM layers may be fabricated from three individual layers. For example, an ISM layer may include a layer of hafnium oxide, a monolayer of titanium oxide, and a layer of silicon oxide. Other similar materials may be substituted for these materials as described above.
The ferroelectric layer and the one or more ISM layers may be deposited in any order and in any combination. For example, an ISM e-FeFET process may deposit the first electrode as a gate electrode, a first number of ISM layers next to the gate electrode, a ferroelectric layer next to the first number of ISM layers, and a second number of ISM layers on the other side of the ferroelectric layer to form a transistor gate stack. A source and drain region may be defined in a semiconductor material to form a transistor device. In another example, an ISM e-FTJ process may deposit a first electrode, a ferroelectric layer next to the first electrode, one or more ISM layers next to the ferroelectric layer, followed by a second electrode. Other combinations, numbers, and distributions of ferroelectric layers and/or ISM layers may be deposited between the electrodes in any combination and without limitation. The specific configurations of ferroelectric layers and ISM layers illustrated in the figures are provided only by way of example and are not meant to be limiting.
It should be appreciated that the specific steps illustrated in
Throughout this disclosure, the term “approximately” may be used to describe values that occur within a range of −15% to +15% of the stated value. For example, a capacitance of approximately 100 nm may fall within the range of 85 nm to 115 nm.
In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, to one skilled in the art that embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.
The foregoing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the foregoing description of the example embodiments will provide those skilled in the art with an enabling description for implementing an example embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of various embodiments as set forth in the appended claims.
Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail in order to avoid obscuring the embodiments.
Also, it is noted that individual embodiments may have beeen described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may have described the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed, but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.
In the foregoing specification, aspects various embodiments are described with reference to specific embodiments, but those skilled in the art will recognize that the invention is not limited thereto. Various features and aspects of the above-described embodiments may be used individually or jointly. Further, embodiments can be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.
