Claims
- 1. A ferroelectric memory array, comprising:
a memory cell field containing a multiplicity of memory cells each having at least one selector transistor with a control terminal, a short-circuit transistor with a controllable path and a control terminal, and a storage capacitor with electrodes, said controllable path of said short-circuit transistor disposed between said electrodes of said storage capacitor, said short-circuit transistor having a different switch-on voltage than said selector transistor; word lines connected to and driving said memory cells, said word lines connected to said control terminal of said selector transistor and said control terminal of said short-circuit transistor; and bit lines connected to said memory cells.
- 2. The ferroelectric memory array according to claim 1, wherein said selector transistor and said short-circuit transistor are alternately connected to said word lines and said word lines serving as both a word line and a control line.
- 3. The ferroelectric memory array according to claim 1, wherein said short-circuit transistor is a depletion type field-effect transistor.
- 4. The ferroelectric memory array according to claim 1, wherein said storage capacitor is a stacked capacitor disposed above said selector transistor.
- 5. The ferroelectric memory array according to claim 1, wherein said storage capacitor is an offset capacitor disposed next to said selector transistor.
- 6. A ferroelectric memory array, comprising:
a memory cell field containing a multiplicity of memory cells having selector transistors with control terminals, short-circuit transistors with controllable paths and control terminals, and storage capacitors with electrodes, each of said controllable paths of said short-circuit transistors disposed between respective ones of said electrodes of said storage capacitors, said short-circuit transistors having a different switch-on voltage than said selector transistors; word lines connected to and driving said memory cells, said word lines connected to said control terminals of said selector transistor and to said control terminals of said short-circuit transistors; and bit lines connected to said memory cells.
- 7. The ferroelectric memory array according to claim 6, wherein said selector transistors and said short-circuit transistors are alternately connected to said word lines and said word lines serving as both a word line and a control line.
Priority Claims (1)
Number |
Date |
Country |
Kind |
198 32 994.6 |
Jul 1998 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International Application No. PCT/DE99/02071, filed Jul. 5, 1999, which designated the United States.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE99/02071 |
Jul 1999 |
US |
Child |
09767804 |
Jan 2001 |
US |