Ferroelectric memory device

Abstract

A ferroelectric memory device includes a memory cell, read circuit, temperature sensing circuit, and read controller. The memory cell includes a ferroelectric capacitor. The read circuit is configured to read data from the memory cell. The temperature sensing circuit is configured to sense the ambient temperature of the memory cell. The read controller is configured to receive a temperature sensing signal from the temperature sensing circuit, and inhibit a data read operation by the read circuit when the temperature sensed by the temperature sensing circuit is higher than a preset temperature.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram showing the arrangement of a ferroelectric memory device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing the arrangement of a cell array in the ferroelectric memory device according to the embodiment of the present invention;

FIG. 3 is a flowchart of a read sequence in the ferroelectric memory device according to the embodiment of the present invention;

FIG. 4 is a graph showing the relationship between the voltage and polarization of a ferroelectric capacitor;

FIG. 5 is a graph showing the relationship between the temperature and spontaneous polarization amount of the ferroelectric capacitor;

FIG. 6 is a graph showing the relationship between the absolute value of a signal amount in a read operation and the temperature of the ferroelectric capacitor;

FIG. 7 is a block diagram showing the arrangement of a temperature sensing circuit according to the embodiment of the present invention;

FIG. 8 is a circuit diagram showing the arrangement of the temperature sensing circuit and a read controller accordingly to the embodiment of the present invention;

FIG. 9 is a circuit diagram showing another arrangement of the temperature sensing circuit and read controller according to the embodiment of the present invention;

FIG. 10 is a circuit diagram showing the arrangement of a temperature sensing circuit and read controller capable of adjusting the set temperature after fabrication according to the embodiment of the present invention; and

FIG. 11 is a circuit diagram showing another arrangement of the temperature sensing circuit and read controller capable of adjusting the set temperature after fabrication according to the embodiment of the present invention.

Claims

1. A ferroelectric memory device comprising: a memory cell comprising a ferroelectric capacitor;a read circuit configured to read data from the memory cell;a temperature sensing circuit configured to sense an ambient temperature of the memory cell; anda read controller configured to receive a temperature sensing signal from the temperature sensing circuit, and inhibit a data read operation by the read circuit when the temperature sensed by the temperature sensing circuit is higher than a preset temperature.

2. A device according to claim 1, further comprising: an output node which outputs an error signal for notifying an external device that the data read operation by the read circuit is inhibited,wherein if the temperature sensed by the temperature sensing circuit is higher than the preset temperature, the temperature sensing signal output from the temperature sensing circuit is output as the error signal from the output node.

3. A device according to claim 1, wherein the temperature sensing circuit comprises an element which changes a resistance value with a temperature, a current supply circuit configured to supply an electric current to the element, and a potential sensing circuit configured to sense an electric potential of one electrode of the element.

4. A device according to claim 1, wherein the read controller comprises a logic circuit which receives the temperature sensing signal and the read signal.

5. A device according to claim 3, wherein the element comprises a ferroelectric capacitor.

6. A device according to claim 3, wherein the element comprises a transistor, the current supply circuit comprises a power supply and a resistor, and the potential sensing circuit comprises an inverter.

7. A device according to claim 3, wherein the element comprises a polysilicon interconnection, the current supply circuit comprises a power supply and a resistor, and the potential sensing circuit comprises an inverter.

8. A device according to claim 3, wherein the current supply circuit further comprises a switch which supplies different electric currents to the element by selecting a plurality of current supply paths.

9. A device according to claim 5, wherein the current supply circuit comprises a power supply and a resistor, and the potential sensing circuit comprises an inverter.

10. A device according to claim 1, wherein the temperature sensing circuit comprises a plurality of elements each of which changes a resistance value with a temperature, a plurality of current supply circuits configured to supply electric currents to said plurality of elements, a switch which selects one electrode of one of said plurality of elements, and a potential sensing circuit configured to sense a potential of the selected electrode.

11. A device according to claim 2, wherein the temperature sensing circuit comprises an element which changes a resistance value with a temperature, a current supply circuit configured to supply an electric current to the element, and an inverter which receives a potential of one electrode of the element, an output signal from the inverter is output as the error signal from the output node, and the read controller comprises a logic circuit which receives the output signal from the inverter and the read signal.

12. A device according to claim 5, wherein the current supply circuit further comprises a switch which supplies different electric currents to the element by selecting a plurality of current supply paths.

13. A device according to claim 12, wherein said plurality of current supply paths extend via resistors different in resistance value.

14. A device according to claim 11, wherein the element comprises a ferroelectric capacitor, and the logic circuit comprises an AND circuit including an input terminal connected to an inverter.

15. A device according to claim 11, wherein the element comprises a transistor, and the logic circuit comprises an AND circuit.

16. A device according to claim 1, wherein the temperature sensing circuit comprises a temperature sensor which measures an ambient temperature of the memory cell, a set temperature storage unit which stores the preset temperature, and a comparator which is connected to the temperature sensor and the set temperature storage unit and compares the ambient temperature of the memory cell with the preset temperature.

17. A device according to claim 1, wherein the preset temperature is lower than a phase transition temperature of a ferroelectric material forming the ferroelectric capacitor.

18. A data read method in a ferroelectric memory device comprising a memory cell which comprises a ferroelectric capacitor, a read circuit configured to read data from the memory cell, and a temperature sensing circuit configured to sense an ambient temperature of the memory cell, comprising: receiving a read signal which designates data read from the memory cell from external;determining whether a temperature sensed by the temperature sensing circuit is higher than a preset temperature; andinhibiting a data read operation by the read circuit when the sensed temperature is higher than the preset temperature.

19. A method according to claim 18, wherein the temperature sensing circuit starts sensing the temperature after the read signal is received and before the determination is performed.