Field effect transistor devices with low source resistance

Abstract

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Description

FIELD OF THE INVENTION

The present invention relates to electronic devices and fabrication methods. More particularly, the present invention relates to high power insulated gate transistors and fabrication methods.

BACKGROUND

Power devices made with silicon carbide (SiC) are expected to show great advantages as compared to those on silicon for high speed, high power and/or high temperature applications due to the high critical field and wide band gap of SiC. For devices capable of blocking high voltages, such as voltages in excess of about 5 kV, it may be desirable to have bipolar operation to reduce the drift layer resistance via conductivity modulation resulting from injected minority carriers. However, one technical challenge for bipolar devices in silicon carbide is forward voltage degradation over time, possibly due to the presence of Basal Plane Dislocations (BPD) in single crystals of silicon carbide. Thus, unipolar devices such as SiC Schottky diodes and MOSFETs are typically used for high power applications, e.g., up to 10 kV or more.

SiC DMOSFET devices with a 10 kV blocking capability have been fabricated with a specific on-resistance of about 100 mΩ×cm². DMOSFET devices may exhibit very fast switching speeds of, for example, less than 100 ns, due to their majority carrier nature. However, as the desired blocking voltage of devices increases, for example up to 15 kV or more, the on-resistance of a MOSFET device may increase substantially, due to the corresponding increase in the drift layer thickness. This problem may be exacerbated at high temperatures due to bulk mobility reduction, which may result in excessive power dissipation.

With the progress of SiC crystal material growth, several approaches have been developed to mitigate BPD related problems. See, e.g., B. Hull, M. Das, J. Sumakeris, J. Richmond, and S. Krishinaswami, “Drift-Free 10-kV, 20-A 4H—SiC PiN Diodes”, Journal of Electrical Materials, Vol. 34, No. 4, 2005. These developments may enhance the development and/or potential applications of SiC bipolar devices such as thyristors, GTOs, etc. Even though thyristors and/or GTOs may offer low forward voltage drops, they may require bulky commutating circuits for the gate drive and protections. Accordingly, it may be desirable for a SiC bipolar device to have gate turn-off capability. Due to their superior on-state characteristics, reasonable switching speed, and/or excellent safe-operation-area (SOA), 4H—SiC insulated gate bipolar transistors (IGBTs) are becoming more suitable for power switching applications.

SUMMARY

A semiconductor device according to some embodiments includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region, and a source ohmic contact is in contact with the source contact regions and the body contact region.

The body contact region may include a plurality of body contact regions that are interspersed between the source contact regions. The plurality of body contact regions may be spaced apart from the channel region by the lateral source region.

The source ohmic contact may be in contact with the source region in a source contact area and the source ohmic contact may be in contact with the body contact region in a body contact region area.

In some embodiments, a ratio of a minimum dimension p1 of the contact region area to a minimum dimension w1 of the well region may be greater than 0.2. In further embodiments, the ratio of the minimum dimension p1 of the contact region area to the minimum dimension w1 of the well region may be greater than about 0.3.

The drift region may include a wide bandgap semiconductor material, such as silicon carbide.

The source region has a sheet resistance and the source ohmic contact has a sheet resistance that is greater than 75% of the contact resistance of the source region, and in some embodiments is greater than the contact resistance of the source region.

The device may have a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiment(s) of the invention. In the drawings:

FIG. 1 is a circuit diagram of a metal-oxide-semiconductor field effect (MOSFET) device.

FIG. 2 is a graph illustrating hypothetical on-state current-voltage characteristics for a MOSFET device.

FIG. 3 is a graph illustrating the effect of source resistance on gate voltage.

FIG. 4 is a partial cross sectional illustration of cell of a conventional power MOSFET device.

FIGS. 5 and 6 are plan views illustrating layouts of conventional power MOSFET devices.

FIGS. 7 and 8 are plan views illustrating layouts of power MOSFET devices according to some embodiments.

FIGS. 9 and 10 are partial cross sectional illustrations of a cell of a power MOSFET device according to some embodiments.

FIG. 11 is a graph on-state current-voltage characteristics for a MOSFET device according to some embodiments.

FIG. 12 is a cross sectional illustration of cell of a power MOSFET device according to some embodiments.

FIG. 13 is a cross sectional illustration of cell of an insulated gate bipolar transistor device according to some embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

Some embodiments of the invention are described with reference to semiconductor layers and/or regions which are characterized as having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some material may be designated with a “+” or “−” (as in n+, n−, p+, p−, n++, n−−, p++, p−−, or the like), to indicate a relatively larger (“+”) or smaller (“−”) concentration of majority carriers compared to another layer or region. However, such notation does not imply the existence of a particular concentration of majority or minority carriers in a layer or region.

Some embodiments of the invention provide silicon carbide (SiC) insulated gate devices that are suitable for high power and/or high temperature applications.

FIG. 1 is a circuit diagram of a metal oxide semiconductor field effect transistor (MOSFET) device 10. As shown therein, a MOSFET device generally includes three terminals, namely, a drain terminal (D), a source terminal (S) and a gate terminal (G). The gate-to-source voltage of the device is denoted V_GS, while the drain-to-source voltage of the device is denoted V_DS. The device has a built in source resistance R_S and a built-in drain resistance R_D based on the physical characteristics of the device. The voltage over the built-in source resistance R_S is denoted V_Rs.

In a MOSFET device, current passing through a channel of the device from the drain to the source is regulated by applying a voltage to the gate. The gate is insulated from the channel by a gate insulator, such as silicon dioxide. As the voltage on the gate terminal is increased, current passing through the device may increase.

FIG. 2 is a graph illustrating hypothetical (curve 102) and actual (104) on-state current-voltage characteristics for a MOSFET device for a given gate-to-source voltage (V_GS). As shown in FIG. 2, for a given gate voltage, the current through the device (I_D) increases as the voltage between the drain and source (V_DS) increases, up to a saturation point. In actual devices, the actual saturation current of a transistor is typically less than the ideal saturation current. Part of the reason for this relates to the source resistance of the device.

In particular, as the drain current I_D passing through the device increases, the amount of voltage dropped over the source resistance R_S increases in direct proportion. FIG. 3 is a graph illustrating the effect of source resistance on gate voltage. In FIG. 3, the voltage from the gate terminal to the source terminal is denoted V_GS. A portion of the gate voltage V_GS applied to the device across the gate and source terminals is dropped over the internal source resistance R_S of the device. That portion of the gate voltage is denoted V_Rs in FIG. 3. The remainder of the gate-to-source voltage appears as a voltage across the gate insulator, denoted V_GS,int in FIG. 3. Thus, V_GS is equal to the sum of V_Rs and V_GS,int.

As shown in FIG. 3, the gate-to-source voltage may remain constant as the drain current increases. However, the portion of the gate voltage V_GS that is dropped over the internal source resistance of the device, V_Rs, increases as the drain current I_D increases, while the portion of the gate-to-source voltage that appears as a voltage across the gate insulator, V_GS,int, decreases as the drain current I_D increases.

Thus, as the drain current increases the portion of the gate voltage that is being used to maintain the channel decreases, which may cause the device to go into saturation at a lower level of drain-to-source voltage. Accordingly, a high source resistance can adversely affect the operation of a MOSFET or other insulated gate controlled device.

A unit cell 10 of a MOSFET structure according to some embodiments is shown in FIG. 4. The device 10 of FIG. 1 includes an n− drift epitaxial layer 14 on an n-type, 8° off-axis 4H—SiC substrate 12. The n− drift layer 14 may have a thickness of about 100 μm to about 120 μm, and may be doped with n-type dopants at a doping concentration of about 2×10¹⁴ cm⁻³ to about 6×10¹⁴ cm⁻³ for a blocking capability of about 10 kV. Other doping concentrations/voltage blocking ranges are also possible.

The structure further includes a p+ well region 18 and an n+ source region 20 that may be formed by selective implantation of, for example, aluminum and nitrogen, respectively. The junction depth of the p+ well region 18 may be about 0.5 μm, although other depths are possible. The structure 10 further includes a p+ contact region 22 that extends from a surface of the drift layer 14 into the p+ well region 18. A junction termination (not shown) may be provided around the device periphery.

All of the implanted dopants may be activated by annealing the structure at a temperature of about 1600° C. with a silicon over pressure and/or covered by an encapsulation layer such as a graphite film. A high temperature anneal may damage the surface of the silicon carbide epitaxy. In order to reduce such damage, a graphite coating may be formed on the surface of the device. Prior to annealing the device to activate the implanted ions, a graphite coating may be applied to the top/front side of the structure in order to protect the surface of the structure during the anneal. The graphite coating may be applied by a conventional resist coating method and may have a thickness of about 1 μm. The graphite coating may be heated to form a crystalline coating on the drift layer 14. The implanted ions may be activated by a thermal anneal that may be performed, for example, in an inert gas at a temperature of about 1600° C. or greater. In particular the thermal anneal may be performed at a temperature of about 1600° C. in argon for 5 minutes. The graphite coating may help to protect the surface of the drift layer 14 during the high temperature anneal.

The graphite coating may then be removed, for example, by ashing and thermal oxidation.

After implant annealing, a field oxide of silicon dioxide (not shown) having a thickness of about 1 μm may be deposited and patterned to expose the active region of the device.

A gate oxide layer 36 may be formed by a gate oxidation process, with a final gate oxide thickness of 400-600 Å.

In particular, the gate oxide may be grown by a dry-wet oxidation process that includes a growth of bulk oxide in dry O₂ followed by an anneal of the bulk oxide in wet O₂ as described, for example, in U.S. Pat. No. 5,972,801, the disclosure of which is incorporated herein by reference in its entirety. As used herein, anneal of oxide in wet O₂ refers to anneal of an oxide in an ambient containing both O₂ and vaporized H₂O. An anneal may be performed in between the dry oxide growth and the wet oxide growth. The dry O₂ oxide growth may be performed, for example, in a quartz tube at a temperature of up to about 1200° C. in dry O₂ for a time of at least about 2.5 hours. Dry oxide growth is performed to grow the bulk oxide layer to a desired thickness. The temperature of the dry oxide growth may affect the oxide growth rate. For example, higher process temperatures may produce higher oxide growth rates. The maximum growth temperature may be dependent on the system used.

In some embodiments, the dry O₂ oxide growth may be performed at a temperature of about 1175° C. in dry O₂ for about 3.5 hours. The resulting oxide layer may be annealed at a temperature of up to about 1200° C. in an inert atmosphere. In particular, the resulting oxide layer may be annealed at a temperature of about 1175° C. in Ar for about 1 hour. The wet O₂ oxide anneal may be performed at a temperature of about 950° C. or less for a time of at least about 1 hour. The temperature of the wet O₂ anneal may be limited to discourage further thermal oxide growth at the SiC/SiO₂ interface, which may introduce additional interface states. In particular, the wet O₂ anneal may be performed in wet O₂ at a temperature of about 950° C. for about 3 hours. The resulting gate oxide layer may have a thickness of about 500 Å.

In some embodiments, the dry O₂ oxide growth may be performed at a temperature of about 1175° C. in dry O₂ for about 4 hours. The resulting oxide layer may be annealed at a temperature of up to about 1175° C. in an inert atmosphere. In particular, the resulting oxide layer may be annealed at a temperature of about 1175° C. in Ar for about a time duration ranging from 30 min to 2 hours. Then the oxide layer receives an anneal in NO ambient at a temperature ranging from 1175 C to 1300 C, for a duration ranging from 30 minutes to 3 hours. The resulting gate oxide layer may have a thickness of about 500 Å.

After formation of the gate oxide 36, a polysilicon gate 32 may be deposited and doped, for example, with boron followed by a metallization process to reduce the gate resistance. Al/Ni contacts may be deposited as the p-type ohmic source contact metal 28, and Ni as the n-type drain contact metal 26. All contacts may be sintered in a Rapid Thermal Annealer (RTA), and thick Ti/Au layers may be used for pad metals.

Referring to FIG. 4, the source resistance of a MOSFET device has two primary components, namely, the contact resistance R_C between the source ohmic contact 34 and the source region 20, and the sheet resistance R_sheet in the source region 20 between the source ohmic contact 34 and the channel. Thus, R_S=R_C+R_sheet. In a conventional silicon-based MOSFET device, the sheet resistance R_sheet is the dominant factor in determining the source resistance, because it is possible to form very low resistivity ohmic contacts to silicon and other narrow-bandgap semiconductors. However, in wide bandgap semiconductors (i.e., semiconductors having a bandgap greater than about 2.0 V), including compound semiconductor materials, such as silicon carbide and gallium nitride, diamond, and ZnO, the contact resistance R_C may be the dominant contributor to the source resistance. In particular, it is difficult to form very low resistivity ohmic contacts to silicon carbide and other wide bandgap materials because of the high energy barrier associated with such materials.

FIGS. 5 and 6 are plan views illustrating layouts of conventional power MOSFET devices. In a conventional power MOSFET device, the layout is designed to reduce or minimize sheet resistance under the assumption that contact resistance is less important than sheet resistance. Thus, referring to FIG. 5, a conventional power MOSFET device typically includes a p-well 18 formed in a drift layer 14, an n+ source region 20 in the p-well 18, and a p+ contact region 22 in the n+ source region 20. Referring to FIG. 6, a source contact 34 is formed on the n+ source region 20 and the p+ contact region 22. A gate 32 is formed over the p-well 18 and overlaps the periphery of the n+ source region 20 and adjacent portions of the drift layer 14. Current flow from the drain to the source is indicated by the arrows 42 in FIG. 5.

As noted above, in a wide bandgap semiconductor material system, the source resistance may be more affected by the contact resistance of the source ohmic contact than by the sheet resistance of the source layer. Accordingly, to decrease the source resistance of a wide bandgap power semiconductor device, it may be desirable to decrease the contact resistance of the source ohmic contact. In general, contact resistance can be decreased by increasing the minimum dimension of the contact, which is the smallest dimension of the contact in any direction. However, simply increasing the minimum dimension of the source ohmic contact of an electronic device can undesirably increase the cell to cell spacing, or pitch, of the device. The pitch of a MOSFET device may be proportional to the width of the p-well region of the device. Increasing the pitch of the device reduces the density of the devices that can be formed on a single substrate, reducing the devices yielded and increasing manufacturing costs.

According to some embodiments, an insulated gate device layout is provided that increases the minimum dimension of the source ohmic contact without increasing the pitch of the device and/or the width of the p-well region of the device. A device layout according to some embodiments may increase the sheet resistance of the device. Such an effect may be highly undesirable in a device based on a narrow bandgap semiconductor material. However, since sheet resistance is not the dominant factor in determining source resistance of a wide bandgap device, such a tradeoff may be acceptable for wide bandgap devices. In devices according to some embodiments, a ratio of the source sheet resistance to the source contact resistance may be greater than 0.75 (i.e. R_sheet/R_C>0.75). In some embodiments, the device may have a source contact resistance that is less than the source sheet resistance. That is, in some embodiments, the ratio of the source sheet resistance to the source contact resistance may be greater than 1 (i.e. R_sheet/R_C>1), and in further embodiments, the ratio of the source sheet resistance to the source contact resistance may be greater than 5.

FIGS. 7 and 8 are plan views illustrating layouts of MOSFET device cells 100 according to some embodiments, and FIGS. 9 and 10 are partial cross sectional illustrations of a cell of a MOSFET device according to some embodiments. In particular, FIG. 9 is a cross section taken along line A-A′ of FIG. 8, while FIG. 10 is a cross section taken along line B-B′ of FIG. 8.

The device 100 shown in FIGS. 7-10 includes an n− drift epitaxial layer 114 on an n-type, 8° off-axis 4H—SiC substrate 112. The n− drift layer 114 may have a thickness of about 100 μm to about 120 μm, and may be doped with n-type dopants at a doping concentration of about 2×10¹⁴ cm⁻³ to about 6×10¹⁴ cm⁻³ for a blocking capability of about 10 kV.

The structure further includes a p+ well region 118 and an n+ source region 120 that may be formed by selective implantation of, for example, aluminum and nitrogen, respectively. The junction depth of the p+ well region 118 may be about 0.5 μm. The structure 100 further includes a plurality of p+ contact regions 122 that extend from a surface of the drift layer 114 into the p+ well region 118. A junction termination (not shown) may be provided around the device periphery.

Referring to FIG. 7, the n+ source region 120 includes a pair of lateral source regions 120A that are parallel to opposing channel regions 125 in the p-well 118. A plurality of source contact regions 120B extend between the lateral source regions 120A, and the plurality of p+ contact regions 122 are provided between the source contact regions 120B.

Referring to FIG. 8, gate contacts 132 are formed over the channel regions 125 and overlap the lateral source regions 120A. A source ohmic contact 134 is formed across the source contact regions 120B and the p+ contact regions 122. The source ohmic contact 134 overlaps the source contact regions 120B in a source contact region 136. The source ohmic contact 134 overlaps the p+ contact regions 122 in a body contact region 138.

The portion of the source contact regions 120B contacted by the source ohmic contact 134 may have a minimum dimension that is larger than the minimum dimension that can be obtained for a conventional layout such as the layout shown in FIGS. 5 and 6 for a similar pitch/p-well size. Accordingly, the source contact resistance may be reduced without substantially increasing the device pitch/p-well size. The “minimum dimension” of a feature refers to the smallest width of the feature in any cross section of the feature. For example, the minimum dimension p1 of the body contact region 138, the minimum dimension n1 of the n-type contact region 136 and the minimum dimension w1 of the p-well region 118 are shown in FIG. 8.

In a device having a layout as shown in FIGS. 7 and 8, current flow to the source contact flows through the source contact regions 120B, as indicated by the arrows 142 in FIG. 7. The source contact regions 120B may have an increased sheet resistance compared to the source region of a device having a conventional layout as shown in FIGS. 5 and 6. However, the increase in sheet resistance may be more than compensated by the decrease in contact resistance, thus providing an overall decrease in the source resistance of the device.

FIG. 11 is a graph of on-state current-voltage characteristics for a 7 mm×8 mm 1200 V silicon carbide MOSFET device according to some embodiments. In the device characteristics illustrated in FIG. 11, a drain current (I_D) of 377 A was measured at a forward voltage drain-to-source voltage (V_DS) of 3.8 V. The current density, normalized to the active area, was over 750 A/cm².

The on-resistance of a MOSFET device is affected by the drain resistance, the channel resistance and the source resistance of the device. Accordingly, reducing the source resistance of the device also reduces the on-resistance of the device.

A wide bandgap MOSFET device having a layout according to some embodiments may be capable of substantially increased saturation current due to the lower on-resistance of the device and the fact that increased current levels have less of a de-biasing effect on the gate. That is, because of the lower source resistance, less voltage will be developed over the source resistance as the drain current increases. Thus, more of the gate-to-source voltage is applied to the channel of the device.

FIG. 12 is an idealized cross section of a device having a layout in accordance with some embodiments. In particular, FIG. 12 illustrates some dimensions of a device having a layout in accordance with some embodiments. For example, as shown in FIG. 12, the minimum dimension of the implanted cell area (i.e. the p-well 118) is denoted as width w1 in FIG. 12. It will be appreciated, however, that the minimum dimension of the p-well 118 may occur in a dimension that is different from the plane of the device illustrated in FIG. 12. For example, the minimum dimension of the p-well 118 may occur in a dimension that is perpendicular to the plane of the device illustrated in FIG. 12.

The minimum dimension of the n-type contact area is denoted as width n1 in FIG. 12, while the minimum dimension of the p-type contact area is denoted as width p1 in FIG. 12. The n-type contact area may be defined as the area of overlap between the source ohmic contact 134 and the n+ source region 120, while the p-type contact area may be defined as the area of overlap between the source ohmic contact 134 and the p+ contact regions 122.

An insulated gate bipolar transistor (IGBT) device 200 according to some embodiments is illustrated in FIG. 13. As shown therein, the IGBT device includes an n− drift epitaxial layer 214 on a p-type epitaxial layer 212. The p-type epitaxial layer 212 is formed on a p-type, 8° off-axis 4H—SiC substrate 210. The n− drift layer 214 may have a thickness of about 100 μm to about 120 μm, and may be doped with p-type dopants at a doping concentration of about 2×10¹⁴ cm⁻³ to about 6×10¹⁴ cm⁻³ for a blocking capability of about 10 kV.

The IGBT structure 200 further includes a p+ well region 218 and an n+ source/emitter region 220 that may be formed by selective implantation of, for example, aluminum and nitrogen, respectively. The junction depth of the p+ well region 218 may be about 0.5 μm. The structure 200 further includes a plurality of p+ body contact regions 222 that extend from a surface of the drift layer 214 into the p+ well region 218. The conductivity types may be reversed in some embodiments.

A gate contact 232 is on a gate insulator 236, a source/emitter contact 234 is on the source contact regions 220 and the body contact regions 222. A collector contact 226 contacts the substrate 210.

According to some embodiments, a transistor device may have a ratio of n1 to w1 that is greater than 0.2. In further embodiments, a transistor device may have a ratio of n1 to w1 that is greater than about 0.3. In further embodiments, a transistor device may have a ratio of n1 to w1 that is in the range of about 0.2 to 1. In further embodiments, a transistor device may have a ratio of n1 to w1 that is in the range of about 0.3 to 1. In further embodiments, transistor device may have a ratio of n1 to w1 that is greater than 0.5. For example, the minimum dimension n1 of the n-type contact area of a device having a layout according to some embodiments may be about 2 μm for a device having a minimum dimension of the implanted cell area of 6 μm.

According to some embodiments, a transistor device may have a ratio of p1 to w1 that is greater than 0.2. In further embodiments, a transistor device may have a ratio of p1 to w1 that is greater than about 0.3. In further embodiments, a transistor device may have a ratio of p1 to w1 that is greater than about 0.5. In further embodiments, a transistor device may have a ratio of p1 to w1 that is in the range of about 0.2 to 0.5. In further embodiments, a transistor device may have a ratio of p1 to w1 that is in the range of about 0.2 to 1.

Some embodiments provide transistor devices having increased current densities. Current density is defined as the total current divided by the cross sectional area of the chip. For example, a wide bandgap transistor device according to some embodiments may be capable of current densities in excess of 200 A/cm² and a blocking voltage of 1000 V or more. A wide bandgap transistor device according to further embodiments may be capable of a current of 100 A or greater at current densities in excess of 200 A/cm², a forward voltage drop of less than 5 V and a blocking voltage of 1000 V or more. A wide bandgap transistor device according to still further embodiments may be capable of a current of 100 A or greater at current densities in excess of 300 A/cm², a forward voltage drop of less than 5 V and a blocking voltage of 1000 V or more.

A semiconductor device according to some embodiments has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A.

A semiconductor device according to further embodiments has a reverse blocking voltage of 1000 volts or more and a forward current capability greater than 100 A at a forward voltage of 5 volts or less.

A metal-oxide semiconductor field effect transistor device according to some embodiments has a reverse blocking voltage of 1200 volts or more and a forward current capability greater than 100 A.

A metal-oxide semiconductor field effect transistor device according to some embodiments has a reverse blocking voltage of 1000 volts or more and a differential on-resistance less than 8 mOhms-cm².

A semiconductor device having a blocking voltage less than 1000 V and configured to pass forward current at a current density greater than 200 amps per square centimeter at a forward voltage drop of 5 V or less.

Some embodiments may enable wide bandgap transistor devices to achieve drain currents of 100 Amps or higher at a drain to source voltage that is less than 4 Volts in a device having a cell pitch of less than 20 μm. Some embodiments may enable wide bandgap transistor devices to achieve drain currents of 100 Amps or higher at a drain to source voltage that is less than 4 Volts in a device having a cell pitch of less than 10 μm. Some embodiments may enable wide bandgap transistor devices to achieve drain currents of 80 Amps or higher at a drain to source voltage that is less than 5 Volts in a device having a cell pitch of less than 10 μm.

An IGBT device according to some embodiments with a voltage blocking capability of 10 kV or greater may have a specific on-resistance of less than 14 mOhm-cm² with a forward voltage drop of 5.2 V or less at a current density of 100 A/cm².

It will be appreciated that although some embodiments of the invention have been described in connection with silicon carbide IGBT and MOSFET devices having n-type drift layers, the present invention is not limited thereto, and may be embodied in devices having p-type substrates and/or drift layers. Furthermore, the invention may be used in many different types of devices, including but not limited to insulated gate bipolar transistors (IGBTs), MOS controlled thyristors (MCTs), insulated gate commutated thyristors (IGCTs), junction field effect transistors (JFETs), high electron mobility transistors (HEMTs), etc.

In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A semiconductor device, comprising: a drift layer having a first conductivity type;a well region in the drift layer having a second conductivity type opposite the first conductivity type;a source region in the well region, the source region having the first conductivity type and defining a channel region in the well region, wherein the source region comprises a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region;a body contact region having the second conductivity type between at least two of the plurality of source contact regions and in contact with the well region; anda source ohmic contact that is on at least one of the source contact regions and the body contact region, and that is not on the lateral source region, wherein the source ohmic contact is on the at least one of the source contact regions in a source contact region area and the source ohmic contact is on the body contact region in a body contact region area, and wherein a ratio of a minimum dimension p1 of the body contact region area to a minimum dimension w1 of the well region on a same plane as the body contact region area is greater than 0.2, wherein the body contact region comprises a plurality of body contact regions that are interspersed between the source contact regions and contact the source ohmic contact, and wherein ones of the plurality of body contact regions are not physically contacting other ones of the plurality of body contact regions.

2. The semiconductor device of claim 1, wherein the plurality of body contact regions are spaced apart from the channel region by the lateral source region.

3. The semiconductor device of claim 1, wherein a ratio of a minimum dimension n1 of the source contact region area to a minimum dimension w1 of the well region is greater than 0.2.

4. The semiconductor device of claim 3, wherein the ratio of the minimum dimension n1 of the source contact region area to the minimum dimension w1 of the well region is between 0.3 and 1.

5. The semiconductor device of claim 3, wherein the ratio of the minimum dimension n1 of the source contact region area to the minimum dimension w1 of the well region is greater than 0.5.

6. The semiconductor device of claim 1, wherein the ratio of the minimum dimension p1 of the body contact region area to the minimum dimension w1 of the well region is greater than about 0.3.

7. The semiconductor device of claim 1, wherein the ratio of the minimum dimension p1 of the body contact region area to the minimum dimension w1 of the well region is greater than about 0.5.

8. The semiconductor device of claim 1, wherein the drift region comprises a wide bandgap semiconductor material having a baudgap greater than 2.0 V.

9. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide.

10. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide having at least one of a 2H, 4H and 6H polytype.

11. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide having at least one of a 3C and 15R polytype.

12. The semiconductor device of claim 1, wherein the source region has a sheet resistance and the source ohmic contact has a contact resistance, wherein the plurality of source contact regions are arranged in a layout such that a ratio of the sheet resistance in ohms per square to the contact resistance in ohms per square area is greater than 1, wherein the square is equal in size to the square area.

13. The semiconductor device of claim 1, wherein the device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 700 amps per square centimeter.

14. The semiconductor device of claim 1, wherein the semiconductor device comprises a field effect transistor.

15. The semiconductor device of claim 1, wherein the semiconductor device comprises an insulated gate bipolar transistor.

16. The semiconductor device of claim 1, wherein each of the plurality of body contact regions is laterally adjacent to the lateral source region.

17. The semiconductor device of claim 16, further comprising a second lateral source region adjacent to ends of the plurality of body contact regions opposite the lateral source region, wherein the second lateral source region separates the plurality of body contact regions from a second channel.

18. The semiconductor device of claim 1, wherein each of the plurality of body contact regions is in contact with the source ohmic contact.

19. A semiconductor device, comprising: a drift layer having a first conductivity type;a well region having a second conductivity type that is opposite the first conductivity type;a source region in the well region, the source region having the first conductivity type;a body contact region having the second conductivity type in contact with the well region; anda source ohmic contact that is on the source region in a source contact region area and that is on the body contact region in a body contact region area;wherein a ratio of a smallest width dimension n1 of the source contact region area to a smallest width dimension w1 of the well region on a same plane as the source contact region area is greater than 0.3, wherein the body contact region is between both ends of the smallest width dimension w1.

20. The semiconductor device of claim 19, wherein the ratio of the smallest width dimension n1 of the source contact region area to the smallest width dimension w1 of the well region is greater than 0.5.

21. A semiconductor device, comprising: a drift layer having a first conductivity type;a well region having a second conductivity type that is opposite the first conductivity type;a source region in the well region, the source region having the first conductivity type;a body contact region having the second conductivity type in contact with the well region; anda source ohmic contact that is on the source region in a source contact area and that is on the body contact region in a body contact region area;wherein a ratio of a smallest width dimension p1 of the body contact region area to a smallest width dimension w1 of the well region on a same plane as the body contact region area is greater than 0.2, wherein the body contact region is between both ends of the smallest width dimension w1.

22. The semiconductor device of claim 21, wherein the ratio of the smallest width dimension p1 of the body contact region area to the smallest width dimension w1 of the well region is greater than about 0.3.

23. The semiconductor device of claim 21, wherein the ratio of the smallest width dimension p1 of the body contact region area to the smallest width dimension w1 of the well region is greater than about 0.5.