This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0131974, filed on Oct. 5, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The present disclosure relates to a field effect transistor wherein a tensile strain is applied to a two-dimensional (2D) material electrode bonding layer to increase the conductivity thereof, an electronic apparatus including the field effect transistor, and/or a method of manufacturing the field effect transistor.
Transistors, which are semiconductor devices for performing an electrical switching function, have been used for various integrated circuit (IC) devices including memories, driving ICs, logic devices, etc. In order to increase the degree of integration of an IC device, a space occupied by a transistor provided therein has been rapidly reduced, and thus, research has been conducted to reduce the size of the transistor while maintaining the performance thereof.
One of the important parts of the transistor is a gate electrode. When a voltage is applied to the gate electrode, a channel adjacent to a gate opens a path for a current and, in an opposite case, blocks a current. The performance of a semiconductor depends on how much a leakage current is reduced and efficiently managed in the gate electrode and the channel. The greater the corresponding area between the channel and the gate electrode that controls a current in the transistor, the higher the power efficiency.
As semiconductor processes become more refined, the size of the transistor is reduced, and thus, the corresponding area between the gate electrode and the channel is also reduced, which may cause problems due to a short channel effect. For example, phenomena such as threshold voltage variation, carrier velocity saturation, and deterioration of subthreshold characteristics may occur.
Provided is a field effect transistor where the conductivity of a two-dimensional (2D) material electrode bonding layer is increased.
Provided is an electronic apparatus including a field effect transistor where the conductivity of a 2D material electrode bonding layer is increased.
Provided is a method of manufacturing a field effect transistor where a tensile strain is applied to a 2D material electrode bonding layer.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an embodiment, a field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode apart from the source electrode; a channel between the source electrode and the drain electrode and including a 2D material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode and including a tensile strain region; and a stressor adjacent to the 2D material electrode bonding layer and configured to apply a tensile strain to the 2D material electrode bonding layer.
In some embodiments, the 2D material electrode bonding layer may include graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.
In some embodiments, the transition metal dichalcogenide may include a transition metal and a chalcogen element. The transition metal may include one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb. The chalcogen element may include one of S, Se, and Te.
In some embodiments, the transition metal dichalcogenide may include one of MoS2, WS2, MoSe2, and WSe2.
In some embodiments, the channel may be configured to have no tensile strain region.
In some embodiments, the 2D material electrode bonding layer may be integrally provided with the channel.
In some embodiments, the stressor may be positioned above the 2D material electrode bonding layer, below the 2D material electrode bonding layer, or below the source electrode and the drain electrode.
In some embodiments, the stressor may include a material represented by (M1)a(M2)b, wherein M1 may include any one of Mo, W, Hf, Nb, and Si, M2 may include any one of O, S, Se, Te, and N, and 0<a≤3 and 0<b≤3.
In some embodiments, the stressor may include MoO, MoO2, MoO3, PtS2, SiO2, or SiN.
In some embodiments, the 2D material electrode bonding layer may include a strain region in a region facing the stressor.
In some embodiments, the field effect transistor may further include an interlayer including TiOx (0<x≤3) or CrOx (0<x≤3) between the 2D material electrode bonding layer and the stressor.
In some embodiments, the stressor may be configured to operate as an electrode.
In some embodiments, the tensile strain region may be in the 2D material electrode bonding layer.
According to an embodiment, an electronic apparatus may include: a memory including a field effect transistor; and a memory controller configured to control the memory. The field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode spaced apart from the source electrode; a channel between the source electrode and the drain electrode and including a 2D material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode and including a tensile strain region; and a stressor adjacent to the 2D material electrode bonding layer and configured to apply a tensile strain to the 2D material electrode bonding layer.
According to an embodiment, a method of manufacturing a field effect transistor may include: forming a gate electrode on a substrate; forming an insulating layer on the gate electrode; forming a source electrode and a drain electrode on the insulating layer; forming a channel between the source electrode and the drain electrode, the channel including a 2D material; forming a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; forming a stressor adjacent to the 2D material electrode bonding layer; and applying a tensile strain to the 2D material electrode bonding layer by oxidizing the stressor.
According to an embodiment, a field effect transistor may include a substrate; a plurality of electrodes including a source electrode, a drain electrode, and a gate electrode spaced apart from each other on the substrate; a channel on the substrate between the source electrode and the drain electrode, the channel including a two-dimensional (2D) material; an insulating layer extending between the channel and the gate electrode; a first 2D material electrode bonding layer connected to a first end of the channel; and a first stressor on at least one of the insulating layer and the source electrode. The first 2D material electrode bonding layer may be spaced apart from the gate electrode and the drain electrode. The first stressor may be adjacent to the first 2D material electrode bonding layer and may be configured to apply a tensile strain to the first 2D material electrode bonding layer.
In some embodiments, the first 2D material electrode bonding layer may include graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.
In some embodiments, the first stressor may include a material represented by (M1)a(M2)b, where M1 includes any one of Mo, W, Hf, Nb, and Si, M2 includes any one of O, S, Se, Te, and N, 0<a≤3, and 0<b≤3.
In some embodiments, the first 2D material electrode bonding layer may be integrally provided with the channel.
In some embodiments, the field effect transistor may further include a second 2D material electrode bonding layer connected to a second end of the channel; and a second stressor on at least one of the insulating layer and the drain electrode. The second 2D material electrode bonding layer may be spaced apart from the gate electrode and the source electrode. The second stressor may be adjacent to the second 2D material electrode bonding layer and may be configured to apply a tensile strain to the second 2D material electrode bonding layer.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.
Hereinafter, a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor according to various embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, like reference numerals denote like elements, and the size of each element may be exaggerated for clarity and convenience of description. It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
An expression used in the singular form also encompasses the plural expression unless it has a clearly different meaning in the context. It will be further understood that when a part “includes” or “comprises” an element, the part may further include other elements, not excluding the other elements, unless defined otherwise. Also, in the drawings, the size or thickness of each element may be exaggerated for clarity of description. It will be further understood that when a material layer is referred to as being “on” another substrate or layer, the material layer may be directly on the other substrate or layer, or a third layers may be present therebetween. Also, materials constituting each layer in the following embodiments are exemplary, and other materials than the described ones may also be used.
Also, the terms “ . . . unit,” “module,” etc. used in the specification indicate a unit that processes at least one function or motion, and the unit may be implemented by hardware or software, or by a combination of hardware and software.
The particular implementations shown and described herein are examples of the present disclosure and are not intended to otherwise limit the scope of the present disclosure in any way. For brevity of the specification, descriptions of conventional electronic configurations, control systems, software, and other functional aspects of the systems may be omitted. Also, line connections or connection members between elements depicted in the drawings represent functional connections and/or physical or circuit connections by way of example, and in an actual device, they may be replaced or embodied with various suitable additional functional connections, physical connections, or circuit connections.
The use of term “the” and other similar determiners may correspond to both a singular form and a plural form.
Unless orders of operations included in a method are specifically described, the operations may be performed according to appropriate orders. Also, the use of all example terms (e.g., “such as” and “etc.”) is intended merely to describe the disclosure in detail and does not pose a limitation on the scope of the disclosure unless otherwise claimed.
A field effect transistor 100 includes a substrate 110, a gate electrode 120 provided on the substrate 110, an insulating layer 125 provided on the gate electrode 120, a source electrode 131 provided on the insulating layer 125, a drain electrode 132 provided apart from the source electrode 131, and a channel 135 provided between the source electrode 131 and the drain electrode 132.
The substrate 110 may be an insulating substrate, or may be a semiconductor substrate having an insulating layer formed on a surface thereof. The semiconductor substrate may include, for example, Si, Ge, SiGe, or a Group III-V semiconductor material. The substrate 110 may be, for example, a silicon substrate having silicon oxide formed on a surface thereof, but is not limited thereto.
The channel 135 may include a two-dimensional (2D) material. The 2D material may include graphene, black phosphorus, phosphorene, or transition metal dichalcogenide. The transition metal dichalcogenide may include one transition metal selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb and chalcogen elements selected from the group consisting of S, Se, and Te. The transition metal dichalcogenide may include, for example, one of MoS2, WS2, MoSe2, and WSe2.
A first 2D material electrode bonding layer 136 may be provided adjacent to the source electrode 131, and a second 2D material electrode bonding layer 137 may be provided adjacent to the drain electrode 132. The first 2D material electrode bonding layer 136 may be arranged to face the source electrode 131, and may be arranged in direct contact with the source electrode 131. The second 2D material electrode bonding layer 137 may be arranged to face the drain electrode 132, and may be arranged in direct contact with the source electrode 132. The first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 include a 2D material, wherein the 2D material is the same as described above. The first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 may extend from the channel 135. A first stressor 141 may be provided on the first 2D material electrode bonding layer 136, and a second stressor 142 may be provided on the second 2D material electrode bonding layer 137. Positions of the first stressor 141 and the second stressor 142 are not limited thereto, and the first and second stressors 141 and 142 may be respectively positioned above or below the first and second 2D material electrode bonding layers 136 and 137, or below the source and drain electrodes 131 and 132. The first and second stressors 141 and 142 may include, for example, a material represented by (M1)a(M2)b, wherein M1 may include any one of Mo, W, Hf, Nb, and Si, M2 may include any one of O, S, Se, Te, and N, and 0<a≤3 and 0<b≤3. The first and second stressors 141 and 142 may include chemical reactants of M1 and M2.
Referring to
Because the first and second stressors 141a and 142a are provided on the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a, and not on the channel 135, the channel 135 may be configured to have no strain region. When a strain is applied to the channel 135, because the channel 135 has a large energy bandgap, off-current may increase. Accordingly, no strain is applied to the channel 135.
Meanwhile, as illustrated in
In
Referring to
Referring to
Referring to
The method of manufacturing a field effect transistor according to an example embodiment includes forming the gate electrode 125 on the substrate 110 (S10), forming the insulating layer 125 on the gate electrode 125 (S20), and forming the source electrode 131 and the drain electrode 132 on the insulating layer 125 (S30). Also, the channel 135 may be formed between the source electrode 131 and the drain electrode 132 (S40). A 2D material electrode bonding layer may be formed adjacent to the source electrode 131 and the drain electrode 132 (S50). The first 2D material electrode bonding layer 136 may be formed adjacent to the source electrode 131, and the second 2D material electrode bonding layer 137 may be formed adjacent to the drain electrode 132. The first 2D material electrode bonding layer 136 may be provided in direct contact with the source electrode 131, and the second 2D material electrode bonding layer 137 may be provided in direct contact with the drain electrode 132. However, the present disclosure is not limited thereto, and the first 2D material electrode bonding layer 136 may be provided adjacent to the source electrode 131 without being in direct contact with the source electrode 131, and the second 2D material electrode bonding layer 137 may be provided adjacent to the drain electrode 132 without being in direct contact with the drain electrode 132.
The first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 may extend from the channel 135 to be integrally formed.
Next, a stressor may be formed (S60). The stressor may include a chemically reactive material. The order of forming the stressor may vary depending on a position of the stressor. In
A tensile strain may be applied to the 2D material electrode bonding layer by chemically reacting a stressor (S70). When the stressor is chemically reacted, for example, a MoS2 stressor may be reacted at a temperature of about 330° C. in an oxygen or chalcogen atmosphere to induce volume expansion of the stressor. Referring to
In the method of manufacturing a field effect transistor according to an example embodiment, a stressor may be formed adjacent to a 2D material electrode bonding layer, and a tensile strain may be applied locally to the 2D material electrode bonding layer by oxidizing the stressor. A region to which the tensile strain is applied in the 2D material electrode bonding layer may be selectively controlled according to a position of the stressor and an area of the stressor.
The size of the strain may be controlled by controlling the volume change of the stressor according to the degree of chemical reaction of the stressor. When a tensile strain is applied to the 2D material electrode bonding layer, an effective mass may decrease and carrier density may increase, thereby improving mobility. Accordingly, in the method of manufacturing a field effect transistor according to an example embodiment, a tensile strain is selectively applied to a 2D material electrode bonding layer such that the contact resistance of the 2D material electrode bonding layer may decrease, thereby increasing the conductivity thereof, while no strain is applied to a channel such that an increase in off current in the channel due to strain application may be prevented.
The field effect transistor according to an example embodiment may be applied to various 2D-based devices, and may contribute to improving characteristics of the 2D-based devices by improving the conductivity of a 2D material electrode bonding layer. The field effect transistor according to an example embodiment may be applied to, for example, a logic transistor, a memory selector transistor, a three-dimensional (3D) monolithic transistor, etc. When a strain is applied to a 2D material, the band structure, bandgap, conductivity, and effective mass thereof may increase or decrease according to the strain type, and thus, the conductivity of the material may be controlled.
When a tensile strain is applied to an n-type channel such as MoS2, electron mobility may increase, mobility may be improved by about 9%, and an energy bandgap may decrease. Also, resistance may decrease when the tensile strain is applied. Accordingly, carrier injection may be improved by applying the tensile strain to the 2D material electrode bonding layer, as compared with an unstrained 2D-based field effect transistor.
The size and type of a strain applied to a 2D material may be confirmed through Raman and photoluminescence (PL). When a tensile strain occurs, changes in a Raman peak down shift and peak splitting (in the case of MoS2, an E2g1 peak is a measure) may appear, and a PL peak position and intensity may decrease. In the case of a compressive strain, opposite Raman and PL changes may appear. No strain occurs in the field effect transistor of the comparative example.
The field effect transistor 200 includes a substrate 210, a source electrode 221 provided on the substrate 210, a drain electrode 222 provided apart from the source electrode 221 on the substrate 210, and a channel 225 provided between the source electrode 221 and the drain electrode 222. A first 2D material electrode bonding layer 231a may be provided on the source electrode 221, and a second 2D material electrode bonding layer 232a may be provided on the drain electrode 222. The first 2D material electrode bonding layer 231a and the second 2D material electrode bonding layer 232a may include a tensile strain region. A first stressor 241a may be provided on the first 2D material electrode bonding layer 231a, and a second stressor 242a may be provided on the second 2D material electrode bonding layer 232a. The first stressor 241a and the second stressor 242a may include a material represented by (M1)a(M2)b, wherein M1 may include any one of Mo, W, Hf, Nb, and Si, M2 may include O, S, Se, Te, and N, and 0<a≤3 and 0<b≤3. The first stressor 241a and the second stressor 242a may have an oxidation reaction, nitridation reaction, or chalcogenide reaction structure.
An insulating layer 250 may be provided to cover the first stressor 241a, the second stressor 242a, and the channel 225, and a gate electrode 260 may be provided on the insulating layer 250. The gate electrode 260 may be provided inside the insulating layer 250 or on the insulating layer 250. In the present embodiment, the field effect transistor 200 may be applied in substantially the same manner as the field effect transistor having a bottom gate structure described with reference to
Additionally, in an example embodiment, a field effect transistor may have a double-gate structure.
Referring to
While
The field effect transistor according to an example embodiment has a highly miniaturized size and exhibits excellent electrical performance, and thus is suitable for an integrated circuit (IC) device having a high degree of integration. The field effect transistor according to an example embodiment may constitute a transistor constituting a digital circuit or an analog circuit. In some embodiments, the field effect transistor may be used as a high-voltage transistor or a low-voltage transistor. For example, the field effect transistor according to an example embodiment may constitute a high-voltage transistor constituting a peripheral circuit of a flash memory device, which is a non-volatile memory device operating at a high voltage, or an electrically erasable and programmable read only memory (ROM) (EEPROM) device. Alternatively, the field effect transistor according to an example embodiment may constitute a transistor included in an IC device for a liquid crystal display (LCD) requiring an operating voltage of 10 V or more, for example, an operating voltage of about 20 V to about 30 V, or an IC chip used in a plasma display panel (PDP) requiring an operating voltage of about 100 V.
Referring to
While
Referring to
The CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a p-channel MOS (PMOS) transistor 620 and an n-channel MOS (NMOS) transistor 630 connected between a power terminal Vdd and a ground terminal. The CMOS transistor 610 may include the field effect transistor according to an example embodiment described above with reference to
The CMOS SRAM device 700 includes a pair of driving transistors 710. Each of the pair of driving transistors 710 includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power terminal Vdd and a ground terminal. The CMOS SRAM device 700 may further include a pair of transfer transistors 740. A source of the transfer transistor 740 is cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 constituting the driving transistor 710. The power terminal Vdd is connected to the source of the PMOS transistor 720, and the ground terminal is connected to the source of the NMOS transistor 730. A word line WL may be connected to gates of the pair of transfer transistors 740, and a bit line BL and an inverted bit line may be respectively connected to drains of the pair of transfer transistors 740.
At least one of the driving transistor 710 and the transfer transistor 740 of the CMOS SRAM device 700 may include the field effect transistor according to an example embodiment described above with reference to
The CMOS NAND circuit 800 includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit 800 may include the field effect transistor according to an example embodiment described above with reference to
The electronic apparatus 900 includes a memory 910 and a memory controller 920. The memory controller 920 may control the memory 910 to read data from the memory 910 and/or to write data to the memory 910 in response to a request of a host 930. At least one of the memory 910 and the memory controller 920 may include the field effect transistor according to an example embodiment described above with reference to
The electronic apparatus 1000 may constitute a wireless communication device, or a device capable of transmitting and/or receiving information in a wireless environment. The electronic apparatus 1000 includes a controller 1010, an input/output (I/O) device 1020, a memory 1030, and a wireless interface 1040, which are interconnected through a bus 1050.
The controller 1010 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The I/O device 1020 may include at least one of a keypad, a keyboard, or a display. The memory 1030 may be used to store commands executed by the controller 1010. For example, the memory 1030 may be used to store user data. The electronic apparatus 1000 may use the wireless interface 1040 to transmit/receive data through a wireless communication network. The wireless interface 1040 may include an antenna and/or a wireless transceiver. In some embodiments, the electronic apparatus 1000 may be used for a third generation communication system, for example, code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or a communication interface protocol for the third generation communication system, for example, wide band code division multiple access (WCDMA). The electronic apparatus 1000 may include the field effect transistor according to an example embodiment described above with reference to
The field effect transistor according to an example embodiment may exhibit good electrical performance with a highly miniaturized structure, and thus may be applied to an IC device, and may realize miniaturization, low power, and high performance.
In the field effect transistor according to an example embodiment, the conductivity of a 2D material electrode bonding layer may be increased by applying a tensile strain to the 2D material electrode bonding layer via a stressor. The electronic apparatus according to an example embodiment may be miniaturized and improved in electrical performance by including the field effect transistor. In the method of manufacturing a field effect transistor according to an example embodiment, a tensile strain may be applied to a 2D material electrode bonding layer by oxidizing a stressor to increase a volume thereof.
One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
Number | Date | Country | Kind |
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10-2021-0131974 | Oct 2021 | KR | national |