Patent Grant
8872154
Various embodiments of the present invention pertain to the fabrication of devices including nanotubes, and in particular to electronic devices including semiconducting carbon nanotubes.
With a market that constantly hungers for smaller, faster, and cheaper electronics, the ability for Si transistor technology to continue to satisfy the demands will soon reach its end. Marvelous innovations, such as strained Si, have enabled engineers to continue to shrink Si transistors while maintaining reasonable device performance. However, heat dissipation is becoming a critical problem with advanced electronic chips, and many researchers are looking for salvation to come from the integration of new nanomaterials into transistor technology. Carbon nanotubes (CNTs) are one of the leading candidates for transistor applications. CNTs are nanosized cylinders of a couple of nanometers in diameter with such intriguing features as zero-resistance (ballistic) transport of electric current and an exceptional ability to transfer heat. For these, and many other reasons, CNTs would provide excellent channels for the next generation transistors. However, several obstacles remain to be resolved in the growth and placement of CNTs, and these issues currently hinder the ability to readily integrate them into advanced electronics.
In addition to the transistor, myriad other device applications exist for which CNTs are promising candidates. Their surface atoms, which are arranged in a honeycomb lattice, provide excellent sensitivity to charge-transferring molecules, enabling them to increase the sensitivity in biological sensing applications. The robust electrical properties of CNTs, such as the ability to carry an order of magnitude more current per unit area than copper, make them viable for use in low-power electron emission applications, such as those used to make flat-panel televisions. Integration of CNTs into many other applications, from noise thermometers to antennas, is being actively explored for the unique improvements that are possible when using the intrinsic properties of this nanoscale material.
Various aspects of the present invention pertain to the growth of carbon nanotubes, and including methods for producing fields of carbon nanotubes that are semiconducting. Other aspects pertain to the support of nanotubes of any type within a cavity such as a pore. Yet other aspects pertain to the creation of pores in which nanotubes will be placed.
One aspect of some embodiments pertain to a field effect transistor. The FET can include an insulating material defining a pore. The FET can include a semiconducting carbon nanotube within the pore, the nanotube having two ends. The FET can include a drain in electrical communication with one end of the nanotube. The FET can include a source in electrical communication with the other end of the nanotube. The FET can include a gate surrounding a portion of the nanotube.
Other aspects of some embodiments pertain to a method for fabricating an electronic device. The method can include providing a template of an electrically insulating material, each pore including at least one carbon nanotube. The method can include establishing a common electrical connection each carbon nanotube. The method can include placing a first dielectric material in each pore of the template. The method can include removing a portion of the insulating material and exposing a portion of the first dielectric material. The method can include placing a conducting material around the exposed portions of the first dielectric material. The method can include surrounding the conducting material with a second dielectric material.
Still other aspects of some embodiments pertain to a method for fabricating an electronic device. The method can include providing an electrically insulating substrate. The method can include placing a pattern of electrodes on the substrate. The method can include depositing an electrically insulating material on at least a portion of the electrodes. The method can include removing a portion of the deposited insulating material and exposing an area of an electrode. The method can include depositing aluminum within the exposed area. The method can include anodizing the deposited aluminum and creating a plurality of vertical pores.
One aspect of yet other embodiments pertain to a method for fabricating an electronic device. The method can include providing a first insulating material having a porous array, each pore including a nanotube, each pore having an end proximate to a conductive layer. The method can include placing the insulating material next to a dielectric material. The method can include depositing a first conductive material within each pore and establishing electrical communication between the nanotube and the conductive layer. The method can include depositing a second insulating material on at least a portion of the deposited first conductive material. The method can include depositing a second conductive material on at least a portion of the deposited second insulating material.
Still further aspects of some embodiments pertain to a method for fabricating an electronic device. The method can include providing a substrate comprising an insulating material. The method can include depositing a first layer of a first conductive material on the substrate. The method can include depositing a second layer of a second conductive material on the first layer, the second conductive material being different from the first conductive material. The method can include depositing a third layer of aluminum on the second layer. The method can include anodizing the aluminum and creating a plurality of pores extending from the surface of the alumina towards the second layer. The method can include removing a portion of the second conductive layer between the end of the pore and the first conductive layer.
One aspect of some embodiments pertain to a method for growing nanotubes. The method can include providing a substrate comprising an insulating material. The method can include depositing a first layer of a first conductive material on the substrate. The method can include depositing a second layer of a catalytic material on the first layer. The method can include depositing a third layer of material on the second layer. The method can include coating the third layer with a resist material. The method can include exposing a pattern in the resist material. The method can include etching the exposed pattern and creating a corresponding pattern of pits in the top surface of the third layer. The method can include oxidizing the third material and creating a pore from each pit that extends generally normal to the top surface of the third material. The method can include growing a nanotube within each pore from the catalytic material.
It will be appreciated that the various apparatus and methods described in this summary section, as well as elsewhere in this application, can be expressed as a large number of different combinations and subcombinations. All such useful, novel, and inventive combinations and subcombinations are contemplated herein, it being recognized that the explicit expression of each of these combinations is excessive and unnecessary.
a) is a method for fabricating an electronic device according to one embodiment of the present invention.
b) is a method for fabricating an electronic device according to one embodiment of the present invention.
c) is a method for fabricating an electronic device according to one embodiment of the present invention.
d) is a flowchart representing a method according to one embodiment of the present invention.
e) is a flowchart representing a method according to one embodiment of the present invention.
f) is a flowchart representing a method according to one embodiment of the present invention.
g) is a flowchart representing a method according to one embodiment of the present invention.
h) is a flowchart representing a method according to one embodiment of the present invention.
FIG. 10-9/1 shows a processing act according to another embodiment of the present invention subsequent to that shown in
FIG. 10-10/1 shows schematic representations of the processing method subsequent to that of FIG. 10-9/1. FIG. 10-11/1 shows schematic representations of the processing method subsequent to that of FIG. 10-9/1.
FIG. 10-12/1 shows schematic representations of the processing method subsequent to that of FIG. 10-9/1.
FIG. 10-9/2 shows a processing act according to another embodiment of the present invention subsequent to that shown in
FIG. 10-10/2 shows schematic representations of the processing method subsequent to that of FIG. 10-9/2.
FIG. 10-11/2 shows schematic representations of the processing method subsequent to that of FIG. 10-9/2.
FIG. 10-12/2 shows schematic representations of the processing method subsequent to that of FIG. 10-9/2.
For the purposes of promoting an understanding of the principles of the invention, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated device, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates. At least one embodiment of the present invention will be described and shown, and this application may show and/or describe other embodiments of the present invention. It is understood that any reference to “the invention” is a reference to an embodiment of a family of inventions, with no single embodiment including an apparatus, process, or composition that should be included in all embodiments, unless otherwise stated.
The use of an N-series prefix for an element number (NXX.XX) refers to an element that is the same as the non-prefixed element (XX.XX), except as shown and described thereafter. As an example, an element 1020.1 would be the same as element 20.1, except for those different features of element 1020.1 shown and described. Further, common elements and common features of related elements are drawn in the same manner in different figures, and/or use the same symbology in different figures. As such, it is not necessary to describe the features of 1020.1 and 20.1 that are the same, since these common features are apparent to a person of ordinary skill in the related field of technology. Although various specific quantities (spatial dimensions, temperatures, pressures, times, force, resistance, current, voltage, concentrations, wavelengths, frequencies, heat transfer coefficients, dimensionless parameters, etc.) may be stated herein, such specific quantities are presented as examples only, and further, unless otherwise noted, are approximate values, and should be considered as if the word “about” prefaced each quantity. Further, with discussion pertaining to a specific composition of matter, that description is by example only, and does not limit the applicability of other species of that composition, nor does it limit the applicability of other compositions unrelated to the cited composition.
This application incorporates by reference the following: U.S. patent application Ser. No. 11/747,680, filed May 11, 2007, titled VERTICAL CARBON NANOTUBE DEVICE IN NANOPOROUS TEMPLATES, to inventors Maschmann, Fisher, Sands, and Bashir; U.S. patent application Ser. No. 12/024,635, filed Feb. 1, 2008, entitled CONTACT METALLIZATION OF VERTICAL CARBON NANOTUBES to inventors Franklin, Maschmann, Fisher and Sands; U.S. patent application Ser. No. 12/025,453, filed Feb. 4, 2008, entitled CONTACT METALLIZATION OF CARBON NANOTUBES, to inventors Franklin, Maschmann, Fisher and Sands; and U.S. patent application Ser. No. 12/694,876, filed Jan. 27, 2010, entitled ELECTROCHEMICAL BIOSENSOR, to inventors Claussen, Franklin, Fisher and Porterfield.
In one embodiment of the present invention, a V-CNTFET templated in a single PAA pore includes a vertical SWCNT channel with a SG. The schematic modeling herein depicts various ideal conditions, such as 100% yield of semiconducting SWCNTs at a density of one SWCNT per pore of the PAA template and the ability to independently access all three contacts (gate, source, and drain) for each device. Additionally, each device includes ten SWCNTs, which is a reasonable assumption based on the need in some embodiments for a high enough ON-current to charge and discharge the capacitance of metal interconnects and switch ON other transistors. However, it is understood that these depictions are not limiting on any of the embodiments or claims included herein.
Top contact electrodes (vias) for the gate and drain are assumed to be the same size as that of the top source contact (90000 nm2). In the hexagonal arrangement of the PAA template, the total chip ‘real-estate’ area that this transistor occupies would be 0.27 μm2. Accounting for some needed separation between the electrodes, a 1 cm2 chip would be able to hold roughly 3.5 million of these 0.2 mA ON-current transistors (based on each SWCNT carrying 20 μA of current).
A microwave-generated hydrogen plasma is used to penetrate the bottom oxide barrier in PAA films supported on silicon substrates. A titanium layer between the alumina film and the silicon substrate is incorporated to promote adhesion and to provide a conductive layer for subsequent electrodeposition of Pd. Following the hydrogen plasma treatment, Pd nanowire arrays of controllable length and diameter are synthesized in templates of various pore diameters by utilizing the exposed Ti layer as the working electrode for electrodeposition. Of the reported techniques for penetrating the oxide barrier, the hydrogen plasma treatment process is helpful because it does not significantly widen the pores, does not form voids in the PAA, and provides consistent penetration of the oxide barrier across the template that yields nanowires with a high uniformity in length. Additionally, this process is shown to provide nanowires with ohmic contact to the underlying substrate—this characteristic is convenient for use in conjunction with further fabrication steps for nano-scale devices, such as MPCVD synthesis of CNTs.
The schematic in
In some embodiments of the present invention, vertical SWCNTs (V-SWCNTs) templated in ordered PAA are fabricated. These self-aligned V-SWCNTs are vertical and confined to their nanopores without a lateral extension above the surface. In further emdiments, they have a potential density of 115 SWCNTs/μm2 with a SWCNT-SWCNT spacing of 100 nm. Source and drain contacts are established using electrochemical and physical vapor deposition, respectively. The length of the V-SWCNTs is controlled using simple deposition and/or etching techniques with a variability of ±10 nm. In yet other embodiments, nanoscale length SWCNT devices are realized without the need for lithographic patterning of the SWCNTs. In yet other embodiments, planar FETs are fabricated that demonstrate
Nanostructures according to various embodiments of the present invention such as nanowires and nanotubes enable good performance for field-effect transistors (FETs), including decreased gate delay, enhanced mobility, lower power operation, and greater opportunity to scale channel length. Single-walled carbon nanotubes (SWCNTs), which structurally are rolled graphene sheets with no edge states and diameters ranging from 1 to 3 nm, exhibit excellent 1D electrostatics that allow for the good channel length scaling among nanomaterials considered for nanoelectronic applications. Some embodiments of the present invention include a surround (i.e., coaxial, annular, wrap-around) gate to obtain optimal control over the energy bands in the nanotube channel. Vertical SWCNTs (V-SWCNTs) that are free-standing and supported in a template can access to the nanotube for applying a surrounding dielectric and metal gate as well as control over device placement and channel length. Various embodiments of the present invention include the fabrication of surrounding dielectrics and gates on nanotubes along with a facile means for controlling the device channel length. An inert gas ion bombardment etch is used to define the final channel length to within a narrow range (±15 nm) over an chip and in a single step, thus eliminating or reducing any need for complex and expensive lithography. The combination of surround gates on V-SWCNTs and a method for scaling the channel length at the wafer-level provides a platform for realizing CNTFETs 1D electrostatics.
Various embodiments of the present invention pertain to apparatus and methods for fabricating electron devices, such as field effect transistors. However, it is understood that the apparatus and methods described herein are not so limited, and other embodiments contemplate fabrication devices other than FETs.
This document provides detailed description of the apparatus and methods used in a variety of different embodiments. However, before providing detailed descriptions,
a) shows a method 100 for fabricating a portion of an electronic device such as a field effect transistor. The method includes act 101 in which a plurality of metal film stacks are placed within a matrix of insulating materials. In some embodiments, the metal film stacks are layers of electrical conductor, CNT catalysts and insulator. In some embodiments, the layers of insulating material are first deposited in metallic form, and later oxidized to a configuration that includes pores. In some embodiments, the metal stacks are placed within an insulating matrix such as silicon or silicon dioxide.
Method 100 further includes the act of creating a plurality of ordered, vertical pores within each stack. It is understood that the term “vertical” refers to a pore extending lengthwise and substantially normal from an outer surface. In some embodiments, the pores are created during the oxidation process. In yet other embodiments, the pores can be etched by other methods described herein, and yet other methods known to those of ordinary skill in the art.
Method 100 further includes the act 103 of growing a nanotube within each pore. Preferably, the pore extends within the film stack and exposes a ring of catalytic material on the inner surface of the pore. For those embodiments in which a transistor is being fabricated, the nanotube is preferably semiconducting in nature and further is a carbon nanotube. However, other embodiments of the present invention contemplate semiconducting tubes other than those fabricated from carbon, and in those embodiments not pertaining to field effect devices the carbon nanotube may be of any chirality, and further need not be fabricated from carbon.
Method 100 further includes the act 104 of establishing electrical communication among the ends of the nanotubes within the pores. This electrical communication can be established from a nanotube to a respective conducting layer within the film stack. In some embodiments a nanowire is deposited within each pore to establish electrical communication from the end of the nanotube to the common electrical plane.
Method 100 further includes the deposition of an insulator within each pore. This insulator preferably surrounds the nanotube and centers the nanotube. Further, some embodiments include the deposition of a material with good wetting properties, such that the material can wick into the nanopores.
Method 100 further includes the act 107 of removing the material surrounding the filled pores, so as to create an array of substantially vertical pillars extending from the film stack. Each pillar contains a nanotube.
Method 100 further includes the act 108 of depositing a gate material around a portion of the pillars. A current later flowing through the gate material provides the electromagnetic field that effects the semiconducting properties of the nanotube within the pillar.
b) shows a method 100/1 for further processing that can be performed on the structure resulting from act 108. Method 100/1 includes the act 110/1 of the depositing insulating material around the pillars and their respective gates. Method 100/1 further includes the act 111 of removing the top surface of the stack and exposing the ends of the nanotubes. A subsequent act 112 establishes a common electrical plan (such as the drain for an FET) on top of the exposed nanotube ends. Further, electrical contact with the gates is established with a third electrical plane.
c) shows a method 200 for creating an electronic device, such as a field effect transistor. Method 200 includes the acts 201 of depositing a layered metal stack. Preferably, the stack includes a layer that would act as a common electrical plane, and yet another layer that will serve as a catalyst for the creation of nanotubes. It is contemplated that acts 201 and 101 can both pertain to placing one or more metal stacks within an insulating matrix, or can pertain to a stack not contained in an insulating matrix.
Method 200 further includes an act 202 of creating an ordered array of surface defects on the top surface of the layered stack. These surface defects, in some embodiments, are nanodimples on the top surface created by photolithography, electron beam lithography, or other methods known in the art. Method 200 further includes the act 203 of creating a pore extending from the surface defect into the stack in a direction substantially normal to the surface. These pores in some embodiments are created by an oxidation process acting on the top layer of metal film, and in yet other embodiments the pores are created by a method such as EBL.
Method 200 further includes the act 204 of growing a carbon nanotube within the pore, similar to act 103 previously discussed. Method 200 further includes an act 205 similar to act 104 discussed previously.
Method 200 further includes the deposition of an insulating material within each pore, act 206, which is similar to act 105 discussed earlier.
Method 200 further includes the act 207 of removing nanotubes from some of the pores, as will be discussed later.
Act 208 includes removing a portion of the film material surrounding the filled pores and creating a plurality of substantially vertical pillars. Act 208 includes depositing gate material around each pillar, and act 210 pertains to the deposition of electrodes, including for the drain and gate.
The present invention includes a method 1000 similar to method 100, but providing specific examples. Further, described herein is a method 1000/1 that is similar to method 100/1, except providing specific examples. Yet other embodiments of the present invention are represented by method 2000, which are similar to method 200, except providing specific examples.
Various other embodiments of the inventions shown herein pertain to fabrication of field effect transistors arranged vertically within pores of an insulating material. An overview of a method 1000 is depicted in the flowchart of
The flowchart of
A flowchart of a method 1002 that is an alternative to method 1001 is shown in
g) is a flowchart for a method 2000 for fabricating field effect transistors with vertically aligned carbon nanotubes.
h) is a flowchart for a method of preparing field effect transistors, especially in those embodiments using method 2000. Method 2001 includes acts 2080 thru 2140, which correspond to
PAA is formed by anodic oxidation of Al in an acidic electrolyte. The Al is in some embodiments either a foil that is several tens of microns thick or a substrate-supported thin-film. The resulting alumina template includes vertical pores in a naturally occurring hexagonal arrangement. The pore diameter is linearly dependent on the anodization electrolyte and voltage—demonstrated pore diameter ranges from sub-10 nm to several hundred nanometers.
When synthesizing MWCNTs in PAA without a catalyst, the main formation mechanism is the adsorption of carbon on the alumina pore walls by the decomposition of hydrocarbons, and this process yields tubes of low crystalline quality. Reported MWCNT synthesis methods utilizing a catalyst yield MWCNTs that take on the diameter of the pores and in some embodiments have a high concentration of disordered carbon. However, in order to fabricate CNTFETs the channel CNT should be semiconducting, which MWCNTs are not.
It is in some embodiments more difficult to achieve SWCNT synthesis from customized templates or catalysts because of their relatively high activation energy in comparison to MWCNTs. Additionally, nucleation of SWCNTs can include catalyst particles of diameters less than a few nanometers. These two obstacles of high activation energy and difficult catalyst particle size-control are overcome in some embodiments work by burying a catalyst (such as iron) layer in a PAA template and synthesizing in a high temperature microwave plasma-enhanced chemical vapor deposition (MPCVD) environment. The plasma helps to lower the required thermal activation energy by providing a separate means for dissociating the hydrocarbon precursors, thus relieving part of the energy burden from the catalyst particle. Secondly, covering Fe with a thin layer (few nanometers) of alumina raises the surface diffusion barrier of the catalytic Fe particles and thus keeps them from agglomerating.
The catalytically active PAA template is formed by first depositing a Ti/Al/Fe/AI film stack on a SiO2 covered Si wafer, as shown in
Synthesis of the SWCNTs from the catalytically active PAA is accomplished in a hydrogen-supported MPCVD with methane as the hydrocarbon precursor gas. Observations to date indicate that only one SWCNT nucleates in any given pore, likely because of the limited gaseous-carbon supply and the relatively high activation energy required for nucleation. After nucleating at the sidewall of a pore, the SWCNT proceeds to grow vertically to the surface of the PAA, towards the carbon supply. Evidence of this vertical growth is seen in cross-sectional field-emission scanning electron microscope (SEM) images showing freestanding, vertical SWCNTs, as shown in
Several other pre-synthesis processes can affect the SWCNT yield. First, in order to use the SWCNTs grown in the PAA for active devices, it is desirable to achieve the highest possible yield of SWCNTs. Variations in the catalyst layer thickness revealed that thick (greater than 2 nm) or thin (less than 0.5 nm) layers decreased the SWCNT yield. Pre-anodization thermal annealing provides an increase in the yield upon thermally annealing the metal film stack in air for 20 min at 450° C.
If nominal catalyst layer thickness is small (1 nm), it can be difficult to determine the uniformity of the Fe film on the Al. When less than 1 nm of Fe is deposited as the catalyst for the PAA/SWCNT template, the SWCNTs can grow from select regions of the sample as shown in
Two factors in SWCNT yield appear to be the catalyst layer thickness (which should be kept around 1 nm for optimal particle size) and the catalyst layer uniformity (which likely increases with increasing catalyst layer thickness). In order to balance these two competing factors, multiple catalyst layers were deposited with a vertical separation of approximately 2 nm of Al. Because confinement of the Fe nanoparticles in the alumina enhances SWCNT yield, separating the catalyst layers by a thin Al layer ensures that all catalyst is incorporated with the alumina formation during anodization, yet retains its deposited thickness. The deposition of each separate catalyst layer will yield a new random dispersion of Fe patches (
Other post-deposition processes can affect the SWCNT yield. One process involving PAA is an alumina etch in dilute phosphoric acid (0.1 M) to widen the pores. Pore-widening also helps to thin the intrinsic alumina barrier at the pore bottoms—the barrier hinders access to an underlying conductive layer that can be used for electrochemical post-processing. Introduction of a brief pore-widening etch on the catalyst-embedded PAA template may decrease SWCNT yield. The SEM images in
In some embodiments of the present invention it would be helpful to have the PAA positioned next to a planar insulator for use in functionalizing devices. However, one difficulty with forming PAA within an insulator is the expansion of the Al when oxidizing to form Al2O3. In some embodiments a sequence of dry and wet etching of SiO2 can provide enough space to account for this film expansion. The process involves the simple etching of lithographically defined trenches into SiO2 followed by metal deposition and finally anodization.
a, b) illustrates the process for obtaining trenches of PAA. Beginning with a Si substrate having a 1 μm thick thermal oxide, the desired dimensions of the trenches are lithographically patterned. In the present case, the trenches ranged in width from 3 to 500 μm. Preferably all of the trenches meet at a common top electrode that will be used for anodization. Once the photoresist is patterned, it is used as an etch mask for removing the desired amount of SiO2 to form the trenches. The depth of the trenches should be well calibrated to the desired PAA film thickness. Using a reactive ion etch (RIE) process, 500 nm of SiO2 was removed for these experiments. Following the RIE, the SiO2 was etched isotropically in a 6:1 buffered oxide etch (BOE) for 30 s. This BOE etch accounts for the film expansion during anodization. After etching, 100 nm Ti, 100 nm Al, 1 nm Fe, and 300 nm Al are sequentially evaporated onto the sample. A two-hour soak in acetone is used to lift-off the photoresist, resulting in the structure shown in
After anodization, SWCNTs were synthesized from the embedded Fe in the PAA using the MPCVD process outlined above. The SEM images in
The procedure developed for fabricating electrically isolated fields of PAA is similar to that used for PAA trenches and is illustrated in
Another lithography step defines the fields (in this case, squares) along the branch electrodes that remain covered by the PCVD SiO2. The SiO2 is dry-etched in a reactive ion etcher using CF4 as the active etching gas. The RIE process provides highly anisotropic removal of the SiO2, and is followed by a brief (≈30 s) wet etch in BOE. The BOE etch serves the purposes of removing contaminants remaining from the RIE and of undercutting the photoresist to minimize the effects of expansion in the Al film as it anodizes to form PAA. Using the same patterned photoresist, a metal film stack of 50 nm Ti, 100 nm Al, 1.2 nm Fe, and 300 nm Al is thermally evaporated and subsequently lifted off.
By briefly wet-etching the PCVD-deposited SiO2 prior to depositing the Al film stack, some effects of volume expansion of the film during formation of the PAA are significantly reduced. The BOE, being an isotropic etchant, undercuts the photoresist to provide space for the film to expand during anodization. The SEM image in
One aspect of using Ti/Pt electrodes buried beneath 500 nm of SiO2 is that the Pt surface is visible in both optical and electron microscopy, enabling alignment to the electrodes when defining patterns within which the PAA is formed.
d) shows SWCNTs extending across the interface between the PAA and SiO2. Restricting the PAA to these embedded fields provides a way to estimate the density of SWCNT growth from PAA. Overall, this process for embedding independently addressable fields of PAA within SiO2 provides a method for initially fabricating and interconnecting the V-CNTFETs. The SiO2 support provides ample area for contact pads to be defined for accessing the Ti/Pt source contact to the nanowires and the eventual gate electrode to the SWCNT channels.
While PAA pore patterns naturally tend toward hexagonal arrangements, the nucleation of the pores at random sites of the Al surface creates the need for long anodization times on thick Al foils to allow the pores to take on their hexagonal arrangement (because of the compressive stress in the template during formation). Consequently, the use of thin-film PAA has traditionally been less common than that of PAA foils. However, because the pores will have a tendency to nucleate at defect sites on the Al surface, methods have been developed for creating ordered defects, which are simply dimples, in the Al surface prior to anodization. Of these methods, few have been developed for dimpling thin-film Al, perhaps because of the surface roughness of most deposited Al films and the inability to apply high pressures to the Al surface using stamps or molds as can be done with Al foils. Processes for dimpling thin-film Al have included the use of a focused ion beam (FIB) to mill dimples into the Al, but the FIB processing is generally not scalable to the wafer level. Some embodiments presented herein use electron-beam lithography (EBL) and wet Al-etching is used to create large regions of ordered, thin-film PAA. However, other embodiments of the present invention are not so constrained and contemplate these other methods for creating the PAA pattern.
One act in creating large regions of ordered, thin-film PAA is to pattern a resist layer using EBL. In designing the pattern to be written, it is helpful that the holes are spaced the proper distance apart and that they do not merge together. The settings for writing patterns with 100 nm spacing for one embodiment were determined to be: a beam current of 500 pA, beam step size of 2 nm, resolution of 2 nm, and dose of 8000 μC/cm2. After the sample is exposed, the pattern is developed with constant agitation for 90 s in MIBK developer diluted 1:3 with isopropanol. After the pattern has been fully exposed and fully developed, the sample will now be at the stage depicted by the schematic in
A commercial Al etchant (a phosphoric acid mixture, from Transene Company) is used to etch the Al at room temperature. The sample is held vertically and agitated from side-to-side to ensure that the etchant proceeds to the Al surface through the patterned PMMA. A 20 s etch is sufficient to transfer the pattern to the Al surface in the form of dimples, as illustrated in
Anodization of the now dimpled Al surface causes pores to nucleate from the dimples and thus begin with a hexagonally arranged template and the designed pore-to-pore pitch. For an inner-pore spacing of 100 nm, the anodization voltage is 40 V in 0.3 M oxalic acid. SEM images of patterned PMMA, a dimpled Al surface, and ordered pores after anodization are shown in
A microwave-generated hydrogen plasma is used to penetrate the bottom oxide barrier in PAA films supported on silicon substrates. A titanium layer between the alumina film and the silicon substrate is incorporated to promote adhesion and to provide a conductive layer for subsequent electrodeposition of Pd. Following the hydrogen plasma treatment, Pd nanowire arrays of controllable length and diameter are synthesized in templates of various pore diameters by utilizing the exposed Ti layer as the working electrode for electrodeposition. Of the reported techniques for penetrating the oxide barrier, the hydrogen plasma treatment process is helpful because it does not significantly widen the pores, does not form voids in the PAA, and provides consistent penetration of the oxide barrier across the template that yields nanowires with a high uniformity in length. Additionally, this process is shown to provide nanowires with ohmic contact to the underlying substrate—this characteristic is convenient for use in conjunction with further fabrication steps for nano-scale devices, such as MPCVD synthesis of CNTs.
One aspect of using PAA to template devices on pre-functionalized substrates is the presence of an intrinsic alumina barrier at pore bottoms (
Electron-beam evaporation at a base pressure of 5×10−7 torr was used to deposit 50 nm SiOx, 150 nm Ti, and 1500 nm Al, respectively, on a thermally oxidized silicon substrate. Anodization of the Al to form PAA was performed using three electrolytes: 0.3 M H2SO4 (sulfuric acid), 0.3 M H2SO4 (oxalic acid), and 0.3 M H3PO4 (phosphoric acid). Anodization employing sulfuric acid yielded the smallest pores (5-10 nm), while oxalic acid and phosphoric acid anodization yielded pore diameters of 20-30 nm and 100-130 nm, respectively. Anodization voltages were 18 V for sulfuric acid, 40 V for oxalic acid, and 100 V for phosphoric acid. All acid electrolytes were maintained at a temperature of 5° C. during anodization. Some of the structures anodized in sulfuric and oxalic acids were immersed in 0.1 M H3PO4 solution following anodization to widen the pores slightly. To obtain highly ordered pores with thin Al films, multiple anodization steps were employed. Following the initial anodization steps, the PAA was removed by immersion in a mixture of diluted chromic and phosphoric acids, leaving the remaining Al imprinted with the pore structure of the removed PAA to serve as initiation sites for subsequent anodization steps. The samples were anodized in two or three-step processes.
Hydrogen plasma treatments were performed in a MPCVD chamber. The plasma power was maintained at 300 W at a pressure of 10 torr and a hydrogen flow rate of 50 sccm. Plasma treatments were performed for 10 minutes with the substrate maintained at a constant temperature of 900° C. using inductive heating. Treatments were also performed at room temperature to study the effect of a lower temperature environment on the penetration of the oxide barrier. Samples were cooled to room temperature in a 3 torr hydrogen ambient prior to removal from the chamber.
Electrodeposition of Pd into the PAA structures was accomplished using a three-electrode system comprised of a platinum gauze auxiliary electrode, a silver/silver chloride reference electrode, and the Ti layer beneath the PAA as the working electrode. Pd nanowires were deposited using a solution of PdCl2 (0.0067 g PdCl2, 0.2 mL HCl, 20 mL DI H2O) in a cyclical chronopotentiometry process using a BAS Epsilon system. A constant current was established between the auxiliary and working electrodes, while the potential of the working electrode was monitored with respect to the reference electrode. For all experiments, a constant current density of 1.5 mA/cm2 was applied in cycles of 500 ms duration, during which the monitored voltage ranged from 0.0887 V to 0.2081 V. To control the length of Pd nanowires, the number of cycles was varied. Following the electrodeposition of Pd, samples were characterized using a Hitachi S-4800 field-emission scanning electron microscope (SEM). Pd nanowires created in a template anodized in oxalic acid at 40 V (without subsequent pore widening) were released by removing the PAA using a NaOH mixture. These nanowires were subsequently imaged using the scanning transmission electron microscope mode of the aforementioned SEM.
The incorporation of pore widening by many reported methods for penetrating the oxide barrier limits the minimum nanowire diameter and porosity. This excessive pore widening also places the nanowires in close proximity to each other, thereby greatly limiting the ability to integrate the array into a device structure. Treating the PAA film in a hydrogen plasma did not significantly affect pore diameters. This anisotropic result allows for the fabrication of nanowire arrays in PAA templates of a wide range of diameters. From our results, templates were created with pores of diameters as small as 10 nm and as large as 130 nm. Within each template, nanowires were successfully synthesized.
As shown in the SEM images of
A hydrogen plasma treatment was performed with the substrate at two different temperatures (32° C. and 900° C.), as recorded from an embedded thermocouple beneath the substrate. For both temperatures used, the oxide barrier was sufficiently penetrated to allow for electrodeposition of Pd; however, samples treated at the higher temperature (900° C.) produced a more uniform penetration of the barrier. The length of the nanowires in 130 nm diameter pores of a sample treated at 32° C. had a standard deviation of 32%, compared to a similar sample treated at 900° C. with only a 2% standard deviation. The higher temperature may provide a more uniform reduction reaction rate with the alumina bottom oxide barrier. Additionally, heating the PAA to such a high temperature in a hydrogen ambient could, in and of itself, provide favorable conditions for a reduction of the oxide barrier.
After plasma treatment, the oxide barrier is still visible in most PAA structures with larger diameter pores (and thus thicker oxide barriers) when the samples are fractured for SEM imaging, as in
In order to use the Pd nanowires as electrodes in nanoscale devices, or for any other in situ device functionalization, electrical contact between the nanowires and the underlying substrate should be confirmed. Verification of electrical contact between the Pd nanowires and the Ti layer was obtained from three samples (anodized in oxalic acid at 40 V, sulfuric acid at 18 V, and phosphoric acid at 100 V) that were intentionally overfilled with Pd, thereby electroplating the top PAA surface. I-V characteristics were obtained between the Pd plated on the PAA top surface and the bottom Ti layer that was exposed approximately 3 mm away. Measurements were also obtained from a PAA template that was not completely overfilled by nanowires, and this sample exhibited no measurable conduction. For all three overfilled samples, ohmic contact between the Pd nanowires and the Ti layer was observed (
PAA templates were fabricated previously. A metal film stack of Ti/Al/Fe/Al/Fe/Al (100 nm/150 nm/1 nm/2 nm/1 nm/350 nm) was electron-beam evaporated at a base pressure of 5.0×10−7 torr. Each sample was anodized at 40 V in 0.3 M oxalic acid maintained at 5° C., yielding pores with an average diameter of 20 nm. In one step, SWCNTs were synthesized from the embedded Fe catalyst (exposed on the inner-sidewalls of the vertical PAA pores) and the alumina barrier was penetrated to partially expose the Ti at each pore bottom using hydrogen-supported microwave plasma-enhanced chemical vapor deposition (MPCVD).
Using a BAS Epsilon Electrochemical System, Pd was galvanostatically electrodeposited into the PAA/SWCNT templates. As shown in
During the electrodeposition of Pd to form nanowires in the PAA, it is helpful to be able to distinguish when the nanowire front has reached the elevated catalyst layer within the pores and thus contacted the SWCNTs. If deposition continues past the point of nanowire/SWCNT contact, the nanowires will continue to grow, filling the remainder of the pore channels until, eventually, they will protrude from the PAA and Pd will electroplate the surface. In order to fit in a process flow for vertical SWCNT devices in some embodiments, the vertical channel regions should be as consistent in length as possible, which means that the extension of the nanowires past their contact to the SWCNTs should be limited. In addition to the continued growth of the nanowires, Pd nanocubes also begin to form on the SWCNTs when deposition continues past the point of nanowire/SWCNT contact.
Electrodepositions in one embodiment were performed by applying 0.5 s pulses of constant current between the auxiliary and working electrodes while monitoring the potential between the reference and working electrodes.
Cyclic voltammograms (CVs) are in some embodiments very useful in investigating deposition mechanisms; however, CVs could not provide data to understand the present system that involves the gradual change of composition and nature of the working electrode (e.g., Ti, Pd, and SWCNTs) over time. One metric for analyzing the time-dependent changes at the working electrode during electrodeposition is the steady-state potential (or the final potential) from each pulse as a function of deposition time.
Plots of the steady-state potential versus deposition time for several 2.0 mA/cm2 depositions are shown in
In some embodiments it is preferred that the current density for forming Pd nanocubes is one that is large enough to enable Pd nanowire nucleation and growth from each pore bottom yet small enough to obtain nanocubes without rough surfaces. Electrodeposition at current densities below 1.0 mA/cm2 greatly reduces the nanowire density; current densities above 3.0 mA/cm2 produce nanocubes with rough and spiky surfaces as well as increased nucleation on many SWCNTs. Therefore, the current density was varied between 1.0 and 3.0 mA/cm2, and the plots of the steady-state potential as a function of deposition time are shown in
After adding the SWCNTs to the working electrode, a deposition pulse causes Pd2+ to reduce at their surfaces.
Some embodiments of the present invention pertain to methods in which the Pd deposits have a selective and distinct shape. A combination of mechanisms could be contributing to the formation of Pd crystals with well-defined cubic shapes. First, equilibrium Pd nucleates in truncated octahedral shapes with {100} and {111} facets. It appears that Cl− ions in the deposition solution serve as additives that selectively adsorb on the {100} planes, enhancing the stability of these planes. This preferential adsorption reduces the crystal growth rate along the <100> direction and makes {100} planes gain in area while other planes, with relatively faster growth rates along their normal directions, grow out of existence in the final morphology, resulting in cubic shapes.
Secondly, the SWCNTs here are supported on PAA instead of a planar insulator (such as SiO2), and the lack of intimate contact between the SWCNTs and the PAA surface would allow the nanocubes to drift freely in the electrolyte, being tethered by SWCNTs that are bound only at one end by their nucleation sites within the pores. Therefore, the SWCNTs can be fully exposed to the solution for Pd deposition. Combined with the relatively low nucleation density of Pd on the SWCNTs, the fully exposed SWCNT surface allows each Pd nucleus to build a spherical diffusion layer around it, which promotes isotropic and uniform growth of cubic Pd crystals.
Another factor that may contribute to the tendency toward cubic shapes is the lack of post-synthesis processing of the SWCNTs. SWCNTs are transferred directly from the MPCVD synthesis chamber to the electrolyte for electrodeposition, allowing the SWCNTs to maintain, as nearly as possible, their as-grown characteristics.
After initial Pd nucleation to the SWCNTs further pulses cause reduction at the Pd nanocube surface at a mass-transfer rate proportional to the applied current density. Therefore, it is expected that higher current densities will yield nanoparticles with less stable morphologies having rough and patchy surfaces, as is evident with the nanocube in
The increasing size of the nanocubes in
One observation is the presence of Pd nanocubes on the SWCNTs before the Pd nanowires have contacted the SWCNTs, as shown in
Few of the SWCNTs hosted spontaneous Pd nanocube formations, and the SWCNTs that did were the brightest when viewed in the SEM. It is possible that the brighter SWCNTs on the insulating PAA surface are metallic while those that are dark are semiconducting.
In scanning electron microscopy, conductors appear bright compared to insulators because of the ease with which secondary electrons can be emitted from them. When imaging SWCNTs on PAA, prior to any post-synthesis processing, a portion of the SWCNTs appear bright while the rest are darker as shown in
In the experiments performed by Brintlinger et al., as with most other reports of SWCNTs imaged using SEM, the SWCNTs were supported on a planar SiO2 substrate. Furthermore, Brintlinger et al. observed a decrease in contrast and overall visibility of the SWCNTs for accelerating voltages greater than 2 kV and/or slow scan speeds; in comparison, the images shown herein used a 5 kV accelerating voltage and observed an increase in the contrast with increasing voltage as well as with slower scan speeds. Notably, low-magnification SEM images show that approximately one-third of the SWCNTs on the PAA are bright (see
The process for obtaining highly ordered PAA thin films and subsequently synthesizing V-SWCNTs within the nanopores is and illustrated in
After development, the hexagonal pattern is transferred to the Al surface by a 25 s wet etch using Transene Al-Etchant Type A at room temperature with moderate agitation. The resulting pits in the Al surface, seen in
Microwave plasma-enhanced chemical vapor deposition (MPCVD) was subsequently used to synthesize the SWCNTs, which nucleate at the embedded Fe layer within the pores and grow vertically to the PAA surface with a yield of one SWCNT per pore. The density of SWCNTs in the present templates was kept low by growing for times of 1 min or less in order to facilitate the testing of single (or few) nanotube devices per 100 μm2 contact area. The portions of the SWCNTs that protrude from the pores are removed in a subsequent etch to leave the vertical channels of V-SWCNTs within the nanopores.
The spacing between nanopores in the hexagonally arranged template is 100 nm, which yields a potential V-SWCNT density of 115 SWCNTs/μm2. Source contacts to the V-SWCNTs were made by electrochemically depositing Pd nanowires within the PAA pore bottoms as described previously. The standard deviation in the length of these nanowires is 4% or less than 10 nm in the present case. A spin-on glass (SOG) dielectric (Honeywell 214) was then applied at 6000 rpm for 30 s followed by a 450° C. cure in N2 for one hour to support each V-SWCNT within its respective pore. The SOG fills the pores, provides a passivating dielectric support of the V-SWCNTs, and forms a planar layer on the PAA surface that is ≈180 nm thick.
Removal of this surface SOG was accomplished using an inductively coupled plasma reactive ion etcher (ICP-RIE). An inert gas plasma was supported by 60 sccm Ar at 1 mlorr and 300 W of coil power while the Ar ions were accelerated to the sample surface with an 800 W platen bias power. The resulting ion bombardment etch removes the 180 nm of surface SOG, along with the portions of the SWCNTs that extended along the PAA surface in 80 s. Continued ion bombardment etching past 80 s removes the PAA/V-SWCNT template at a vertical rate of 40 nm/min as determined from 42 etching trials with different etching times. After the etch, the top of the SOG within the nanopores is relatively level with the PAA surface. A further act in fabrication is the evaporation of 8 nm Pd/20 nm Ti/60 nm Au top contacts of various lithographically-defined sizes completes the fabrication of vertical two-terminal devices.
a) illustrates the final SWCNT length (LCNT) in these devices, which is defined from the top of the Pd nanowire source contact to the top of the PAA template. LCNT has been controlled by a combination of the initial top Al layer thickness (300 nm in the present case) and the ion bombardment etch time on the PAA/V-SWCNT template. The accuracy of controlling LCNT from device to device by the top Al thickness depends on the uniformity of the Al film. The roughness of the Al film is determined by the deposition process, which was thermal evaporation in this case with a surface roughness around 40 nm, as determined from cross-sectional field-emission scanning electron microscope (SEM) images of the deposited film. Control of the length from sample to sample by varying the initial Al thickness can be accomplished with reasonable accuracy preferably by taking into account expansion.
The ion bombardment etch yields very accurate control over the V-SWCNT length as compared to simply varying the Al thickness. The etch rate of the surface SOG (2.25 nm/s) is more than three times faster than the etch rate of the PAA/V-SWCNTs (0.67 nm/s). This rate difference enables close control in defining the V-SWCNT length. As seen in the SEM image of
Electrical characteristics from a two-terminal V-SWCNT device consisting of one metallic and one semiconducting nanotube are given in
With a V-SWCNT length below 300 nm (close to the mean free path for acoustic phonon scattering), a generally defect-free, metallic nanotube should be ballistic and exhibit a low-bias conductance near the theoretical limit of 4 q2/h (154.8 μS). The substantially lower conductance observed here is attributed to the series and contact resistances in the device. The low conductance of the semiconducting V-SWCNT is attributed to the normally-OFF nature of semiconducting nanotubes in terms of band positions under no gate bias (illustrated in
Qualitative band diagrams for a possible configuration of the semiconducting device are shown in
Templated, V-SWCNTs have several aspects in nanoelectronic applications. First, the V-SWCNT length can be scaled down without the use of lithography. Variation of the ICP-RIE ion bombardment etch time (a rate of about 40 nm/min) provides control over LCNT, which in the context of fabricating CNTFETs would serve as the device's channel length.
Another aspect of the V-SWCNT structure is the ability to obtain individual channels of V-SWCNTs that are wrapped in a dielectric (SOG in this case). While SOG was used as a dielectric support for the nanotubes herein, the V-SWCNTs could alternatively be coated with a high-x dielectric using atomic layer deposition (ALD). When fabricating multi-nanotube devices for interconnects or FETs, the individual channels of V-SWCNTs will minimize deleterious charge screening between nanotubes that other configurations encounter as the nanotubes become more closely packed and bundled. In some embodiments density of nanotubes in the V-SWCNT templates is an order of magnitude greater than some densities reported to date for planar configurations. Other aspects include the ability to use these V-SWCNT templates for fabricating surround-gated CNTFETs, creating ordered arrays of V-SWCNTs of adjustable density, or even using the V-SWCNT tips as probes for biological interfacing.
To provide additional verification of the presence of semiconducting nanotubes in the V-SWCNT templates, planar CNTFETs were fabricated from the nanotubes. On the Each field of PAA was surrounded by a region of 200 nm-thick SiO2 using a process reported in previously. The SWCNTs were grown for a longer time (15 min as opposed to 1 min for low density growth), which caused them to extend out of their pores and along the PAA surface (see
The final devices had long channels (3 μm), which caused them to operate in the diffusive transport regime. However, these devices were sufficient for identifying the semiconducting nature of the SWCNTs by use of the back gate.
The screening length (λ) is an intrinsic property of a device configuration that represents the natural length over which potential is dropped between two electrically different materials (e.g., p-n or metal-semiconductor junctions). A similar intrinsic length often introduced in bulk semiconductor electrostatics is the Debye length, which traditionally represents some factor of the depletion width of a p-n junction in thermal equilibrium for a semiconductor with a particular doping level. The Debye length is a device parameter that depends on doping and temperature, while the screening length is an intrinsic parameter that depends only on dielectric/channel properties and thicknesses. For nanoscale devices, the smaller of these two lengths will determine the distance over which the bands bend—for thin body devices (e.g., nanowires or nanotubes) the doping would have to be high to render a Debye length shorter than λ.
In nanoelectronic devices according to some embodiments, λ offers a metric for determining how aggressively a device's channel length can be scaled down without incurring short-channel effects, such as high leakage currents and drain-induced barrier lowering (DIBL). One proposed rule-of-thumb according to some embodiments for scaling nanoelectronics is to keep the channel length greater than 3λ in order to maintain long-channel device behavior.
In equation 7.1, ∈ox is the dielectric constant of the gate dielectric, ∈body is the dielectric constant of the channel material (nanotube or nanowire), dox is the gate dielectric thickness, and dbody is the thickness (diameter) of the nanomaterial.
A schematic for a SG CNTFET is shown in
To achieve the structure shown in
A V-SWCNT supported in its own channel with the SOG dielectric can have the PAA be selectively etched back to expose these rigid dielectric pillars, which serve to template the SG formation. As In a solution of chromic acid at 65° C., the PAA is etched back at a rate of approximately 10 nm/min. This slow etch rate provides the ability to accurately define the portion of the source-to-drain channel length that is to be gated for the device. Once the PAA has been etched back (see
Another act to completing the SG V-SWCNTs begins with applying another SOG layer using the same process employed to fill the pores initially. This final SOG layer acts as a support for the SG pillars and allows the final gated channel length to be defined. After application and curing, the SOG is etched back using the same Ar ion bombardment process described above. This time, the ion etch is continued until the cylindrical Al gate metal is exposed as shown in
Results of selectively etching back the PAA to expose the V-SWCNTs wrapped in the rigid dielectric pillars are given in the SEM images of
Fad=2πRWad (7.3)
where R is the radius of the pillar and Wad is the work of adhesion of the SOG. The elastic force generated by bending a pillar of stiffness kb (kb=3πR4E/4l3) over a displacement δ is
where l is the length of the pillars and E is the Young's modulus of the SOG.
In order to prevent the pillars from adhering to each other, the elastic force should be greater than the adhesion force. Solving the inequality between equations 7.3 and 7.4, the maximum length of the pillars before they agglomerate is
where S=2δ is the spacing between the pillars. Assuming a Young's modulus of 20 GPa (approximately one-third that of SiO2) and work of adhesion of 0.12 N/m, the maximum pillar length (R=10 nm, S=100 nm) is about 146 nm. It should be noted that this pillar length is given by way of example only, and is used to illustrate the inner relationship among process variables and the device geometry. The use of different process chemistry or different device geometry will yield a different calculated maximum value. Of course, those of ordinary skill in the art recognize that this maximum length is a calculation only, and there is actually a range of acceptable pillar lengths.
It should be also noted that the calculated length is for SOG pillars in air; however, during the drying of the SOG pillars after length definition in the chromic acid, capillary forces will increase the adhesion force between pillars, and this effect will cause agglomeration at somewhat shorter lengths. Experimentally, agglomeration of the pillars was observed to occur when they reached approximately 110 nm in length as shown in
The dimensions of the PAA templates in this study would yield devices with d—of ≈9-12 nm and ∈ox of ≈3.9 (the SOG is a silicate with a dielectric constant similar to SiO2). Also, the SWCNTs have a diameter of approximately 1-2 nm and have been shown to exhibit ∈body values in the range of 20-30. Therefore, this SG device geometry would yield a screening length of λ≈3 nm, which is one-fourth of the λ achieved from the same parameters using a bottom-gate geometry. Replacement of the SOG with an ALD high-κ dielectric As in other embodiments of the present invention would decrease the screening length to 1.5 nm for the surround-gate and improve the electrostatics of the resulting FET. The PAA pore diameter and spacing can also be scaled to smaller dimensions by anodizing at lower voltages or in a different electrolyte (e.g., sulfuric acid) to decrease dox.
Two other process acts can be used to control the channel length: one is the etchback of the PAA to expose the dielectric pillars, and the other is the final etch of the SOG filler to expose the V-SWCNT tips. For the three samples, the final SG channel length had a maximum variability of ±15 nm as measured using cross-sectional SEM images. As the ordering of the pores improves, the uniformity of the etching will improve, thus reducing the variations in channel length across a sample. Furthermore, improvement of the initial Al film surface smoothness and the dielectric layer uniformity (SOG in this case) can also increase the uniformity of channel length.
Another of these SG V-SWCNTs for FETs is that they lend themselves to the facile fabrication of multi-nanotube devices. The current-carrying capacity for many devices based on nanomaterials can be high for their nanoscale dimensions Realization of nanomaterial-enabled nanoelectronics in some embodiments includes the use of FETs with multiple channels. In these modified PAA templates, V-SWCNTs grow at a yield of no more than one per pore, and the pores can be fabricated in highly ordered arrays. Such arrays allow for the definition of the desired number of channels for a FET simply by defining an appropriately sized top contact to the surface shown in
The templated V-SWCNTs (with multi-nanotube FETs) with SGs also decrease detrimental charge-screening among nanotubes compared to planar SWCNT devices. When SWCNTs are closely packed, a capacitive coupling develops between them that causes a screening of the gate charge and thus a degradation of the current per nanotube. In the PAA template, each V-SWCNT is a fixed distance from its nearest neighbors and is individually coated in the dielectric and wrapped in the gate metal, thus allowing each channel to feel the same gate potential in a multi-nanotube FET.
The V-SWCNTs in the PAA still contain a mixture of metallic and semiconducting types. However, various embodiments described herein show a strong selectivity towards semiconducting nanotubes (95% of characterized nanotubes were semiconducting). Also, metallic nanotubes can be selectively removed by turning the semiconducting nanotubes OFF with the gate bias and sweeping a high bias on the metallic nanotubes to burn them out. When each multi-nanotube device contains a certain number of SG V-SWCNT channels, the statistical distribution of their band gap energies should be comparable from device to device, creating I-V characteristics within the same operating range as compared to the variation seen when testing many single nanotube devices.
A vertical FET structure for SG V-SWCNTs fabricated in accordance with some embodiments will contain a single underlap between the gate and Pd nanowire (drain) contact while the top contact is considered self-aligned to the gate. Al readily develops a 4-8 nm thick native oxide on its surface when exposed to air, and the presence of this layer has been shown to provide an adequate separation layer between gate and source/drain metals for self-aligned CNTFETs. The exposed Al gate (shown in the SEM image of
The top contact metal is electron-beam evaporated with the following sequential layers: 8 nm Pd/20 nm Ti/80 nm Au. The intermediate Ti is added to improve adhesion, and the Pd is preferably thin because of its poor adhesion to insulating surfaces.
One aspect of a vertical geometry for FETs includes gaining access to the gate, drain, and source contact metals. With the SG V-SWCNTs, addressing the bottom contact, which serves as the drain, is fairly straightforward—the top of the sample contains an unanodized portion of the original metal layers that directly accesses the underlying Ti, as shown in
approach to access the gate involved the use of SG V-SWCNTs that were templated in a PAA field surrounded by SiO2. Figures of the 1000—series schematically outline acts in a method according to one embodiment of the present invention, with two options for accessing the gate (identified in the figure number either as/1 or/2).
As previously discussed, the Pd nanocubes could be employed for studies from catalysis to sensing. However, other applications of these SWCNT-supported nanocubes can be achieved by further augmenting them with another electrodeposited layer. For instance, because of the biocompatibility of Au, biosensing applications can include a Au-coating on the Pd nanocubes. The Pd serves as a stable, low-resistance contact to the SWCNTs. The templating of these nanocube-decorated SWCNTs in PAA allows for even further customization; functionalizing independently accessible regions of nanocubes with specific metals/ligands can allow for the sensing of multiple biological species with a single chip (multiplexed biosensing).
Some embodiments of the present invention pertain to fabrication of individually addressable fields of PAA surrounded by SiO2. This is accomplished by defining underlying electrodes, depositing the SiO2 insulator, patterning user-defined fields on top of the electrodes, etching the SiO2 in these fields to expose the electrode metal, evaporating the desired film stack for PAA formation, and anodizing the film to create PAA fields (see
A Pd nanocube-decorated field of PAA according to another embodiment was selectively augmented with a thin layer of electrodeposited Au. Au was chronoamperometrically electrodeposited at a potential of 750 mV for 5 sec in a chloroauric acid electrolyte, forming an overlayer on the Pd nanocubes (see
Thermal transducers are used to characterize effects such as heat conduction mechanisms, electrical self-heating, and phase change phenomena in nanoscale devices. One specific type of transducer is a solid-state thermometer, which relates changes in electrical resistance to temperature. Such solid-state devices exhibit electrical resistance that is both stable at a constant temperature and highly sensitive to temperature changes.
Noise thermometry offers an alternative to resistance thermometry for nanoscale objects. In yet another embodiment of the present invention, vertical two-terminal SWCNT devices are used to measure the temperature dependent shot noise. When measured in combination with Johnson noise, Spietz et al. showed recently that shot noise can be exploited to achieve accurate temperature measurements from the mK range to many hundreds of Kelvin.
Further analysis of the data in
Thermionic emission involves the transfer of enough thermal energy to electrons that they overcome the work function (potential energy barrier) at the surface of a solid and escape either into vacuum or another material. Thermionic emission has been used for electron supply, including cathode ray tubes, fluorescent bulbs, scanning electron microscopes, mass spectrometers, and more. Vacuum and solid-state thermionic emission processes have attracted attention for generating electrical power from heat or solar energy. In such a device, electrons replace the usual working fluid, eliminating the need for mechanical components such as compressors, evaporators, and generators to convert mechanical work to electricity. The absence of moving parts in a thermionic emission diode potentially allows for long device lifetimes and silent operation.
The emitter material should have a very low work function to maximize the electron emission current and should also be stable at high temperatures. One embodiment includes the use of SWCNTs intercalated with potassium atoms (K/SWCNTs) as a possible emitter material for use in a thermionic emission power generator. It has been shown that the work function of pristine SWCNTs, which is similar to that of graphite (≈4-5 eV), can be reduced to 2-3 eV by the introduction of alkali metal intercalants. As for stability at high temperatures, Robinson et al. showed that intercalated potassium metal atoms can be stable in graphitic nanofibers at temperatures up to 970 K, indicating that emission from intercalated carbon nanostructures may exhibit greater long-term stability than that from planar emitting cathodes.
The K/SWCNTs emitters were fabricated using SWCNTs templated in PAA with electrodeposited Pd nanowire back contacts. Potassium intercalation was carried out by depositing a 30-60 nm layer of potassium on the samples surface and then heating the sample to an appropriate temperature corresponding to a stage-1 (C8K) or stage-2 (C24K) K/SWCNTs intercalate. Photonic excitation was combined with thermal excitation to enhance the thermal efficiency and power generation capacity. The K/SWCNTs emitter was irradiated with a 100 mW Nd:YAG laser (532 nm) while the resultant energy distributions of photo-emitted and thermionic electrons were measured using a hemispherical electron energy analyzer.
The first distribution was recorded at a sample temperature of approximately 560 K, and was followed by cooling to room temperature, which caused the magnitude of the laser-enhanced EED to decrease by over four orders of magnitude and shift toward higher energies by approximately 0.25 eV. Interestingly, reheating the sample to 380 K resulted in no visible change to the measured EED, yet when the sample was heated to 480 K the intensity increased by approximately 1000× and shifted to lower energies by 0.1 eV. Further heating of the sample to 580 K caused the emission peak to shift to nearly the same location as that of the first recorded data obtained at 560 K. Thereafter, heating the sample above 580 K caused the emission peak to shift to higher energies. At temperatures exceeding 580 K, potassium atoms are highly mobile in the SWCNT lattice; thus, the increase in the effective sample work function with increasing temperature may be due to rearrangement and deintercalation of the potassium atoms from the SWCNT surface.
Overall, it was observed that irradiating K/SWCNTs templated and contacted in PAA substantially increases the electron emission intensities above that which is obtained from thermionic emission alone. The PAA support provided an insulating support for the intercalation of SWCNTs that was stable at the high temperatures useful for thermionic emission studies.
Some embodiments of the present invention utilize a hydrogen plasma to allow for electrodeposition of Pd beginning at the underlying Ti. However, the present invention is not so limited, and yet other embodiments contemplate either methods for connection to the titanium substrate. One option is to use an inert gas ion bombardment etch to remove the barrier. An ion bombardment etch works by accelerating Ar ions toward the sample where they bombard and mechanically etch the surface. Directly following anodization, an ion bombardment can be performed to remove the barrier and fully expose the underlying Ti.
Various embodiments of the present invention include the use of electron beam lithography (EBL) to define an ordered arrangement of holes, followed by an etch to create pits that serve as subsequent pore nucleation sites. However, other embodiments of the present invention contemplate other methods for obtaining the ordered pores. Some embodiments include the use of nanoimprint lithography. Using a quartz mold with the desired pore pattern etched out of it, a carefully prepared resist is applied to the sample, imprinted, and hardened. The result is akin to the EBL-patterned resist, serving as an etch mask for creating pits in the Al surface. The throughput for nanoimprint can be orders of magnitude higher than EBL, with the capability of processing an entire wafer within a few hours. Other lithographic techniques may also improve on the EBL.
Spin-on glass (SOG) plays a role in fabricating V-SWCNT devices in some embodiments described herein. The primary roles of the SOG include providing a support for the V-SWCNTs and a dielectric for gating the nanotube channel. However, SOG also plays a role in centering the V-SWCNTs within their pores. When the SWCNTs grow from the embedded Fe layer, there is a possibility that they interface with the pore sidewall. The SOG wets the PAA efficiently, which is hypothesized to force the V-SWCNTs toward the center of their pore.
However, other embodiments of the present invention contemplate alternatives to the use of SOG. Atomic layer deposition (ALD) is one option for forming high-quality, uniform high-K dielectrics. ALD may pin the nanotube to the wall by depositing around it. Yet another process would involve centering the V-SWCNTs and then uniformly depositing a high-κ dielectric.
An embodiment of the present invention shown in
Yet another embodiment of the method discussed relative to
Various embodiments described herein pertain to SWCNT devices templated in PAA. However, yet other embodiments pertain to the use of templates other than PAA. One example is illustrated in
An embodiment of the present invention shown in
Yet another embodiment of the method discussed relative to
While the inventions have been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only certain embodiments have been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.
This application claims the benefit of priority to U.S. Provisional Patent Application Ser. No. 61/166,953, filed Apr. 6, 2009, entitled FABRICATION OF FIELD EFFECT TRANSISTORS FROM CARBON NANOTUBES, incorporated herein by reference.
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