Patent Application
20220310790
The technical field of the invention is that of power electronics. The present invention relates to a vertical-structure field-effect transistor, manufactured from a substrate made of III-N semiconductor material such as gallium nitride (GaN).
A high electron mobility transistor (or HEMT) is a field-effect transistor that benefits from the conductive properties of a 2-dimensional electron gas (or 2DEG). It comprises a vertical stack of III-N semiconductor layers on a substrate, typically made of silicon, silicon carbide or sapphire. The 2-dimensional electron gas is formed by a heterojunction between a channel layer, typically made of gallium nitride (GaN), and a barrier layer, typically made of aluminium gallium nitride (AlGaN).
This heterojunction transistor is qualified as a lateral-structure transistor, because the source electrode, the drain electrode and the gate electrode of the transistor are disposed on the same side of the substrate, the source electrode and the drain electrode being located on either side of the gate electrode.
The HEMT supports high current densities in the ON state, due to the high density of charge carriers and the great mobility of these carriers in the 2-dimensional electron gas. It can also have a high switching speed.
On the other hand, it has a relatively low threshold voltage, generally comprised between 1 V and 3 V, which is insufficient for certain applications, such as high-power automobile applications for example. Moreover, in order to obtain good voltage resistance in the OFF state, in other words a high breakdown voltage, substantial spacing between the gate electrode and the drain electrode is required, which increases the size of the transistor.
A vertical-structure GaN transistor can on the contrary have a high breakdown voltage without increasing the surface of the component, by adjusting the thickness of an active layer called the drift layer. This type of transistor is generally formed from a self-supporting substrate made of GaN.
The document [“1.8 mΩ·cm2 vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation”, Tohru Oka and al., Appl. Phys. Express 8, 054101, 2015] describes an example of a vertical GaN transistor, of the trench-MOSFET type.
In reference to
The transistor 10 of
It is therefore observed that the need for a power transistor having a high threshold voltage is not satisfied.
According to a first aspect of the invention, this need tends to be satisfied by providing a field-effect transistor comprising:
This vertical-structure transistor is remarkable in that the first face of the layer of III-N semiconductor material has a polarity of the nitrogen (N) type and in that the channel layer forms a heterostructure with the drift layer.
By successively disposing the drift layer and the channel layer on the nitrogen face of the layer of III-N semiconductor material (rather than the gallium face in the example of a substrate made of GaN), a negative piezoelectric charge is formed at the interface between the drift layer and the channel layer. This negative charge has for effect to raise the conduction band at this interface, creating a high barrier potential that opposes the passing of the current. This results in a significant increase in the threshold voltage of the transistor.
A III-N semiconductor material designates a material from the nitride family comprising (in addition to nitrogen) one or more elements of group 13 (column IIIA in the North American CAS system) of the periodic table of the elements.
The III-N semiconductor layer can be made of gallium nitride (GaN) or of aluminium gallium nitride (AlGaN).
In a preferred embodiment of the transistor, the drift layer is made of n-doped gallium nitride (GaN) and the channel layer is made of p-doped or unintentionally doped aluminium gallium nitride (AlGaN).
According to a development of this preferred embodiment, the aluminium gallium nitride (AlGaN) of the channel layer has a percentage of aluminium comprised between 20% and 40%.
According to another development, the channel layer has a thickness comprised between 10 nm and 20 nm.
In an alternative embodiment, the drift layer is made of n-doped aluminium gallium nitride (AlGaN) and the channel layer is made of p-doped or unintentionally doped aluminium nitride (AlN).
In another alternative embodiment, the drift layer is made of n-doped aluminium gallium nitride (AlGaN) and the channel layer is made of p-doped or unintentionally doped aluminium gallium nitride (AlGaN) and having a percentage of aluminium greater than that of the drift layer.
The transistor according to the first aspect of the invention can also have one or more of the characteristics hereinbelow, taken individually or in any technically permissible combination:
A second aspect of the invention relates to a method for manufacturing a field-effect transistor, comprising the following steps:
The method can further comprise a step of thinning the substrate before the step of forming the drain electrode.
A third aspect of the invention relates to a method for manufacturing a field-effect transistor, comprising the following steps:
The transfer substrate is advantageously made of metal.
Preferably, the stack further comprises a barrier layer formed by epitaxy on the first face of the growth substrate before the channel layer. The barrier layer is for example made of aluminium gallium nitride (AlGaN).
The invention and its different applications shall be better understood when reading the following description and when examining the accompanying figures.
Other characteristics and advantages of the invention shall appear clearly in the description of it which is given hereinbelow, for the purposes of information and in no way limiting, in reference to the following figures:
For increased clarity, identical or similar elements are marked with identical reference signs on all the figures.
The field-effect transistor 20 comprises:
The III-N semiconductor layer 21 is constituted of a first III-N semiconductor material with a hexagonal mesh structure, for example gallium nitride (GaN) or aluminium gallium nitride (AlGaN) (the aluminium atoms substituting for a portion of the gallium atoms in the AlGaN). The first face 21a has a polarity of the nitrogen (N) type, while the second face 21b has a polarity of the group III type (gallium, aluminium, indium . . . ). The notion of polarity is described in detail in the reference work [“Gallium nitride electronics”, Rüdiger QUAY, Springer Science & Business Media, pp. 29-30, 2008].
The III-N semiconductor layer 21 can be a self-supporting substrate made of III-N semiconductor material or a solid substrate made of III-N semiconductor material, on which the drift layer 22 and the channel layer 23 were successively formed. A self-supporting substrate is obtained by epitaxy of a thick layer on a growth substrate then removal of the growth substrate, while a solid substrate is obtained by drawing and cutting a lingot. Alternatively, the III-N semiconductor layer 21 can be an epitaxial layer on a growth substrate, this growth substrate being removed only after the formation of the drift layer 22 and the channel layer 23. The growth substrate is for example made of sapphire, silicon carbide or silicon.
With a concern for simplification, the term “substrate” will be used in what follows to designate the III-N semiconductor layer 21 of the transistor 20.
The first III-N semiconductor material is preferably n-type doped. The concentration in n-type doping impurities (for example silicon atoms) of the substrate 21 is preferably comprised between 1017 cm−3 and 1020 cm−3, for example equal to 1018 cm−3.
The transistor 20 has a vertical structure, because the source electrode 25 and the drain electrode 26 are disposed on either side of the substrate 21.
The drift layer 22, also called a voltage resistance layer, is constituted of a second III-N semiconductor material, for example gallium nitride (GaN) or aluminium gallium nitride (AlGaN). The second III-N semiconductor material, which can be identical or different from the first III-N semiconductor material (substrate 21), is preferably n-type doped. The concentration in n-type doping impurities of the drift layer 22 is advantageously less than that of the substrate 21. It is preferably comprised between 1014 cm−3 and 1017 cm−3, for example equal to 1016 cm−3. The thickness of the drift layer 22 is advantageously greater than 10 μm so as to provide the transistor 20 with good voltage resistance (drain-source voltage VDS), for example of at least 1000 V.
The channel layer 23 is the layer in which the conducting channel of the transistor 20 is formed, along a flank of the gate structure 27. It is constituted of a third III-N semiconductor material and forms a heterostructure with the drift layer 22. The third III-N semiconductor material (channel layer 23) therefore has a band-gap width that is different from that of the second III-N semiconductor material (drift layer 22). The band-gap width of the third III-N semiconductor material is advantageously greater than that of the second III-N semiconductor material, so as to create a potential barrier (due to the drift of the conduction bands), also called tunnel barrier, in the direction of the circulation of the charge carriers, here electrons coming from the source and moving in the direction of the drain. The third III-N semiconductor material can be p-type doped or unintentionally doped. The thickness of the channel layer 23 can be comprised between 10 nm and 30 nm.
In a preferred embodiment of the transistor 20, the drift layer 22 is made of n-doped GaN (1014 cm−3-1017 cm−3) and the channel layer 23 is made of p-doped or unintentionally doped AlGaN. The substrate 21 is advantageously made of n-doped GaN (1017 cm−3-1020 cm−3) in order to minimise the growth defects in the drift layer 22 made of n-GaN.
In an alternative embodiment, the drift layer 22 is made of n-doped AlGaN (1014 cm−3-1017 cm−3) and the channel layer 23 is made of p-doped or unintentionally doped aluminium nitride (AlN). In another alternative embodiment, the drift layer 22 is made of n-doped AlGaN (1014 cm−3-1017 cm−3) and the channel layer 23 is made of p-doped or unintentionally doped AlGaN with a concentration in aluminium greater than that of the drift layer 22. In these two alternative embodiments, the substrate 21 is advantageously made of n-doped AlGaN (1017 cm−3-1020 cm−3) in order to minimise the growth defects in the drift layer 22 made of n-AlGaN.
Advantageously, the transistor 20 further comprises a source contact layer 24 disposed between the channel layer 23 and the source electrode 25. The source contact layer 24 improves the quality of the electrical contact between the channel layer 23 and the source electrode 25.
The source contact layer 24 is preferably constituted of a fourth n-doped III-N semiconductor material, preferably at a concentration comprised between 1018 cm−3 and 1020 cm−3 so as to form a weakly resistive contact (ohmic) with the source electrode 25. The source contact layer 24 can form a second heterostructure with the channel layer 23. The fourth III-N semiconductor material is then different from the third III-N semiconductor material (channel layer 23). It is preferably identical to the first III-N semiconductor material (substrate 21).
In the absence of the source contact layer 24, the source electrode 25 is in direct contact with the channel layer 23.
The gate structure 27 of the transistor 20 is preferably a MOS (Metal-Oxide-Semiconductor) gate structure. It comprises a gate dielectric layer 27a and a gate electrode 27b separated from the channel layer 23 (and from the source contact layer 24, where applicable) by the gate dielectric layer 27a. The transistor 20 is then a metal-oxide-semiconductor (MOSFET) field-effect transistor, here with a n channel (n-MOSFET) given the type of conductivity of the substrate 21 (drain side) and of the source contact layer 24 (source side).
The gate dielectric layer 27a is for example made of silicon dioxide (SiO2). The gate electrode 27b is preferably made of metal, for example of titanium nitride (TiN).
The gate structure 27 is disposed in a trench 28, that extends to the drift layer 22 through the channel layer 23, and where applicable, the source contact layer 24 (this is then referred to as “trench-MOSFET”).
The source electrode 25 and the gate electrode 27b can each contain several portions. The portions of the same electrode are electrically connected together in order to be subjected to the same electrical potential. With a concern for clarity, only a portion of the gate electrode 27a and two portions of the source electrode 25, disposed on either side of the portion of the gate electrode 27a, were shown in
Like the source electrode 25 with the channel layer 23, the drain electrode 26 is in electrical contact (ohmic) with the substrate 21 made of III-N semiconductor material. The source electrode 25 and the drain electrode 26 are preferably made of metal, for example of TiN or TiN on Ti (bilayer).
A particularity of the field-effect transistor 20 is that the drift layer 22, the channel layer 23 and the source contact layer 24 (when the latter is desired) are stacked on the N polarity face of the substrate 21, rather than on the Ga polarity face as in the vertical GaN transistors of the prior art.
A negative piezoelectric charge 31 is formed at the interface between the drift layer 22 (made of GaN) and the channel layer 23 (made of AlGaN), in other words at the heterojunction. The electric field induced by this negative interface charge raises the conduction band BC at the interface, thus creating a potential barrier 32 that opposes the circulation of the electrons (from the source to the drain) when the transistor 20 is in the OFF state (VGS<VT, for example VGS=0 in
The increase in the potential barrier 32 results in a significant increase in the threshold voltage VT of the transistor, i.e. the gate-source voltage VGS from which the transistor becomes ON.
These figures show that the threshold voltage VT of the transistor 20 is much greater than 5 V and increases with the aluminium rate in the channel layer 23 made of AlGaN or with the thickness of the channel layer 23. This is due to the fact that the drift of the conduction bands between the GaN and the AlGaN (at the drift layer 22—channel layer 23 and channel layer 23—source contact layer 24 interfaces) increases with the aluminium rate or with the thickness of the channel layer 23.
A concentration in aluminium comprised between 20% and 40% and a thickness comprised between 10 nm and 20 nm constitute good compromises between a sufficiently high threshold voltage, facility of producing the control circuit of the transistor and current leakage in the OFF stated.
The p doping of the channel layer 23 provides an additional degree of adjustment of the threshold voltage VT of the transistor 20: the concentration in p-type doping impurities.
Two methods for manufacturing the field-effect transistor 20 according to
This first method of manufacturing initially comprises the providing of a self-supporting substrate 21 made of III-N semiconductor material. This substrate 21 has a first face 21a of a nitrogen polarity (“N face”) and a second face 21b, opposite the first face 21a and of polarity of the group III type (“group III face”). Its thickness is for example 400 μm.
The providing of the substrate 21 can comprise a growth operation of a layer of III-N semiconductor material on a host substrate, for example made of silicon, silicon carbide or sapphire, then an operation of removing the host substrate, for example by cutting or grinding.
The step S11 shown in
Advantageously, the first face 21a of the substrate 21 is inclined with respect to the plane c ({0001}) of the hexagonal mesh structure by an angle comprised between 0.2° and 4° and preferably between 0.5° and 2° in the direction of the plane a ({11
A metal layer, for example made of titanium or aluminium, can also be deposited on the source contact layer 24. This metal layer is intended to form a portion of the source electrode 25. The deposition of a portion of the source electrode 25 on the stack of epitaxial layers, immediately after the growth step, makes it possible to reduce the electrical resistance of the source electrode 25 and the contact resistance with the source contact layer 24.
The first method of manufacturing then comprises the formation of the gate structure 27 of the transistor.
In a preferred embodiment of the first method of manufacturing, the gate structure 27 is a MOS gate structure. Its formation advantageously comprises the steps S12 to S15 shown in
In step S12 of
The trench 28 has a bottom 28a and side walls 28b. The side walls 28b of the trench 28 preferably extend in a direction perpendicular to the first face 21a of the substrate 21.
The step S13 of
The formation of the passivation layer 29 can comprise the following operations:
Then, in S14 (
The gate dielectric layer 27a is advantageously formed by using a so-called high-temperature deposition technique, such as low pressure chemical vapour deposition (LPCVD) or atomic layer deposition (ALD). Compared to the other deposition techniques (in particular the PECVD technique used to form the passivation layer 29), these techniques make it possible to obtain a gate dielectric layer 27a of better quality, of a constant thickness (conformal deposition) and procures better control of its thickness.
In step S15 of
In reference to
The substrate 21 is advantageously thinned during a step S17 shown in
Finally, in step S18 of
The growth by epitaxy on the N polarity face of a self-supporting substrate made of III-N semiconductor material (such as the substrate 21) is more difficult than the growth on a group III polarity face. Moreover, a self-supporting substrate with a GaN base often has a higher dislocation rate on the N face than on the Ga face.
Thus, in a second method of manufacturing of the transistor 20 shown in
This second method of manufacturing first comprises the providing of a growth substrate 70 comprising a layer made of III-N semiconductor material, for example made of GaN or AlGaN. The growth substrate 70 comprises a first face 70a having a polarity of the group III type. The growth substrate 70 can be made of self-supporting substrate made of III-N semiconductor material, a solid substrate made of III-N semiconductor material or comprise a layer of III-N semiconductor material disposed on a support layer, for example made of sapphire, silicon carbide or silicon.
The step S21 of
During the epitaxy, the growth substrate 70 is thus oriented differently from the substrate 21 used in the first method of manufacturing (step S11 of
In step S22 of
In S23 (
In step S24 of
Finally, the gate structure 27 and the source electrode 25 of the transistor 20 are formed, preferably in the way described in relation with
This second method of manufacturing has the advantage of limiting the growth defects in the structure (vertical) of the transistor 20. It is however longer to implement.
Advantageously, the stack 700 further comprises a barrier layer 73, formed by epitaxy on the first face 70a of the growth substrate 70 before the source contact layer 24 (or the channel layer 23). This barrier layer 73, for example made of AlGaN, facilitates the removal of the growth substrate 70. Indeed, the growth substrate 70 is then removed in two steps, first by grinding or laser lift-off over several hundred micrometres, then the remaining thickness is removed by etching by stopping on the barrier layer 73. At the end of the step of removing the growth substrate 70, the layer 73 is removed by etching with stopping on the source contact layer 24 (or on the channel layer 23).
A piezoelectric interface charge between the drift layer and the channel layer can also be obtained in a field-effect transistor (vertical) with a p channel (p-FET), by disposing these layers on the group III polarity face of the III-N semiconductor layer 21/71.
Thus, another aspect of the invention relates to a p-channel field-effect transistor, comprising:
The III-N semiconductor layer, the drift layer and the source contact layer of the p-FET transistor a p-type doped, rather than n-type doped. In blocking and in conducting, the drain electrode of the transistor p-FET is negatively polarised (not positively as in the case of an n-FET transistor).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2103210 | Mar 2021 | FR | national |
