Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share a same body potential.
Source 3 and drain 3′ each include a contact, 4 and 4′, respectively, and are connected to a common body 7. Common body 7 also includes a contact, 4″.
According to one embodiment, the invention provides a semiconductor device comprising: a substrate; a field effect transistor (FET) comprising: a source within the substrate; a drain within the substrate; and an active gate atop the substrate and between the source and the drain; an inactive gate structure atop the substrate and adjacent the source or the drain; a body adjacent the inactive gate; and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate, the width of the active gate being a distance along a longitudinal axis of the active gate from a first end of the active gate to a second end of the active gate opposite the first end.
In another embodiment, the invention provides a semiconductor device comprising: a substrate; a first field effect transistor (FET) comprising: a first source within the substrate; a first drain within the substrate; and a first gate atop the substrate and between the first source and the first drain; a second FET adjacent the first FET, the second FET comprising: a second gate atop the substrate and adjacent the first drain of the first FET; and a second drain within the substrate and adjacent the second gate; a common body adjacent the second drain; and a discharge path within the substrate for releasing a charge from each of the first FET and the second FET, the discharge path lying between the first source and the common body, wherein the discharge path is substantially perpendicular to a width of the first gate, the width of the first gate being a distance along a longitudinal axis of the first gate from a first end of the first gate to a second end of the first gate opposite the first end.
In still another embodiment, the invention provides a semiconductor device comprising: a substrate; a field effect transistor (FET) comprising: a source within the substrate; a drain within the substrate; and an active gate atop the substrate and between the source and the drain; an additional gate atop the substrate and adjacent the source or the drain; and a body adjacent the additional gate, wherein the substrate includes a portion positioned between a pair of shallow trench isolations (STIs), the portion of the substrate having a substantially wedge shaped cross-section, a lower portion of the portion of the substrate extending laterally to a greater distance than an upper portion of the portion of the substrate, such that the lower portion is disposed beneath a portion of at least one of the STIs.
The illustrative aspects of the present invention are designed to solve the problems herein described and other problems not discussed, which are discoverable by a skilled artisan.
These and other features of embodiments of the invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
It is noted that the drawings are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements among the drawings.
Unlike known devices, semiconductor device 100 includes a second, inactive gate structure 52 adjacent second SiC:P region 32. The presence of inactive gate structure 52 separates SiC:P region 32 from SiGe:B region 34, which acts as a body contact area, on the other side of inactive gate structure 52. This reorients a discharge path within substrate 20, as compared to known devices. Specifically, the discharge path is substantially perpendicular to a width WG1 of active gate 50 and/or a width WG2 of inactive gate structure 52, the widths of active gate 50 and inactive gate structure 52 defined as a distance along a longitudinal axis of the gate from a first end to a second end opposite the first end. With this configuration, the wider the FET, the greater the benefit that may be gained, as compared to conventional devices. As used herein, the term “inactive” is meant to convey that inactive gate structure 52 is not directly involved in the function of n-FET 60, aside from the described orientation of discharge path. Similarly, “gate structure” is meant to convey that the feature is formed substantially as would be a functional gate, but that the feature, in some embodiments of the invention, does not function as a gate within a device, such as a FET.
In some embodiments of the invention, distances between active gate 50 and inactive gate structure 52 may be between about 50 nm and about 200 nm. Widths of active gate 50 and/or inactive gate structure 52, according to some embodiments of the invention, may be between about 0.2 μm and about 5 μm. As such, discharge path 80 is typically shorter than discharge paths in known devices, which, as described above, are oriented substantially parallel to, and extend the width of, the FET gate 5 (
As shown in
In
In
However, unlike the embodiments described above, a portion of substrate 420 between STI 410 is substantially wedge shaped in cross-section, as can be seen in
Substrate tabs 422, 424 provide a current channel between first n-FET 460 and second n-FET 470, which serves a dual function. First, the current channel improves the efficiency of the discharge paths of first n-FET 460 and second n-FET 470. Second, the current channel ensures that first n-FET 460 and second n-FET 470 are self-balanced and share the same potential. That is, first n-FET 460 and second n-FET 470 are self-balanced in that a change in potential of first n-FET 460 will be at least partially distributed to second n-FET 470 such that first n-FET 460 and second n-FET 470 equalize at approximately the same potential. One skilled in the art will recognize, of course, that a change in potential of second n-FET 470 will similarly be at least partially distributed to first n-FET 460.
In the embodiment shown in
Semiconductor devices including FETs according to embodiments of the invention, including those embodiments described above, may be formed using conventional techniques and methods, as will be recognized by one skilled in the art. Such techniques and methods include, for example, ion implantation, reactive ion etching (RIE), lithographic techniques such as photolithography, and epitaxial techniques.
Semiconductor devices according to various embodiments of the invention can be distributed by a fabricator in a raw wafer form (that is, a single wafer that has multiple unpackaged integrated circuit chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other single processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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6344671 | Mandelman et al. | Feb 2002 | B1 |
6815282 | Dachtera et al. | Nov 2004 | B2 |
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7687365 | Sleight | Mar 2010 | B2 |
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