BRIEF DESCRIPTION OF THE DRAWINGS
The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment, as set forth below. The Description of the preferred embodiment is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:
FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a fin-FET structure in accord with a preferred embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The invention provides a method for fabricating a fin-FET device while employing a bulk semiconductor substrate.
The invention realizes the foregoing object by backfilling a trough adjoining a fin within a bulk semiconductor substrate to form an exposed fin region of the bulk semiconductor substrate separated from a remainder portion of the bulk semiconductor substrate by an unexposed fin region of the bulk semiconductor substrate. Both the exposed fin region and the unexposed fin region are formed of limited cross-sectional dimensions. A gate dielectric layer and a gate electrode are subsequently successively layered upon the exposed fin region but not the unexposed fin region to thus form a fin-FET structure. Since the unexposed fin region is formed of limited cross-sectional dimensions, the same thus serves to effectively isolate the exposed fin region from the remainder portion of the bulk semiconductor substrate. Thus, the invention provides a method for fabricating a fin-FET structure that may be employed within a fin-FET device, as well as the resulting fin-FET structure, while employing a bulk semiconductor substrate.
FIG. 1 to FIG. 8 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a fin-FET structure in accord with a preferred embodiment of the invention.
FIG. 1 shows a bulk semiconductor substrate 10.
The invention may be practiced employing bulk semiconductor substrates of any of several varieties. They may include but are not limited to bulk silicon, bulk germanium, bulk silicon-germanium alloy and bulk III-V compound semiconductor substrates. Preferably, the invention employs a bulk silicon semiconductor substrate. The bulk silicon semiconductor substrate may have either dopant polarity, any of several dopant concentrations and any of several crystallographic orientations.
FIG. 2 shows the results of further processing of the bulk semiconductor substrate 10 of FIG. 1 to form an etched bulk semiconductor substrate 10′. The etched bulk semiconductor substrate 10′ has a fin 10a connected to a remainder portion 10b of the etched bulk semiconductor substrate 10′. As is illustrated within FIG. 2, the fin 10a separates a pair of troughs 11a and 11b adjoining and adjacent the fin 10a. The fin 10a is typically formed to a fin height of from about 100 to about 10000 angstroms above the remainder portion 10b of the etched bulk semiconductor substrate 10′. The fin 10a is also typically formed of a limited linewidth from about 10 to about 200 nanometers and an extended lateral dimension (not shown) terminating at both ends to provide a pair of source/drain contact pads. The fin 10a is intended to provide a channel region within a fin-FET device.
FIG. 3 shows the results of forming a blanket first dielectric layer 12 upon the etched bulk semiconductor substrate 10′. The blanket first dielectric layer 12 covers the fin 10a while partially backfilling each of the pair of troughs 11a and 11b. The blanket first dielectric layer 12 is formed employing a deposition method and preferably not a thermal oxidation method. The blanket first dielectric layer 12 may be formed from any of several dielectric materials, including generally higher dielectric constant dielectric materials (i.e., having a dielectric constant greater than about 4.0 such as silicon oxide, silicon nitride and silicon oxynitride dielectric materials) and generally lower dielectric constant dielectric materials (i.e., having a dielectric constant less than about 4.0 such as spin-on-polymer (SOP), spin-on-glass (SOG), fluorosilicate glass (FSG) and amorphous carbon dielectric materials). Preferably, the blanket first dielectric layer 12 is formed of a dielectric material (typically silicon oxide containing) deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method such as to provide a nominally planar partial backfilling of the pair of troughs 11a and 11b. The HDP-CVD method also provides a tip portion of the blanket first dielectric layer 12 above the fin 10a. Typically, the blanket first dielectric layer 12 is formed to a thickness of from about 50 to about 6000 angstroms such as to partially backfill the pair of troughs 11a and 11b to a thickness of from about 40 to about 60 percent of the height of the fin 10a while completely covering the fin 10a.
FIG. 4 illustrates the results of removing portions of the blanket first dielectric layer 12 from upon the upper surfaces and sidewalls of the fin 10a to form an exposed fin region 10a![]()
and an unexposed fin region 10a![]()
, while simultaneously forming a pair of patterned first dielectric layers 12a and 12b partially backfilling the pair of troughs 11a and 11b. The portions of the blanket first dielectric layer 12 formed upon the upper portions of the fin 10a may be removed therefrom while employing: (1) a chemical mechanical polish (CMP) planarizing method (for removing portions of the blanket first dielectric layer 12 from upon the top of the fin 10a), followed by; (2) a wet chemical etch method (for removing portions of the blanket first dielectric layer 12 from upon the sidewalls of the fin 10a). Within the resulting semiconductor product as illustrated in FIG. 4, the exposed fin region 10a![]()
typically extends for about 50 to about 6000 angstroms above the pair of patterned first dielectric layers 12a and 12b, and the unexposed fin region 10a″ typically extends for about 50 to about 6000 angstroms sidewall covered by the pair of patterned first dielectric layers 12a and 12b.
FIG. 5 shows a blanket stop layer 14 formed upon exposed portions of the pair of patterned first dielectric layers 12a and 12b, as well as the exposed fin region 10a![]()
. FIG. 5 also shows a blanket second dielectric layer 16 formed upon the blanket stop layer 14.
The blanket stop layer 14 may be formed from any of several stop materials having stop properties with respect to the blanket second dielectric layer 16. The blanket second dielectric layer 16 may be formed from any of several dielectric materials as are employed for forming the blanket first dielectric layer 12. Typically, the blanket stop layer 14 is formed of a silicon nitride stop material formed to a thickness of from about 100 to about 1000 angstroms. Typically, the blanket second dielectric layer 16 is formed to a thickness of from about 2500 to about 10000 angstroms.
FIG. 6 shows the results of planarizing the blanket second dielectric layer 16 to form a pair of patterned second dielectric layers 16a and 16b, while employing the blanket stop layer 14 as a planarizing stop layer. Such planarizing may be effected while employing planarizing methods as are conventional in the art, in particular such as chemical mechanical polish (CMP) planarizing methods.
FIG. 7 shows the results of stripping a portion of the blanket stop layer 14 from upon the exposed fin region 10a![]()
to thus form a pair of patterned stop layers 14a and 14b and an aperture 17 separating the pair of patterned stop layers 14a and 14b and the pair of patterned second dielectric layers 16a and 16b from the exposed fin region 10a![]()
. The portion of the blanket stop layer 14 may be removed employing etch methods as are otherwise generally conventional in the art. A phosphoric acid etch method may be employed when the blanket stop layer 14 is formed of a silicon nitride or silicon oxynitride material, and the pair of patterned second dielectric layers 16a and 16b is formed of a silicon oxide dielectric material.
FIG. 8 shows the results of forming a gate dielectric layer 18 upon the exposed fin region 10a. The gate dielectric layer 18 partially fills the aperture 17 between the exposed fin region 10a and the pair of patterned stop layers 14a and 14b, as well as the pair of patterned second dielectric layers 16a and 16b. The gate dielectric layer 18 may be formed employing methods and materials as are otherwise conventional in the semiconductor product fabrication art. Such methods will typically include thermal oxidation methods to form the gate dielectric layer 18 of a silicon oxide material.
FIG. 8 also shows a gate electrode 20 formed upon the gate dielectric layer 18. The gate electrode 20 bridges to the pair of patterned second dielectric layers 16a and 16b, while completely filling the aperture 17 that separates the exposed fin region 10a![]()
from the pair of patterned stop layers 14a and 14b and the pair of patterned second dielectric layers 16a and 16b. The gate electrode 20 may be formed employing methods and materials as are conventional in the semiconductor product fabrication art. Typically, the gate electrode 20 is formed of a doped polysilicon (having a dopant concentration of greater than about 1E20 dopant atoms per cubic centimeter) or polycide (doped polysilicon/metal silicide stack) gate electrode material. As is understood by a person skilled in the art, since the invention employs the pair of patterned second dielectric layers 16a and 16b as nominally planarizing layers, the gate electrode 20 may be patterned from a nominally planar blanket gate electrode material layer. This is advantageous since it provides more accurate patterning than of a corresponding blanket gate electrode material layer formed topographically upon a topographic feature.
FIG. 8 shows a schematic cross-sectional diagram of a fin-FET structure in accord with a preferred embodiment of the invention. The fin-FET structure is formed employing a bulk semiconductor substrate having a fin and an adjoining trough formed therein. The trough is partially backfilled with a dielectric layer to form an unexposed fin region and an exposed fin region from the fin. A gate dielectric layer is formed upon the exposed fin region (but not the unexposed fin region) and a gate electrode is formed upon the gate dielectric layer. The unexposed fin region is of sufficient height and limited cross-sectional dimensions such that it assists in providing adequate isolation of the exposed fin region from a remainder portion of the bulk semiconductor substrate. Thus, the invention provides a fin-FET structure and a method for fabricating the same that employs a bulk semiconductor substrate.
The preferred embodiment of the invention is illustrative of the invention rather than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions in accord with the preferred embodiment of the invention while still providing an embodiment in accord with the invention, further in accord with the accompanying claims.
Patent Application
20070272954
