Patent Application
20180226394
The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to circuits for managing electrostatic discharge (ESD) in fin-type field effect transistor (FinFET) structures.
As integrated circuit technology has evolved, circuit devices, including process-technology used to make those devices, has become ever smaller. Crowding of circuitry in these advanced devices increases the incidence of ESD, or the discharge of static electricity from a body surface to a device. ESD concerns are relevant to both manufacturing processes used in forming integrated circuit devices, as well as in the end-user environment, where haptics have increased the level of interaction between users and devices.
A first aspect includes a fin field effect transistor (FinFET) electrostatic discharge (ESD) device, the device comprising: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate, an n-well region laterally abutting the p-well region over the substrate, a first P+ doped region over the p-well region, and a first N+ doped region over the p-well region, a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.
A second aspect relates to a fin field effect transistor (FinFET) electrostatic discharge (ESD) device, comprising: a substrate including a p-well region and an n-well region, wherein the p-well region is adjacent to the n-well region; a Schottky diode above and electrically coupled to the n-well region to form a silicon controlled rectifier (SCR) including: a P+ doped region forming a well tap within the p-well region, a first N+ doped region forming a drain within the p-well region, a second N+ doped region forming a source, and wherein the Schottky diode is electrically coupled to the n-well region and spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.
A third aspect relates to a fin field effect transistor (FinFET) electrostatic discharge (ESD) device, comprising: a substrate including a p-well region and an n-well region, wherein the p-well region is adjacent to the n-well region, and wherein the n-well region contains a drain; a Schottky diode laterally abutting the drain of the n-well region, the Schottky diode electrically coupled with the n-well region to form a silicon controlled rectifier (ISCR) including: a P+ doped region forming a well tap within the p-well region, a first N+ doped region forming a source within the p-well region, a second N+ doped region forming a drain, and wherein the Schottky diode is electrically coupled to the n-well region and spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.
These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure.
It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative. It is understood that the various process steps discussed herein can be implemented in the same manner and/or with slight modifications for semiconductor elements embodied in forms other than a silicon layer. Further, semiconductor elements may be a remaining portion of a single semiconductor-on-insulator (SOI) substrate composed of a layer of semiconductor material bonded to and positioned over a buried insulator layer, as described elsewhere.
As noted herein, the conventional structures for reducing ESD voltage levels have been insufficient. Embodiments of the disclosure include a device with one or more Schottky diodes to protect ESD nodes from voltages that exceed a tolerance level of a device. Schottky diodes (also known as “Schottky barrier diodes”) are formed at a junction between a metal and a semiconductor material. The position of the metal directly adjacent to the semiconductor material can allow a depletion region to form at the boundary surface during operation of a device. The current-voltage properties of the Schottky diode depend upon the polarity of the applied voltage. As used herein, ‘well taps’ are used to prevent latch-up and positioned in the integrated circuit appropriate distances from one another. Each well tap is an electrically conductive lead that couples a well region of the integrated circuit to a power source and each substrate tap is an electrically conductive lead that couples a substrate region of the integrated circuit to ground. Coupling the well and substrate regions to power and ground, respectively, reduces the substrate resistance, thus causing the positive feedback to be removed. Additionally used herein, an ohmic contact, or an ‘ohmic contact trench’ is defined as one in which there is an unimpeded transfer of majority carriers from one material to another, i.e., the contacts do not limit the current. The way to achieve such a contact is by doping the semiconductor heavily enough that tunneling is possible.
Forming one or more devices according to the present disclosure can include forming a p-well and an n-well directly laterally adjacent to each other on a semiconductor substrate. As shown in
Further referring to
As noted, device 100 can also include a Schottky diode 102. Schottky diode 102 is formed laterally abutting n-well region 104, and is formed through the junction between a metal area and semiconductor substrate 108. A metal contact 125 forms the metal area in this embodiment and may electrically connect to n-well region 104. Schottky diode 102 is electrically coupled with a source side 126 of the FinFET ESD device to a silicon-controlled rectifier (SCR) that possesses an extra terminal at contact 125 as an anode to apply a latching voltage to be turned on. Metal contact 125 may include metal such as but not limited to: molybdenum, platinum, chromium or tungsten, and may include certain silicides (e.g., palladium silicide and platinum silicide). To act as an anode region of Schottky diode 102, n-well region 104 can be negatively doped, e.g., with ions of arsenic and/or phosphorus. This n-well region 104 is on source side 126 of device 110, i.e., NMOS FinFET.
The SCR of device 100 can also include a P+ doped region 112 forming a well tap to give a reverse bias to n-well region 104 and p-well region 106 to avoid latch-up. Device 100 can also include a first fin N+ doped region 114 acting as a drain region and a second N+ doped region 116 acting as a source region, adjacent to a gate 124 (fin) formed above p-well region 106 between first N+ doped region 114 and a second N+ doped region 116. Device 100 can include a shallow isolation trench 118 laterally abutting P+ doped region 112, which also laterally abuts isolation trench 120. Isolation trench 122 is adjacent to the second N+ doped region 116 and n-well region 104. Optional power clamp 150 may be electrically coupled to P+ doped region 112 to fix either the positive or the negative peak excursions of a signal to a defined value by shifting its DC value.
Referring to
Referring to
Referring to
Device 400 can also include a P+ doped region 412 forming a well tap to give a reverse bias to n-well region 404 and p-well region 406 to avoid latchup. Device 400 can also include a first N+ doped region 416 acting as a drain, and a second N+ doped region 414 acting as a source region adjacent to a gate 424 (fin) formed above p-well region 406. Gate 424 is positioned between a first N+ doped region 414 and a second N+ doped region 416. Device 400 can also include shallow isolation trench 418 laterally abutting P+ doped region 412, which in turn can laterally abut an isolation trench 420. Isolation trench 420 is positioned between second N+ doped region 414 and P+ doped region 412, and isolation trench 422 is positioned between N+ dope region 416 and n-well region 404.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s).
Spatially relative terms, such as “inner,” “outer,” “beneath,” “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the disclosure as defined by the accompanying claims.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
