Patent Application
20150097197
The present invention relates generally to semiconductor fabrication and, more particularly, to improved finFET devices and methods of fabrication.
Semiconductor devices are increasing in layout density. Fin-type manufacturing techniques are employed to create non-planar structures on a semiconductor substrate. In these techniques, a semiconductor “fin” is formed, which facilitates formation of the gate of a device. Device density can be increased because the channel, source, and/or drain can be raised out of the semiconductor substrate, which reduces potential current leakage from the device. Accordingly, a device manufactured according to such a technique is often referred to as a fin-shaped field effect transistor (finFET). As integrated circuits continue to scale downward in size, the finFET is becoming an attractive device for use with smaller nodes (e.g., the 22 nm node and beyond). In a finFET, the channel is formed by a semiconductor fin, and a gate electrode is located on at least two sides of the fin. FinFETs have a wide variety of applications. It is therefore desirable to have improved finFET devices and methods of fabrication.
In a first aspect, the present invention provides a method of forming a semiconductor structure, comprising: forming a sigma cavity in a semiconductor substrate, wherein the sigma cavity is adjacent to a gate disposed on the semiconductor substrate; forming a first epitaxial material region in the sigma cavity; and forming a second epitaxial material region disposed on the first epitaxial material region.
In a second aspect, the present invention provides a semiconductor structure, comprising: a semiconductor substrate; a gate disposed on the semiconductor substrate; a sigma cavity formed in the semiconductor substrate adjacent to the gate; a first epitaxial material region formed in the sigma cavity; and a second epitaxial material region formed on the first epitaxial material region.
In a third aspect, the present invention provides a semiconductor structure, comprising: a semiconductor substrate; a gate disposed on the semiconductor substrate; a sigma cavity formed in the semiconductor substrate adjacent to the gate; a first epitaxial material region formed in the sigma cavity; a second epitaxial material region formed on the first epitaxial material region; and a stacking fault formed in the semiconductor structure, extending from the semiconductor substrate through the first epitaxial material region and the second epitaxial material region.
Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG.).
Features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique.
It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure (e.g., a first layer), is present on a second element, such as a second structure (e.g. a second layer), wherein intervening elements, such as an interface structure (e.g. interface layer), may be present between the first element and the second element.
While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.
