Claims
- 1. A micromirror device comprising:a semiconductor substrate; at least one memory cell formed in said substrate, said memory cell comprising: a first input/output node; a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node; at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes; at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.
- 2. The micromirror device of claim 1, further comprising:a bitline; and a write transistor connecting said bitline to said first input/output node.
- 3. The micromirror device of claim 2, wherein a 7.5 volt write signal is used to enable said write transistor.
- 4. The micromirror device of claim 2, further comprising: a pre-charge capacitor electrically connected to said bitline.
- 5. The micromirror device of claim 4, further comprising:a pair of pre-charge transistors, each of said pre-charge transistors connecting said bitline to a supply voltage.
- 6. The micromirror device of claim 1, each of said first and second inverters comprising two transistors.
- 7. A memory cell comprising:a first input/output node; a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node; at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes; at least one deflectable member supported by a semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.
- 8. The memory cell of claim 7, further comprising:a bitline; and a write transistor connecting said bitline to said first input/output node.
- 9. The memory cell of claim 8, wherein a 7.5 volt write signal is used to enable said write transistor.
- 10. The memory cell of claim 8, further comprising:a pre-charge capacitor electrically connected to said bitline.
- 11. The micromirror device of claim 10, further comprising:a pair of pre-charge transistors, each of said pre-charge transistors connecting said bitline to a supply voltage.
- 12. A image projection system comprising:a light source for providing a beam of light along a light path; a micromirror device on said light path for selectively reflecting portions of said beam of light along a second light path in response to image data signals; a controller for providing image data signals to said micromirror device; and a projection lens on said second light path for focusing said selectively reflected light onto an image plane; said micromirror device comprising; a semiconductor substrate; at least one memory cell fabricated on said semiconductor substrate, said memory cell comprising: a first input/output node; a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node; at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes; at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority under 35 USC § 119(e)(1) of provisional application No. 60/114,193 filed Dec. 30, 1998.
The following patents and/or commonly assigned patent applications are hereby incorporated herein by reference:
US Referenced Citations (8)
Provisional Applications (1)
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Number |
Date |
Country |
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60/114193 |
Dec 1998 |
US |