Patent Application
20150236136
The disclosure relates most generally to semiconductor manufacturing methods and semiconductor devices, and more particularly to floating gate flash memory cells with low erase voltages and methods for forming the same.
A flash memory semiconductor device is a non-volatile storage device that can be electrically erased and reprogrammed. Flash memories are commonly used in memory cards, USB flash drives and solid-state drives for general storage and transfer of data between computers and other digital products. Flash memories typically store information in an array of memory cells made using floating gate transistors.
A floating gate transistor is a field effect transistor having a structure similar to a MOSFET (metal oxide semiconductor field effect transistor). Floating gate MOSFETs are distinguished from MOSFETs because the floating gate transistor includes two gates instead of one. In addition to an upper control gate, a floating gate transistor includes an additional floating gate between the control gate and above the transistor channel but completely electrically isolated by an insulating layer such as an oxide that completely surrounds the floating gate. This electrically isolated floating gate creates a floating node in DC with a number of inputs or secondary gates such as the control gate, formed above the floating gate and electrically isolated from it. These secondary gates or inputs are capacitively connected to the floating gate. Because the floating gate is completely surrounded by highly resistive material, i.e., an insulating layer, any charge placed on the floating gate is trapped there and the floating gate remains unchanged for long periods of time until the floating gate MOSFET is erased.
Unless erased, the floating gate will not discharge for many years under normal conditions. These devices, however, must often be erased.
The default state of an NOR flash cell is logically equivalent to a binary “one” value because current flows through the channel under application of an appropriate voltage to the control gate when charge is stored in the floating gate. Such a flash cell device can be programmed or set to binary “zero” by applying an elevated voltage to the control gate.
To erase such a flash cell, resetting it to the “one” state, a large voltage of the opposite polarity is applied between the control gate and the source causing electrons to exit the floating gate through quantum tunneling. In this manner, the electrical charge is removed from the floating gate. In stacked gate flash cells, i.e., when the control gate is directly over the floating gate, a high voltage is used to erase the flash cell. In split gate flash cells, i.e., flash cells in which the control gate is formed over part of the floating gate and is also disposed along the side and lateral to the floating gate, floating gate transistors with large feature sizes are used to provide a sufficiently large area between the two electrodes so that, when a voltage is applied, the transistor will be erased. For stacked gate flash cells, the high voltage levels are undesirable and can cause other problems such as shorting in the devices. In split gate flash cells, the large device features take up valuable space and reduce integration levels.
The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.
Various embodiments of the disclosure provides flash memories with floating gate transistors that can be erased using relatively low voltages and split gate flash cell memory devices that do not require large critical dimensions in order to be erased.
Various embodiments of the disclosure provide floating gate transistors including both stacked gate floating gate transistors and split gate floating gate transistors. Some embodiments provides a floating gate electrode with an increased upper surface area and an upper surface area that is much greater than the corresponding lower surface area, i.e. much greater than the “footprint” of the floating gate. In some embodiments, the area of the upper surface is at least 300% of the area defined by the lateral dimensions of the floating gate electrode. This is attributable to sharp peaks, also referred to as apices throughout this disclosure, formed on the top surface, and pillars associated with the apices, according to various embodiments of the disclosure. In various other embodiments of the disclosure, the floating gate electrode includes an increased surface area with other surface configurations such as but not limited to pillars with flat top surfaces and having a generally rectangular shape or pillars with rounded tops or a generally roughened surface with increased surface area.
Because the upper surface of the floating gate electrode includes an increased surface area, stacked gate floating gate transistors can be erased using lower erase voltages. Further, split gate flash cell floating gate transistors do not require large device features because of the increased area that enables the flash cells to be erased using a voltage considerably less than necessary for erasing a floating gate transistor with a flat, smooth upper surface. Various embodiments of the disclosure provide methods for forming the stacked and split gate floating gate transistors by forming a polymer “grass” on the surface of the floating gate prior to carrying out an etching operation in which the polymer grass functions as a plurality of tiny masking objects that enable the production of the floating gate electrode with the roughened upper surface with sharp edges and therefore a greater surface area.
The thicknesses and other dimensions provided in the foregoing and following descriptions are according to various embodiments of the disclosure, but other thicknesses and dimensions are used in other embodiments. In each case, the dimensions are best suited to manufacturability, comply with design rules, and produce a device with maximized functionality and performance.
These residual specks 21 serve as masking objects during an etching operation used to etch silicon layer 3 as will be shown in
In various embodiments of the disclosure, the surface area of the upper surface such s upper surface 37 is at least 300% of the surface area defined by the lateral dimensions of silicon layer 3 and bottom surface 11. In various embodiments of the disclosure, upper surface 37 of etched silicon layer 3 includes a surface area that ranges from about 200-400% of the area defined by the lateral dimensions such as width 32 and an orthogonal lateral dimension (not shown) of silicon layer 3. In various other embodiments of the disclosure such as shown in
Now turning to
After the etching operation is carried out and the photoresist removed, spacers 45 and a silicide portion 49 are formed over the stacked floating gate transistors in some embodiments such as shown in
An etching operation is then carried out at this stage to completely etch, i.e. remove, uncovered portions of silicon layer 3 and gate dielectric 5. After silicon layer 3 is patterned by etching, dielectric 53 is formed over patterned silicon layer 3 including over top surface 37 and along the opposed sides of silicon layer 3 and over the surface of laterally adjacent portions of substrate 1 according to the embodiment in which a split gate transistor is being formed. The patterned silicon layer 3 and dielectric 53 are shown in
In some embodiments, dielectric 53 is a conformal dielectric and includes a thickness chosen in conjunction with various device considerations. In some embodiments, dielectric 53 has a thickness ranging from about 2-100 nm, but other thicknesses are used in other embodiments. In some embodiments, dielectric 53 is an oxide or a nitride, and in other embodiments, dielectric layer 33 is an ONO (oxide/nitride/oxide) layer, including a native oxide, a nitride layer over the native oxide, and a top oxide layer having various thicknesses.
Various other densities of pillars and apices are achieved in other embodiments and are determined, at least in part by the plasma density and the RIE plasma etching conditions. It can be seen that the surface area of the top of the structure shown in
Further, the surface area of the roughened upper surface of silicon can take on other shapes as described above and as shown in
According to one aspect, a method for forming a floating gate transistor is provided. The method comprises: forming a silicon layer over a gate dielectric layer over a substrate; coating a polymer layer over the silicon layer; treating the polymer layer with an RIE (reactive ion etch) process that removes portions of the polymer layer and creates a plurality of residual specks of polymer from the polymer layer on the silicon layer; etching the silicon layer using the plurality of residual specks as masking objects and thereby producing a plurality of sharp apices in the silicon layer; removing the residual specks; and forming a floating gate for a floating gate transistor, from the silicon layer.
In some embodiments, the polymer comprises photoresist and an upper surface of the etched silicon layer has a surface area being at least 300% of an area defined by lateral boundaries of the polysilicon layer.
In some embodiments, the polymer comprises one of a uv-curable photosetting polymer and a thermoplastic polymer.
In some embodiments, the residual specks include radii ranging from about several nanometers to about several hundred nanometers and the forming a floating gate comprises forming a further dielectric over the silicon layer after the etching, forming a polysilicon layer over the dielectric and patterning the polysilicon layer, the further dielectric and the silicon layer, the further dielectric being an oxide or a nitride and including a thickness of about 2-50 nm.
In some embodiments, the forming a floating gate comprises forming a further dielectric over the silicon layer after the etching, forming a polysilicon layer over the dielectric and patterning the polysilicon layer, the further dielectric and the silicon layer, the further dielectric being an ONO dielectric including a native oxide, a nitride layer and a top oxide layer.
In some embodiments, the floating gate transistor comprises a split gate floating gate transistor and the forming a floating gate comprises patterning the silicon layer, etching to remove uncovered portions of the silicon layer thereby forming a floating gate, forming a further dielectric over top and sides of the floating gate, then forming an upper control gate over a portion of the floating gate and laterally adjacent one side of the floating gate, wherein the further dielectric comprises an ONO dielectric including a native oxide, a nitride layer and a top oxide layer.
The method as in claim 1, wherein the treating includes the RIE process including a pressure of about 100-300 millitorr, a power of about 200-400 watts, a time of about 30 seconds to 2 minutes, a magnetic field of about 20-40 Gauss and HBr and Cl2 as etching gases.
In some embodiments, the sharp apices form tops of respective pillars having heights ranging from about 5 nm to about 300 nm.
In some embodiments, the silicon layer comprises polysilicon and the sharp apices form tops of respective pillars having heights ranging from about 50% to about 100% of an original height of the silicon layer.
According to another aspect, a method for forming a floating gate transistor is provided. The method comprises: forming a polysilicon layer over a gate dielectric layer over a substrate, the polysilicon layer having an upper surface with a first surface area; forming a sacrificial layer over the polysilicon layer; treating the sacrificial layer with an RIE (reactive ion etch) process that removes portions of the sacrificial layer and creates a plurality of residual specks from the sacrificial layer on the polysilicon layer; and etching the polysilicon layer using the plurality of residual specks as masking objects and thereby producing a second surface area of the polysilicon layer being greater than the first surface area.
In some embodiments, the second surface area is at least 300% of an area defined by lateral boundaries of the polysilicon layer and further comprising: removing the residual specks; forming a floating gate from the etched polysilicon layer and a dielectric on the floating gate; and forming a control gate over the floating gate.
In some embodiments, the sacrificial layer comprises an oxide layer and the dielectric comprises an ONO dielectric including a native oxide, a nitride layer, and a top oxide layer.
In some embodiments, the upper surface includes a plurality of polysilicon pillars.
In some embodiments, the second surface area is at least two times as great as the first surface area and the residual specks include radii ranging from about several nanometers to about several hundred nanometers.
In some embodiments, the sacrificial layer comprises one of a UV-curable photosetting polymer and a thermoplastic polymer.
In some embodiments, the upper surface has a surface area being at least 300% of an area defined by lateral boundaries of the polysilicon layer.
According to another aspect, a floating gate transistor comprises: a polysilicon layer disposed over a gate dielectric layer disposed over a substrate, the polysilicon layer having an upper surface including a plurality of polysilicon pillars; a further dielectric disposed over the polysilicon layer; and a control gate disposed over the further dielectric.
In some embodiments, the polysilicon pillars have apices and in some embodiments, the apices are sharp apices.
In some embodiments, the polysilicon pillars have flat top surfaces and a rectangular shape.
In some embodiments, the polysilicon pillars have rounded top surfaces.
In some embodiments, the upper surface has a surface area being at least 300% of an area defined by lateral boundaries of the polysilicon layer.
The preceding merely illustrates the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
Although the disclosure has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the disclosure, which may be made by those of ordinary skill in the art without departing from the scope and range of equivalents of the disclosure.
