Forward error correction using non-binary low density parity check codes

Abstract

Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink.

Description

TECHNICAL FIELD

The present document relates to wireless communication, and more specifically, to forward error corrections codes used therein.

BACKGROUND

Forward error correction is used in a wide variety of devices including wireless communications systems, wired communications systems, optical communication systems, disk drives, as well as many others. Forward error correction adds redundancy to transmitted information that allows for correction of errors at a receiver. For example, errors caused by noise in a transmission channel between a transmitter and receiver may be corrected at the receiver. Low density parity check codes provide excellent forward error correction performance but new techniques are needed to improve their performance even more.

SUMMARY

This document relates to methods, systems, and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes. Embodiments of the disclosed technology formulate a parity-check matrix that includes non-binary entries, which provides better permutations, thereby lessening error triggering events and producing extremely low error floors such as 10⁻¹¹ or 10⁻¹².

In one exemplary aspect, a method for forward error correction is disclosed. The method includes receiving information bits, encoding the information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries, modulating the encoded information bits to generate a signal, and transmitting the signal. The signal is modulated using an OTFS or OFDM modulation scheme.

In another exemplary aspect, a method for forward error correction is disclosed. The method includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries, and providing the decoded data to a data sink.

In yet another exemplary aspect, the above-described method(s) are embodied in the form of processor-executable code and stored in a computer-readable program medium.

In yet another exemplary aspect, a device that is configured or operable to perform the above-described methods is disclosed.

The above and other aspects and their implementations are described in greater detail in the drawings, the descriptions, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example of a transformation in the OTFS domain.

FIG. 2 shows an example of a transformation using the OTFS lattice.

FIGS. 3A and 3B show an example of the OTFS information domain and a received OTFS symbol, respectively.

FIG. 4 shows an example of a two-dimensional (2D) OTFS transform from the delay-Doppler domain to the time-frequency domain.

FIG. 5 shows an example of the 2D OTFS transform to a basis function.

FIG. 6 shows an example of a periodic transform.

FIG. 7 shows an exemplary system that uses the NB-LDPC code.

FIG. 8 shows an example Tanner graph for an LDPC code.

FIG. 9 shows an example of an LDPC encoder within a transmit chain.

FIG. 10 shows an example of the overall architecture for the LDPC encoder.

FIG. 11 shows an example of the LDPC encoder core architecture with signaling.

FIGS. 12A, 12B and 12C shows exemplary memory elements and mappings for a generator matrix associated with the LDPC code.

FIG. 13 shows an example of a submatrix processing unit.

FIG. 14 shows an example plot of the max* function.

FIGS. 15A-15D show exemplary architectures for various max* functions.

FIG. 16 shows an example of message passing at an equality node.

FIG. 17 shows an example of messaging on a Tanner graph.

FIG. 18 shows an example of an LDPC decoder within a receive chain.

FIG. 19 shows an example of the LDPC decoder architecture.

FIG. 20 shows an example architecture for an elementary check node (ECN).

FIG. 21 shows an example of a recursive calculations used in LLR computations.

FIGS. 22A and 22B show an example of an LDPC-symbol-wise and bit-wise LLR computation, respectively, for a 16-QAM constellation.

FIG. 23 shows an example of an LLR computation architecture.

FIG. 24 shows an example method for forward error correction, in accordance with some embodiments of the presently disclosed technology.

FIG. 25 shows an example method in accordance with some embodiments of the presently disclosed technology.

FIG. 26 is a block diagram representation of a portion of an apparatus, in accordance with some embodiments of the presently disclosed technology.

DETAILED DESCRIPTION

Section headings are used in the present document to improve readability of the description and do not, in any way, limit the discussion to the respective sections only. Section headings are used only to facilitate readability and are not intended to limit the embodiments and technology described in each section only to that section. Furthermore, for ease of explanation, a number of simplifying assumptions have been made. Although these simplifying assumptions are intended to help convey ideas, they are not intended to be limiting.

Next generation of applications and services that use wireless transmission will demand high reliability of data transmission. For example, it is expected that applications such as autonomous vehicle driving and medical patient care may rely on wireless transmission. Therefore, it is becoming important to provide very high reliability and low error rate of data transmission in wireless networks.

Traditional error correction codes often are not able to meet the stringent bit error rate (BER) requirements of the next generation wireless networks. In some cases, the codes may mathematically allow for very low BER operations, but the computational complexity for such implementations may be excessive for next generation wireless devices. For example, many devices may be powered from a battery that is not easily replaceable (e.g., machine to machine communication devices) or may have minimal power storage capability (e.g., IoT devices, wireless devices with small, thin form factors).

The techniques provided in the present document overcome these challenges, and others. In one example aspect, a mathematically powerful error correction code is disclosed, along with its encoding and decoding implementations. The code uses non-binary symbols and achieves very high degree of reliability without causing significant increase in computational complexity. The use of such codes, along with recently developed OTFS modulation technique, is expected to meet the stringent reliability and other operational needs of next generation wireless networks.

To explain the disclosed subject matter, a brief introduction to OTFS modulation is first provided, followed by various embodiments of the error coding technology disclosed herein.

1 Overview of OTFS Modulated Systems

OTFS modulation has numerous benefits that tie into the challenges that 5G systems are trying to overcome. Arguably, the biggest benefit and the main reason to study this modulation is its ability to communicate over a channel that randomly fades within the time-frequency frame and still provide a stationary, deterministic and non-fading channel interaction between the transmitter and the receiver. As will be seen, in the OTFS domain all information symbols experience the same channel and the same SNR, e.g., there is no concept of time-selective or frequency-selective fading.

Further, OTFS best utilizes the fades and power fluctuations in the received signal to maximize capacity. To illustrate this point, assume that the channel consists of two reflectors which introduce peaks and valleys in the channel response either across time or across frequency or both. An OFDM system can theoretically address this problem by allocating power resources according to the waterfilling principle. However, due to practical difficulties such approaches are not pursued in wireless OFDM systems, leading to wasteful parts of the time-frequency frame having excess received energy, followed by other parts with too low received energy. An OTFS system resolves the two reflectors and the receiver equalizer coherently combines the energy of the two reflectors, providing a non-fading channel with the same SNR for each symbol. It therefore provides a channel interaction that is designed to maximize capacity under the transmit assumption of equal power allocation across symbols (which is common in existing wireless systems), using only standard AWGN codes.

In addition, OTFS operates in a domain in which the channel can be characterized in a very compact form. This has significant implications for addressing the channel estimation bottlenecks that plague current multi-antenna systems and can be a key enabling technology for addressing similar problems in future massive MIMO systems. One key benefit of OTFS is its ability to easily handle extreme Doppler channels. This is not only useful in vehicle-to-vehicle, high speed train and other 5G applications that are Doppler intensive, but can also be an enabling technology for mm-Wave systems where Doppler effects will be significantly amplified.

Further, as will be seen, OTFS provides a natural way to deliver massive processing gain, and two dimensional CDMA random access to multicarrier systems. The processing gain can address the challenge of deep building penetration needed for IoT applications, while the CDMA multiple access scheme can address the battery life challenges and short burst efficiency needed for IOT deployments.

Last but not least, the compact channel estimation process that OTFS provides can be essential to the successful deployment of advanced technologies like Cooperative Multipoint (Co-MP) and distributed interference mitigation or network MIMO.

1.1 Example Principles of OTFS Modulation

OTFS works in the Delay-Doppler coordinate system using a set of basis functions orthogonal to both time and frequency shifts. FIG. 1 illustrates the modulation and demodulation steps. The transmit information symbols (QAM symbols) are placed on a lattice or grid in the 2-dimensional Delay-Doppler domain, as opposed to the more familiar Time-Frequency domain, where OFDM, TDMA and CDMA information symbols would be placed. A two dimensional OTFS transform (similar to a 2D FFT) translates the QAM symbols from the Delay-Doppler domain into the Time-Frequency domain.

Through this transform, each QAM symbol is spread throughout the Time-Frequency plane (e.g., across the full signal bandwidth and symbol time) utilizing a different basis function. As a result, all symbols have the same SNR and experience exactly the same channel. The implication is that there is no frequency or time selective fading of QAM symbols, in contrast with existing modulations such as OFDM or TDMA. Since FEC is not required to counter this frequency or time selective fading impact, the full power of the code can be applied to the non-faded signal.

After the 2D OTFS transform, the signal is now spread throughout the Time-Frequency plane. In fact, the transform results in a doubly periodic extension that extends throughout frequency and time. This signal is be windowed, as will be explained below. The resulting transformed and windowed signal lies in the same domain as the familiar OFDM symbols. The OTFS signal then follows the same data path as an OFDM symbol, namely through a transmit filter bank. At the receive side, the inverse processing is performed. Note that in OFDM the transmit and receive symbols in the Time-Frequency domain are related through the multiplicative channel H(f, t), whereas in OTFS the transmit and receive symbols in the Delay-Doppler domain are related through the convolutive channel h(τ, ν).

1.2 Examples of the OTFS Lattice

An alternate illustration of this construction is shown in FIG. 2. In this figure the OTFS QAM symbols reside on a grid or lattice of size N×M. The OTFS transform translates these QAM symbols to a lattice in the Time-Frequency plane of size M×N (note the swapping of axes—a result of the OTFS transform, as will be explained below). The OTFS Delay-Doppler lattice and the Time-Frequency multi-carrier lattice are related through a mathematical reciprocity relation intimately linked with the symplectic Fourier transform. In this Time-Frequency domain, one can think of the points along the frequency axis as the equivalent of an OFDM symbol, made up of M subcarriers. In the time dimension, we have the equivalent of N OFDM symbols, where N is a design parameter related to the Doppler spread of the channel.

Another observation worth noting in FIG. 2 is the fine resolution of the Delay-Doppler lattice. In the Delay-Doppler coordinate system, the delay or multipath resolution is given by the inverse of the bandwidth and the Doppler resolution is given by the inverse of the OTFS symbol time or observation time.

To summarize, in OTFS information symbols are indexed by points on a lattice or grid in the Delay-Doppler domain. Through the OTFS Transform each QAM symbol weights a 2D basis function defined in the Time-Frequency domain. The frequency domain samples at each time are transformed into time domain waveforms using filter banks.

1.3 The OTFS Information Domain

In OTFS, the information QAM symbols are arranged over an N×M grid on the Delay-Doppler plane, as shown in FIG. 3A. One pilot substitutes one of the information QAM symbols for channel sounding and acquisition. The pilot power can be boosted since the energy of all symbols is spread evenly throughout the Time-Frequency domain. An unused rectangle surrounds the pilot to allow for interference-free channel estimation at the receiver. For multiple streams/antennas, additional pilots would be inserted along the empty strip shown on the top part of the figure.

1.4 Examples of Channel Estimation

After transmission and demodulation, the received OTFS symbols are given by the two dimensional convolution of the transmitted QAM symbols above with the Delay-Doppler channel. The result is shown in FIG. 3B. As seen therein, the Delay-Doppler impulse response estimate is given by the region surrounding the received pilot. By extracting this region, a concise and accurate estimate of the Delay-Doppler impulse response may be obtained. In some embodiments, a 2D equalizer is used to remove the convolutive interaction of the channel with the transmitted QAM symbols. Standard equalization techniques can be used, extended to two dimensions.

1.5 Examples of the 2D OTFS Transform

The various components of OTFS modulation include the 2D OTFS transform, as shown in FIG. 4. OTFS QAM symbols are defined over a grid in the Delay-Doppler domain. As described previously, the 2D OTFS transform translates every point on this Delay-Doppler plane into a corresponding basis function that covers the entire Time-Frequency plane. Thus OTFS QAM symbols are transformed onto a grid representing sample points in the Time-Frequency domain and the energy of each QAM symbol is spread over the Time-Frequency domain. Recall that this is the same grid over which OFDM QAM symbols (or any of its filtered multi-carrier variants) are defined.

1.5.1 The Symplectic Finite Fourier Transform

The first step in the modulation of the QAM symbols is the 2D OTFS transform. This is given by a variant of the 2D FFT called the Symplectic Finite Fourier Transform (SFFT), defined as

$\begin{array}{c}X\left(k,l\right)=\mathrm{SFFT}\left\{x\left(m,n\right)\right\}\\ =\sum _{m=0}^{M-1}\sum _{N=0}^{N-1}x\left(m,n\right)b_{m,n}\left(k,l\right)\end{array}{b}_{m,n}\left(k,l\right)=e^{-\mathrm{j2}\pi \left(\frac{\mathrm{lm}}{M}-\frac{\mathrm{kn}}{N}\right)}$

Where x(m, n) are the QAM symbols in the Delay-Doppler domain, b_m,n(k, l) are the basis functions associated with the [m, n]th QAM symbol in the Time-Frequency domain (with time and frequency indexed by k and l, respectively), and M and N are the number of points in the Delay and Doppler dimensions, respectively. Alternatively, M is equivalent to the number of subcarriers and N to the number of multi-carrier symbols. Notice that the Symplectic Fourier Transform differs from the more well-known Cartesian Fourier Transform in that the exponential functions across each of the two dimensions have opposing signs and the coordinates are flipped in the two domains. This is necessary as it matches the behavior of the Delay-Doppler channel representation relative to the time-varying frequency response representation of the channel.

To visualize the 2D basis functions, consider the continuous time representations of the Delay-Doppler and Time-Frequency domains. In FIG. 5, a point in the Delay-Doppler domain on the left, indexed by [τ₀, v₀] is transformed to a multiplication of two linear phases in the Time-Frequency domain on the right, where the frequency of the exponential in the ‘time’ dimension is given by the Doppler index, v₀, and the frequency of the exponential in the ‘frequency’ dimension is given by the Delay index, τ₀.

To summarize the initial step in the modulation process:

• • QAM symbols are placed on a grid in the Delay-Doppler domain.
  • Through the Symplectic Fourier Transform, each QAM symbol multiplies a 2D basis function defined in the Time-Frequency domain.
  • The Time-Frequency signal is a superposition of multiple QAM symbols weighting the 2D basis functions.
  • The energy of each symbol is spread across the signal bandwidth and OTFS symbol time.

At the receiver, the corresponding final demodulation step is the Inverse Symplectic Finite Fourier Transform, given by

$x\left(m,n\right)=\sum _{l=0}^{M-1}\sum _{k=0}^{N-1}X\left(k,l\right)b_{m,n}^{*}\left(k,l\right)b_{m,n}^{*}\left(k,l\right)=e^{\mathrm{j2}\pi \left(\frac{\mathrm{lm}}{M}-\frac{\mathrm{kn}}{N}\right)}$

1.5.2 Example of the OTFS Window

In some embodiments, the basis functions, X(k, l) are doubly periodic with period [N, M], or equivalently, as seen in FIG. 6, they are defined on a torus discretely sampled with M and N points in each dimension. The basis functions extend infinitely in frequency and time and are thus windowed at the transmitter with a 2D shaping window, W_tr[k, l], in order to restrict the available transmission bandwidth and time. This window multiplies the modulation symbols in the Time-Frequency domain. A trivial window example is the rectangular window W_tr[k, l]=1 for all k=0, . . . , N−1, l=0, . . . , M−1 and zero elsewhere. Since the signal in this domain is periodic, the window can be applied in any region of the domain without loss of information.

The signal in the Time-Frequency domain is thus given byΘ(k,l)=W_tr[k,l]·SFFT{x(m,n)}

The window in general could extend beyond the period of the information symbols [N, M] and could have a shape different from a rectangular pulse. This would be akin to adding cyclic prefix/suffix in the dimensions of both time and frequency with or without shaping. The choice of window has implications on the shape and resolution of the channel response in the information domain. In some embodiments, the OTFS window also enables the multiplexing of traffic to or from multiple users.

2 Examples of NB-LDPC Codes in OTFS Systems

In some digital communication systems, low density parity check (LDPC) error correction is used. While “textbook” LDPC can provide good performance that is close to the well-known Shannon limit, for practical reasons, real implementations often use sub-optimal LDPC such as repeat-accumulate techniques for implementing LDPC. As a result, the error floor seen in these implementations is of the order of 10⁻⁵ to 10′. In applications that require better performance, an outer code such as ReeD Solomon code or BCH code is used. The use of outer code increases the complexity and latency of an implementation.

The non-binary LDPC codes described in the present document can be used in embodiments in which an extremely low error floor (10⁻¹¹ or 10⁻¹²) can be achieved. Due to the formulation of an H matrix that includes non-binary entries, as further described herein, the H matrix provides better permutations, thereby lessening error triggering events, thus resulting in superior performance.

In addition, the disclosed non-binary LDPC codes are especially useful in orthogonal time frequency space (OTFS) modulation based communication systems. Certain error correction codes such as LDPC are known to provide better results on AWGN channels (as compared to fading channels). Due to the property that a symbol in OTFS is spread over the entire channel spectrum, the impairment due to channel is averaged and the resulting error statistics looks more like AWGN, thus making LDPC implementations particularly suitable for OTFS modulation.

FIG. 7 depicts an example of a system 700 utilizing a non-binary LDPC code, in accordance with some example embodiments. The system 700 includes data source 710 which can include a data source to be sent over a wired or wireless radio frequency or optical communications system, or data associated with a device such as a disk drive. In the example of a disk drive, the data may include data to be written by a write head to cause magnetic changes on a magnetic disk. Data source 710 is provided to LDPC encoder 720. The LDPC encoder 720 includes the non-binary LDPC encoder. The encoded data from LDPC encoder 720 is provided to a transmitter including a modulator. For example, the encoded data may be provided to an orthogonal time frequency space (OTFS) modulator and transmitter 730. In another example, the encoded data may be provided to a magnetic write head of a disk drive. The transmitted signal (or signal written to disk) is passed over a transmission medium 740 which can include, for example, air for wireless RF or optical signals, wire, optical fiber, or other medium. Transmission medium 740 can also include a magnetic platter of a magnetic click drive. After passing through transmission medium 740, the signal is received. For example, an RF or optical signal may be received by OTFS receiver 750. In another example, the receiver may be a read head of a magnetic disk drive. After reception, the received signal may be passed through a log likelihood ratio computer 760, followed by a LDPC decoder (e.g., a non-binary LDPC decoder). After decoding, the data is provided to a data sink 770.

Exemplary embodiments of NB-LDPC codes in OTFS systems are described in the following subsections.

2.1 Terms and Definitions

Definition: Let be a set of objects on which two operations ‘+’ and x′ are defined. is said to be a field if and only if (iff):

1. forms a commutative group under ‘+’. The additive identity element is ‘0’.

2. \ {0}−(read as: take away 0) (the set with the additive identity removed) forms a commutative group under ‘×’. The multiplicative identity element is ‘1’.

3. The operations ‘+’ and ‘×’ distribute: a×(b+c)=(a×b)+(a×c).

A field can also be defined as a commutative ring with identity in which every element has a multiplicative inverse.

Example: Rational numbers form one of the ‘infintite fields’.

Example: The real numbers form another infinite field, and so do the complex numbers.

Example: The integers do not form a field, for most of the integers do not have an integer multiplicative inverse.

Definition: Fields of finite order are known as Galois fields. A Galois field of order q is denoted as GF(q). Examples of GF(2) and GF(7) are given in Tables 2.1, 2.2, 2.3, and 2.4.

TABLE 2.1
(2)-Addition
	+	0	1
	0	0	1
	1	1	0

TABLE 2.2
(2)-Multiplication
	×	0	1
	0	0	0
	1	0	1

TABLE 2.3
(7)-Addition
	+	0	1	2	3	4	5	6
	0	0	1	2	3	4	5	6
	1	1	2	3	4	5	6	0
	2	2	3	4	5	6	0	1
	3	3	4	5	6	0	1	2
	4	4	5	6	0	1	2	3
	5	5	6	0	1	2	3	4
	6	6	0	1	2	3	4	5

TABLE 2.4
(7)-Multiplication
+	0	1	2	3	4	5	6
0	0	0	0	0	0	0	0
1	0	1	2	3	4	5	6
2	0	2	4	6	1	3	5
3	0	3	6	2	5	1	4
4	0	4	1	5	2	6	3
5	0	5	3	1	6	4	2
6	0	6	5	4	3	2	1

TABLE 2.5
+	0	1	2	3
0	0	1	2	3
1	1	0	3	2
2	2	3	0	1
3	3	2	1	0

TABLE 2.6
×	0	1	2	3
0	0	0	0	0
1	0	1	2	3
2	0	2	3	1
3	0	3	1	2

Example Tables 2.5 and 2.6 describe the ‘+’ and ‘×’ operations of (2²). Since the rules of addition and multiplication are not straightforward, it is best to implement it in the hardware using two dimensional look up tables. In a simple implementations, two tables each of size q² would be required for this for this purpose. However, this memory requirement can be brought down to q.

Linear Block Codes. A block error control code C consists of a set of M code words {c₀, c₁, c₂ . . . , c_M-1}. Each code word is of the form c_i=(c₀, c₁ . . . c_n-1); if the individual coordinates take on values from the Galois Field GF(q), then the code C is said to be q-ary. C is a q-ary linear code of length n iff C forms a vector sub space over the vector space V consisting of all n-tuples of GF(q).

Let {g₀, g₁, . . . , g_k-1} be a basis of the code words for the (n,k) q-ary code C. There exists a unique representation c=a₀g₀+a₁g₁+ . . . +a_k-1g_k-1 for every code word c_i∈C. Since every linear combination of the basis elements must also be a code word, there is a one-to-one mapping between the sets of k-symbols (a₀, a₁, . . . , a_k-1) over GF(q) and the code words in C. A generator matrix G can be constructed by taking as its rows the vectors in the basis.

$\begin{array}{cc}G=\left[\begin{array}{c}{g}_0\\ g_1\\ ⋮\\ g_{k-1}\end{array}\right]=\left[\begin{array}{c}{g}_{0,0},g_{0,1},\dots ,g_{0,n-1}\\ g_{1,0},g_{1,1},\dots ,g_{1,n-1}\\ ⋮\\ g_{k-1,0},g_{k-1,1},\dots ,g_{k-1,n-1}\end{array}\right]& \left(\mathrm{Equation}2.1\right)\end{array}$ G can be used to directly encode k-symbol data blocks in the following manner. Let m=(m₀, m₁, . . . , m_k-1) be a q-ary block of un-coded data.

$\begin{array}{cc}\mathrm{mG}=\left(m_0,m_1,\dots ,m_{k-1}\right)\left[\begin{array}{c}{g}_0\\ g_1\\ ⋮\\ g_{k-1}\end{array}\right]=m_0{g}_0+m_1{g}_1+\dots ,m_{k-1}{g}_{k-1}+=c& \left(\mathrm{Equation}2.2\right)\end{array}$

As discussed, a q-ary code C of length n forms a vector sub space of dimension k, within the vector space V of all n-tuples over GF(q). Given this, we can talk about the dual space of C within V. Two sub spaces, S and S^⊥ of the vector space V are dual to each other if for all a e S and b∈S^⊥, a·b=0. The dual space of a linear code is called the dual code of C. It is denoted by C^⊥. It is a vector space of dimension n−k. It follows that a basis {h₀, h₁, . . . h_n-k-1} for C^⊥ can be found. This is used to construct a parity-check matrix H.

$\begin{array}{cc}H=\left[\begin{array}{c}{h}_0\\ h_1\\ ⋮\\ h_{k-1}\end{array}\right]=\left[\begin{array}{c}{h}_{0,0},h_{0,1},\dots ,h_{0,n-1}\\ h_{1,0},h_{1,1},\dots ,h_{1,n-1}\\ ⋮\\ h_{k-1,0},h_{k-1,1},\dots ,g_{k-1,n-1}\end{array}\right]& \left(\mathrm{Equation}2.3\right)\end{array}$

For every c∈C, cH^T=0. Similarly if cH^T=0, c is a code word. It follows that GH^T=0.

Using Gaussian elimination and column reordering on a linear code C with a generator matrix G, it is always possible to obtain a generator matrix of the form in Eq. 2.4.

$\begin{array}{cc}G\left[I_k❘P_{n-k}\right]=\left[\begin{array}{c}1,0,\dots ,0❘p_{0,0},p_{0,1},\dots ,p_{0,n-1}\\ 0,1,\dots ,0❘p_{1,0},p_{1,1},\dots ,p_{1,n-1}\\ ⋮\\ 0,0,\dots ,1❘p_{k-1,0},p_{k-1,1},\dots ,p_{k-1,n-k-1}\end{array}\text{⁠}\right]& \left(\mathrm{Equation}2.4\right)\end{array}$ When a data block is encoded using G, the data block is embedded without modification in the first k coordinates of the resulting code word. This is called systematic encoding.

$\begin{array}{cc}\begin{array}{c}c=\mathrm{mG}\\ =\left[m_0,m_1,\dots ,m_{k-1}\right]\left[I_k❘P\right]\\ =\left[m_0,m_1,\dots ,m_{k-1},c_0,c_1,\dots ,c_{n-k-1}\right]\end{array}& \left(\mathrm{Equation}2.5\right)\end{array}$

After decoding, the first k symbols are removed from the selected code word and passed along to the data sink.

Given a systematic generator matrix of the form Eq. 2.4, a corresponding parity check matrix can be obtained as:

$\begin{array}{cc}H=\left[-P^T❘I_{n-k}\right]=\left[\text{⁠}\begin{array}{c}-p_{0,0}-p_{0,1},\dots ,-p_{k-1,0}❘1,0,\dots ,0\\ -p_{0,1}-p_{1,1},\dots ,-p_{k-1,1}❘0,1,\dots ,0\\ ⋮\\ -p_{0,n-k-1},-p_{1,n-k-1},\dots ,-p_{k-1,n-k-1}❘0,0,\dots ,1\end{array}\text{⁠}\right]& \left(\mathrm{Equation}2.6\right)\end{array}$

Circulant Matrix: An n×n circulant matrix C takes the form:

$\begin{array}{cc}C=\left[\begin{array}{ccccc}{c}_0& c_{n-1}& \dots & c_2& c_1\\ c_1& c_0& c_{n-1}& & c_2\\ ⋮& c_1& c_0& \ddots & ⋮\\ c_{n-2}& & \ddots & \ddots & c_{n-1}\\ c_{n-1}& c_{n-2}& \dots & c_1& c_0\end{array}\right]& \left(\mathrm{Equation}2.7\right)\end{array}$

A circulant matrix is fully specified by one vector, c, which appears as the first column of C. The remaining columns of C are each cyclic permutations of the vector c with offset equal to the column index. The last row of C is the vector c in reverse order, and the remaining rows are each cyclic permutations of the last row. In the context of non-binary LDPC codes, a typical circulant matrix will have the following form:

$\begin{array}{cc}C=\left[\begin{array}{ccccc}c1& 0& \dots & 0& 0\\ 0& c2& \dots & 0& \\ ⋮& 0& c3& \ddots & ⋮\\ 0& & \ddots & \ddots & 0\\ 0& 0& \dots & 0& \mathrm{cn}\end{array}\right].& \left(\mathrm{Equation}2.8\right)\end{array}$

Permutation Matrix: The permutation matrix P_π corresponding to the permutation:

$\begin{array}{cc}\pi =\left(\begin{array}{ccccc}1& 2& 3& 4& 5\\ 1& 4& 2& 5& 3\end{array}\right),\mathrm{is},& \left(\mathrm{Equation}2.9\right)\\ P_{\pi }=\left[\begin{array}{c}{e}_{\pi \left(1\right)}\\ e_{\pi \left(2\right)}\\ e_{\pi \left(3\right)}\\ e_{\pi \left(4\right)}\\ e_{\pi \left(5\right)}\end{array}\right]=\left[\begin{array}{c}{e}_1\\ e_2\\ e_3\\ e_4\\ e_5\end{array}\right]=\left[\begin{array}{ccccc}1& 0& 0& 0& 0\\ 0& 0& 0& 1& 0\\ 0& 1& 0& 0& 0\\ 0& 0& 0& 0& 1\\ 0& 0& 1& 0& 0\end{array}\right].& \left(\mathrm{Equation}2.1\right)\end{array}$

In the context of non-binary LDPC codes, the non-zero elements can, in general, be different.

2.2 Quasi-Cyclic Codes

Let b, k, and t be positive integers such that k<tb. A (tb, k) linear code C_qc over GF (2^m) is called a quasi-cyclic code when: 1) Each code word in C_qc consists of t sections of b bits each; and 2) every t-sectioned cyclic-shift of a codeword in C_qc is also a codeword in C_qc. Such a QC code is called a t-section QC code.

Regular Codes: If the number of non-zero elements in each column of the H matrix is same, we call it a regular code. On the other hand, if the weights of the columns differ, then its called irregular code.

2.3 A Priori, A Posteriori, and Extrinsic Probabilities

There are several types of probabilities that can be associated with a random variable, x. For the event {x=a_k}, suppose that E is an event whose effect on the variable x is under question. The prior probability refers to the probability P (x=a_k) that the variable x takes the value a_k. It is also known as the intrinsic probability. The prior/intrinsic probability for the variable x with respect to the event E is denoted as P_E^int (x=a)=P (x=a). The posterior (a posteriori) probability is the conditional probability for random variable x with respect to event E is denoted as P_E^post (x=a)=P (x=a|E). The intrinsic and posterior probabilities represent the probability before and after taking into account the event E. Using Bayes' rule, the posterior probability can be written as:

$\begin{array}{cc}\stackrel{\mathrm{posterior}}{\overbrace{P\left(x=a❘E\right)}}=\frac{1}{P\left(E\right)}\stackrel{\mathrm{prop}.\mathrm{to}\mathrm{extrinsic}}{\overbrace{P\left(E❘x=a\right)}}\stackrel{\mathrm{intrinsic}}{\overbrace{P\left(x=a\right)}}& \left(\mathrm{Equation}2.11\right)\end{array}$

The term P (x=a) is the intrinsic probability; the term P (E|x=a) is proportional to the ‘extrinsic’ probability, which is the probability that describes the new information for x that has been obtained from the event E. The extrinsic probability for x with respect to E is defined by, P_E^ext (x=a)=c_x′P (E|x=a) where c′ is the normalization constant.

These terms will come up again when we discuss the messages passed in the sum-product algorithm.

2.4 Graphical Representation of LDPC Codes

Block codes, such as LDPC codes, can be represented using bipartite graphs known as Tanner Graphs. This is best illustrated with an example. The Tanner graph for the parity check matrix H in (Equation 2.12) is shown in FIG. 8. There are N=6 variable nodes (circles), where each one corresponds to a different column of H or a different symbol in the code word. There are M=3 check nodes (squares) in the graph, where each corresponds to a different row in H or a different parity check equation.

$\begin{array}{cc}H=\left(\begin{array}{cccccc}{h}_{11}& h_{12}& 0& h_{14}& 0& 0\\ 0& h_{22}& h_{23}& 0& h_{25}& 0\\ h_{31}& 0& h_{33}& 0& 0& h_{36}\end{array}\right)& \left(\mathrm{Equation}2.12\right)\end{array}$

The reliability of each variable node (the variable node's belief that it takes on each of its possible values, which is a conditional probability distribution or LLR) is initialized from the received symbols (after equalization, so it is assumed that soft information about each variable is an independent piece of information). In the sum-product algorithm (SPA), or message passing algorithm, this reliability information is refined by being passed back and forth between variable nodes and check (constraint) nodes iteratively. In each iteration, the information (hopefully) becomes more reliable.

The a priori, or intrinsic, information associated with a node is the information known about it before the decoding starts. For a variable node, this is the information from the received symbols from the channel. The extrinsic information associated with a node a is the information provided by the decoder except for the information provided by node a. The a posteriori information for node a is all of the information provided by the decoder without removing the information provided by node a. This is the information that a variable node will use to make a final decision on its value.

2.5 NB-LDPC Code Construction and Encoding

Building a decoder for a generic LDPC code is not viable in hardware. It would require an enormous amount of wiring and silicon. For this reason, commercial LDPC implementations use a special class of codes known as Quasi Cyclic (QC) LDPC codes. Decoder architecture for QC binary and non-binary (NB) codes are simple to implement. QC-binary systematic encoders can be implemented using simple shift-registers with linear complexity owing to a QC-Generator matrix. However, a QC-non-binary encoder does not entail, in general, a QC-G matrix and so would require quadratic complexity. However, for short/medium length codes, such as some of the example embodiments disclosed here, encoder complexity is not of prime concern currently.

Two examples of the disclosed subject matter include LDPC codes a) structured regular systematic repeat accumulate codes (RA codes) over the non-binary, structures (qⁿ) and b) codes that are created out of just permutation matrices. Code/H-matrix designs for a) are based on computer search whereas b) are based on analytic (Euclidean geometry) techniques. Both these methods are described in the sequel.

2.5.1 Design of Structured Regular Repeat Accumulate (RRA) Codes

Construction of a parity check matrix, H, for a non-binary RRA (regular repeat accumulate) code consists of two parts; 1) construct the binary-H matrix and 2) convert it to non-binary.

2.5.2 Construction of the Binary-H Matrix Based on Computer Search

Parity check matrix for RRA code is given by, H=[H₁, H₂], where H₁ is the parity part and H₂ is the systematic part. Both H₁ and H₂ are composed of blocks of circulant permutation matrices and zero matrices of block size Q. There are Q different possibilities for each block/sub-matrix. Each block can be fully specified by an exponent that denotes the number of right shifts required for the non-zero element of the first row. For example, an exponent of 0 denotes an identity sub-matrix of size Q. The distinct exponents can thus be 0, 1 . . . (Q−1). An all-zero block is denoted with an exponent of −1 (or 16, at times). The parity part, H₁, includes circulant permutation blocks while the systematic part, H₂ is square and double diagonal on the block level, meaning that each Q-sized block in H₂ consists of identity elements on its main and lower diagonal, and zero blocks elsewhere.

Henceforth the methodology by which H₁ can be constructed to contain no four-cycles in its Tanner graph is discussed. Four cycles can be formed either internal to H₁ or between H₁ and H₂. The method for reducing the amount of six-cycles is mentioned as well, although our application total removal of 6-cycles may not be feasible.

Let L be the number of Q-sized block rows and J be the number of block columns in H₁. From the definition of RRA, the number of block columns in H₂ is J. N, the number of columns in [H₁, H₂], is N=(L+J)Q. A necessary and sufficient condition for removing 4-cycles for any configuration of rectangle abcd below (note that a, b, c, d are block circulant matrices as described previously) is given by,

$\begin{array}{cc}\left(\begin{array}{ccccc}& ⋮& ⋮& ⋮& \\ \dots & a& \dots & b& \dots \\ & ⋮& \ddots & ⋮& \\ \dots & c& \dots & d& \dots \\ & ⋮& ⋮& ⋮& \end{array}\right)a-c\ne b-d\left(\mathrm{mod}Q\right)& \left(\mathrm{Equation}3.1\right)\end{array}$

Now offsetting column (a,c) by X and column (b,d) by Y (offsets are mod Q), as well as row (a,b) by D and row (c,d) by E. The transformation results inaa+X+D cc+X+E bb+Y+D dd+Y+E  (Equation 3.2)and the new equation is(a+X+D)−(c+X+E)≠(b+Y+D)−(d+Y+E)⇒(a+D)—(c+E)≠(b+D)−(d+E)⇒a−≠b−d  (Equation 3.3)

This shows that the rectangle rule is invariant under constant offsets to entire rows or columns. Therefore, without loss of generality, we can add offsets such that the first row and the first column consist of identity sub-matrices (‘0’ exponent blocks). By exploiting this property the search space for solutions is decreased. Having the first row and first column exponents as 0 implies that each row and each column must contain unique values lest a 4-cycle be formed. Note that, a 6-cycle will be formed with the first row and column if a≡d (mod Q).

The algorithm used to design the H matrix works as follows: Let W be an array containing all ones, [1,1 . . . 1], of length Q. Let it denote the inclusion of numbers {0 . . . (Q−1)} in a given set, say A. That is W=[1,1, . . . 1] implies A={0,1, . . . 15}. As another example, let W=[1,0,1,1,0,1,1,1,1,1,0,0,0,1,1,1]. This implies that A={0,2,3,5,6,7,8,9,13,14,15}. Similarly for other values of W.

Recall that the first row and column of H₁ are preselected to have 0 exponents. Starting with index (2,2) of H₁, and working row-wise (or column-wise, since the rules are invariant under transposition), solve for the set of possible exponent values for each index of H₁ that will form 4-cycles. This is done as follows: For each index, compare it with all slots with indexes less than its own, such that the current index is d and the one it is compared with is a, with b and c found to form the rectangle. Solve Equation 3.1 (recall a, b, c are known values) to find the value of d that will form a 4-cycle. Remove this value from A by suitably modifying W.

After this process, two situations may arise. Either there is at least one option for d, in which case pick one at random, or there are no options, in which case the run is aborted and the process must be restarted. If a matrix is successfully generated, it is passed into a function that runs a quick check to make sure that it indeed does pass the conditions for no 4-cycles, as well as counts the number of instances of a a≡d (mod Q) to get a metric for the amount of 6-cycles.

In some example embodiments, the following choices may be made: N=256, Q=16, and L=1 . . . 8, J=15 . . . 8. High rate codes,

$\left(R=\frac{J}{L+J}\right)$ such as 15/16, 14/16 will have low number of layers (1 and 2). This is undesirable due to the low degree of H₁. This is especially so for 15/16 where the degree is equal to 1, rendering the code ineffective. Simulation results of these codes and ensuing discussions are detailed below.

Good high rate codes may be designed by increasing the number of layers. Since J must be increased by the same proportion as L to keep the rate fixed, N=(L+J)Q has to increase for a given constant value of Q. However, increasing N will cause greater latency and hardware resources. Since each row and column must contain unique values (prior to adding an offset of one to even rows), Q≥J is necessary to eliminate 4-cycles.

Relation between Code Rate (R), Number of Layers (L), sub-matrix Size (Q), Code Size (N) are depicted in Table 3.1.

TABLE 3.1
N for a choice of {L,R} for 4-cycle free H
R	1	2	3	4	5	6
8/16	256~	256~	258~	256~	260~	264~
9/16	—	—	—	—	—	—
10/16	—	—	256~	—	—	256*
11/10	—	—	—	—	256*	—
12/16	256~	256~	264~	256*	320	456
13/16	—	—	256*	—	—	864
14/16	256~	256*	528∧	928	1440	2064
15/16	256*	992	2208	3904	6080	8736
		R	7	8	9	10
		8/16	266~	256*	270∧	260∧
		9/16	256*	—	—	—
		10/16	—	—	384∧	—
		11/10	—	—	—	736
		12/16	616∧	800	1908	1240
		13/16	—	—	1920	—
		14/16	2800	3648	4608	5680
		15/16	11872	15488	19584	24160

Wherever there are no entries in Table 3.1, it implies that there is no solution existing using this algorithm. For example, for a 9/16 code, the only possible value of N is 256 and so on. Entries in the table with * indicates example embodiments. Entries with ˜ indicates there are better alternative parameters possible for the given value of N. Entries with {circumflex over ( )} denote 256≤N≤640.

As can be seen in Table 3.1, there is no solution for R=15/16, L>1, N≤640. Only one possible other option exists for R=14/16, none other exist for R=13/16 and several possibilities exist for R=12/16.

2.5.3 Conversion of Binary-H Matrix to Non-Binary H

Currently the elements in a sub-matrix are chosen at random. However, this has to be changed to maximize the entropy. This is done as follows: Say we have a code that has M=N−K=16. We have 16 entries in the syndrome vector. Consider the 1st entry; by maximizing the entropy of the bit/symbol at that location.

The LDPC encoder belongs to the transmit chain, and it sits between the scrambler and the data/symbol mapper, as shown in FIG. 9. The LDPC encoder always gets its input data from the scrambler, even if the RS encoder is bypassed. The LDPC encoder may be bypassed if only the RS code is being used, and the LDPC encoder handles this case internally.

The LDPC encoder encodes the output of the scrambler whether or not the RS code is not being used. It takes a k-symbol message vector and encodes it into an n-symbol codeword vector (n>m). This adds structured redundancy that the LDPC decoder can exploit to correct errors in the codeword caused by the channel. For this reason, the encoder comes before the data is mapped to constellation symbols and modulated

2.6 Example Architectures for Non-Binary LDPC Codes

The architecture must be able to implement any of the codes from the set {8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16, 15/16}. Switching between code rates should be able to happen from frame to frame. The encoder must support shortened codewords in the form of “zero stuffing” and must support zero padding.

At the top level, the LDPC encoder has four components: (1) the top controller, (2) the input interface to the scrambler, (3) the core, and (4) the Tx interface at the output. The signals and connections between the blocks are shown in FIG. 10.

The top controller controls switching between normal encoding operation, zero stuffing operation, and zero padding operation based on configuration registers that set the number of information bytes per frame, the number of zero to stuff/pad, and whether to stuff or pad if the number of zeros is larger than 0. It also controls the ready signal that goes to frame buffer FSM and times it so that the information symbols coming into the encoder pause at the correct time

The input interface converts the 8-bit output from the scrambler to a 32-bit input for the LDPC encoder and pulses a valid signal when the 32-bits are ready. During the last codeword of the frame and if zero stuffing is enabled, zeros may be appended to the input in order to make up a full codeword. These zeros are not part of the information, so they must be removed before the codeword is written to the Tx FIFO in the output interface.

The core stores the information symbols from the input interface in a memory, encodes the information when enough information symbols have been stored (the number depends on the code rate), and outputs a 512-bit codeword 32-bits (16 symbols) at a time. It also raises a valid signal concurrently with each 32-bit codeword segment.

The Tx interface is an asynchronous FIFO that accepts a 32-bit input and a concurrent data valid signal and reads out between 2 and 10 valid bits depending on the current QAM constellation used by the modulator. During the last codeword and if zero stuffing is enabled, zeros added in the input interface must be removed.

2.6.1 Core Operation

As shown in FIG. 11, the LDPC encoder core is broken up into five components: (1) the I memory, (2) the G memory, (3) the submatrix processing unit (SPU), (4) the read out registers, and (5) the core controller. The I memory holds the information symbols, the G memory holds the submatrices of the G matrix, and the SPU computes the matrix multiplication of a parity submatrix and the corresponding portion of the message vector. There are two SPUs that are resource-shared, but more could be added if necessary (e.g., if the codes change in the future). The choice for two SPUs is based on meeting the latency constraint.

The I memory is a ping-pong memory where the scrambler writes into one memory and the LDPC encoder reads from the other memory. The memory to write to and read from is controlled by the LDPC encoder's controller. The scrambler supplies the write data and data valid signals, and the LDPC encoder provides the write address, read address, and the memory select signals. The memory width is 32 because an entire submatrix's worth of information symbols is read out every cycle (z=16, and log 2(q)=2, so the total width is 32). The memory depth is 15 since the highest rate code has 15 block rows in its generator matrix. The other code rates will not use the full depth of the memory.

The G memory is a ROM that stores the submatrices for all G matrices (all code rates) so that it can switch between matrices quickly by just changing an offset to the read address that puts its first read at the desired matrix's first address (FIG. 12A). Each row of the G memory stores all elements corresponding to one submatrix of a G matrix, and the order that the submatrix is stored in the G memory is shown in FIG. 12B.

The width of the ROM is calculated as n_SPU·z²·log₂ q, where n_SPU is the number of SPUs in the architecture (here n_SPU=2, so the width is 1024). The depth is set as the sum of the depth required by each matrix and the depth of each matrix is the number of block rows in the matrix multiplied by the number of groups of block columns, which is the number of block columns in P divided by n_SPU rounded up to the nearest integer (FIG. 12C). When n_SPU does not divide the number of block columns in P, some SPUs will not produce a useful output because they are extra for that computation. In that case, the G memory entries for those block columns are set to all zeros.

A single SPU computes one submatrix multiply operation (one miPi term in the sum in Equation 2.2) every clock cycle. FIG. 13 shows an example of a submatrix processing unit. The partial results for each block row are accumulated serially to find the overall parity symbols for the block column. Since every row in Pi is unique, all rows must be stored in a single word of the G memory. The kth element of the result (where k is between 1 and 16) is found by multiplying each information symbol by the corresponding element in the ith column of the submatrix and adding them (the correspondence between the submatrix element and the memory bit positions is given in FIG. 12B). Therefore, the SPU multiplies each information symbol by each generator row element and adds the appropriate elements together to form the submatrix multiply result. The results are saved in an accumulation register whose output is also added with the rest of the information symbol-generator symbol products. A multiplexer resets the accumulation result to zero when a new block column is started. In the SPU, the signals are 2-bits wide except the 32-bit wide signal from the G memory.

The controller generates all read addresses for the I and G memories, the memory select signal for the I memory, the signal that resets the running sum in the SPUs when a new set of block columns is processed, and the ready signal that controls the frame buffer FSM that feeds information symbols to the RS encoder and scrambler. The controller keeps track of the number of writes to the I memory and the status of the encoder (based on the number of block column sets supplied by configuration registers and the cycle count) to indicate whether the encoder is ready for more data to be written to the I memory and which memory to should be written.

Operation of the encoder includes the following:

• • 1. The scrambler buffers information symbols into the I memory with a high ready signal.
  • 2. Every cycle the encoder reads one entry from the I memory that is not being written.
  • 3. For the first set of block columns, the information symbols are also sent to the read out registers. This is the correct behavior because the code is systematic and the information symbols appear in the codeword in the same order as they are input to the encoder.
  • 4. The 2 SPUs serially compute the submatrix multiplications for the information symbols read from the I memory and store the partial results in registers. Note that two block columns are processed simultaneously.
  • 5. After the last block row in a set of block columns is processed, the results are sent to the read out registers and are serially shifted out (note on the last set of block columns, the last_parity_valid_string signal is used to generate the parity_valid signal since not all SPUs may have a valid output since there may be extras if the block column size is not divisible by the number of SPUs)
  • 6. The SPUs start processing the next set of block columns by reading the next entries from the G memory as normal but also setting the reset_running_sum signal high.
  • 7. When the encoder finishes processing the last set of block columns, it checks to see if there is another set of information symbols ready in the I memory. If so, it starts encoding the next codeword. If not, it pauses until another codeword is buffered.

2.7 Examples of Decoding NB-LDPC Codes

The message passing equations detailing how to process the reliability information at the variable nodes and check nodes is detailed below.

Linear Combinations of RVs over Finite Algebraic Structures: Consider the discrete random variable x∈GF (q), which can take on values in the set {0,1, . . . , q−1}. It has a probability mass function (PMF) P (x) given byP(x)={(P(x=0)=p₀),(P(x=1)=p₁), . . . ,(P(x=q−1)=p_q−1)}  (Equation 4.1)where p₀, p₁, . . . , p_q-1 sum to 1. The question is: what is P (h×x) where h∈GF (q)?

In other words, we are asking for each of the probabilities P(h×x=0), P(h×x=1), . . . , P (h×x=q−1). Rearranging these terms:

$\begin{array}{cc}\begin{array}{c}P\left(h\times x=0\right)P\left(x=h^{-1}\times 0\right)\\ P\left(h\times x=1\right)P\left(x=h^{-1}\times 1\right)\\ ⋮\\ P\left(h\times x=q-1\right)P\left(x=h^{-1}\times \left(q-1\right)\right)\end{array}& \left(\mathrm{Equation}4.2\right)\end{array}$

In general P(h×x=r)⇒P (x=h⁻¹×r). Note that h⁻¹×{0,1, . . . , q−1} results just in reordering (shuffle) of the set {0,1, 2, . . . , q−1} by virtue of the closure property of the field multiplication. Thus we see that P (h×x) is a shuffle of the elements of the vector/PMF P (x) by h⁻¹. The exact shuffle depends on the primitive polynomial that was used to build the field GF (q), which sets the multiplication table for the field.

Now, consider the following check equation, where all elements are from GF (q):h₁×x₁+h₂×x₂+h₃×x₃=0  (Equation 4.3)

Each x_i has vector of probabilities, one for each of its possible values, where all elements sum to 1. Now let us ask the question: Given the above relation/constraint between x₁, x₂ and x₃, what is the distribution of x₁, given the distributions of x₂ and x₃?

From a Galois field Fourier transform, for y, s, t, ∈GF (q), if y=s+t, the distribution of y will be the finite field convolution of the distributions of s and t. In this way, the distribution of x₁ can be found as detailed below. From Equation 4.3:−h₁×x₁=h₂x x₂+h₃×x₃  (Equation 4.4)The distribution of −h₁×x₁ in the above equation, thus, will be the finite field convolution of the distributions of h₂×x₂ (a shuffle of the distribution of x₂ by h₂⁻¹) and that h₃×x₃ (a shuffle of the distribution of x₃ by h₃⁻¹). Note that −h₁ (viz. the additive inverse of h₁) is the same as h₁ in finite fields of the form GF (2ⁿ). So the distribution of x₁ is obtained by shuffling the result of the above convolution by (h₁⁻¹)⁻¹=h₁.

There is another way of looking at the above equation. This interpretation will be appreciated later when we deal with the mixed-mode sum-product algorithm (SPA). Equation 4.4 can be re-written for finite fields (note that the negative sign is dropped, which presumes we are in a field of the form GF (2^m)) asx₁=h₁⁻¹×h₂×x₂+h₁⁻¹×h₃×x₃  (Equation 4.5)From Equation 4.5, the distribution of x₁ is obtained in two steps: (a) shuffle the distributions of x₂ by h₁×h₂⁻¹ and x₃ by h₁×h₁⁻¹, and (b) take the (finite field) convolution of the shuffled distributions.

Moving from the Linear to the Log Domain based on a Linear Combination of Two Random Variables: Consider the discrete random variable x∈GF (2). The log likelihood ration (LLR) of x, LLR(x), is a scalar defined as:

$\begin{array}{cc}\mathrm{LLR}\left(x\right)={\log }_e\left(\frac{P\left(x=1\right)}{P\left(x=0\right)}\right).& \left(\mathrm{Equation}4.6\right)\end{array}$ Now consider the discrete random variable y∈GF (2²). The LLR of y, (LLR(y)), is a vector of length 2²−1=3. It is defined as:

$\begin{array}{cc}\mathrm{LLR}\left(y\right)=\left[{\log }_e\left(\frac{P\left(x=1\right)}{P\left(x=0\right)}\right),{\log }_e\left(\frac{P\left(x=2\right)}{P\left(x=0\right)}\right),{\log }_e\left(\frac{P\left(x=3\right)}{P\left(x=0\right)}\right)\right].& \left(\mathrm{Equation}4.7\right)\end{array}$ The LLR for elements from higher order fields can be defined similarly with q−1 elements in the LLR vector.

Let us now address the question: Given the LLR vectors of x₁ and x₂, how can we compute the LLR vector of h₁×x₁+h₂×x₂ where (h₁, h₂∈GF(4))? To answer this, consider an element, α_i∈GF(q) (i.e. α_i∈GF (4) can take values {0,1,2,3}). Then,

$\begin{array}{cc}\mathrm{LLR}=\left(h_1\times x_1+h_2\times x_2={\alpha }_i\right)& \left(\mathrm{Equation}4.8\right)\end{array}$ $\begin{array}{cc}\equiv \ln \frac{P\left(h_1\times x_1+h_2\times x_2={\alpha }_i\right)}{P\left(h_1\times x_1+h_2\times x_2=0\right)}& \left(\mathrm{Equation}4.9\right)\end{array}$ $=\ln \frac{\sum _{v\in \mathrm{GF}\left(q\right)}\frac{P\left(x_1=v\right)P\left(x_2=h_2^{-1}\times \left({\alpha }_i-h_1\times v\right)\right)}{P\left(x_1=0\right)P\left(x_2=0\right)}}{\sum _{v\in \mathrm{GF}\left(q\right)}\frac{P\left(x_1=v\right)P\left(x_2=-h_2^{-1}\times h_{1}v\right)}{P\left(x_1=0\right)P\left(x_2=0\right)}}$ $=\ln \left[\left(e^{{\mathrm{LLR}}_1\left(h_1^{-1}\times {\alpha }_i\right)}+e^{{\mathrm{LLR}}_2\left(h_2^{-1}\times {\alpha }_i\right)}+\sum _{v\in \mathrm{GF}\left(q\right)\backslash \left\{0,h_1^{-1}\times {\alpha }_i\right\}}{e}^{\left[{\mathrm{LLR}}_1\left(v\right)+{\mathrm{LLR}}_2\left(h_2^{-1}\times \left({\alpha }_i-h_1\times v\right)\right)\right]}\right)\right]-\ln \left(1+\sum _{v\in \mathrm{GF}\left(q\right)\text{[}0]}{e}^{\left[{\mathrm{LLR}}_1\left(v\right)+{\mathrm{LLR}}_2\left(h_2^{-1}\times \left(-h_1\times v\right)\right)\right]}\right)$ LLR₁(v) corresponds to the LLR value of x₁ at x₁=v, and similarly for LLR₂ (v). The notation v∈GF (q)\{0, h₁⁻¹×α_i} denotes that v takes all the values in GF (q) except {0,h₁⁻¹×α_i}. The second equality is obtained by dividing the top and bottom terms by P (x₁=0)·P (x₂=0) and by expanding the sums inside the P(·)s to account for all events in which the sum is true. The third equality comes from expanding the numerator and denominator and separating the log of the division into a difference of logs. Equation 4.8 can be used for each value of α_i (for a total of q−1 times) to calculate each element of the LLR vector LLR (h₁×x₁+h₂×x₂) and thus obtain the entire LLR vector of h₁×x₁+h₂×x₂.

As has been detailed, in (·), (α_i−h₁×v) is (α_i−h₁×v)_(·) and (h₂⁻¹×(−h₁×v)) is (h₂⁻¹×(h₁×v))_(·). In the following, the subscripts indicating the algebraic structure will be omitted for clarity.

Consider α∈GF (4). α takes value 0,1,2,3. Let h₁=2 and h₂=3. From Table 2.6, h₁⁻¹=3 and h₂⁻¹=2. Therefore,

$\begin{array}{cc}\begin{array}{c}\mathrm{LLR}\left(h_1·x_1+h_2·x_2=0\right)=0\\ \mathrm{LLR}\left(h_1·x_1+h_2·x_2=1\right)=\ln [e^{{\mathrm{LLR}}_1\left(3\times 1\right)}+e^{{\mathrm{LLR}}_2\left(2\times 1\right)}+\\ (e^{{\mathrm{LLR}}_1\left(v=1\right)+{\mathrm{LLR}}_2\left(2\times \left(1-2\times 1\right)\right)]}+\\ e^{\left[{\mathrm{LLR}}_1\left(v=2\right)+{\mathrm{LLR}}_2\left(2\times \left(1-2\times 2\right)\right)\right]})]-\\ \ln [1+e^{{\mathrm{LLR}}_1\left(v=1\right)+{\mathrm{LLR}}_2\left(2\times \left(2\times 1\right)\right)]}+\\ e^{\left[{\mathrm{LLR}}_1\left(v=2\right)+{\mathrm{LLR}}_3\left(2\times \left(2\times 2\right)\right)\right]}+\\ e^{\left[{\mathrm{LLR}}_1\left(v=3\right)+{\mathrm{LLR}}_3\left(2\times \left(2\times 3\right)\right)\right]}.\end{array}& \left(\mathrm{Equation}4.1\right)\end{array}$ Similarly, we can compute, LLR(h₁×x₁+h₂×x₂=2) and LLR(h₁×x₁+h₂×x₂=3).

Linear Combination of n Random Variables: Once again, consider the following check equation,h₁x₁+h₂x₂+h₃x₃+h₄x₄=0  (Equation 4.11)Where h₁, . . . , h₄, x₁, . . . , x₄ are elements from GF (q). Next, define σ and ρ as:σ₁=h₁x₁,ρ₁=h₁x₁+h₂x₂+h₃x₃+h₄x₄ σ₂=h₁x₁+h₂x₂,ρ₂=h₂x₂+h₃x₃+h₄x₄ σ₃=h₁x₁+h₂x₂+h₃x₃,ρ₃=h₃x₃+h₄x₄ σ₄=h₁x₁+h₂x₂+h₃x₃+h₄x₄,ρ₄=h₄x₄  (Equation 4.12)which can be re-written as,σ₁=h₁x₁,ρ₁=h₁x₁+ρ₂ σ₂=σ₁+h₂x₂,ρ₂=h₂x₂+ρ₃ σ₃=σ₂+h₃x₃,ρ₃=h₃x₃+ρ₄ σ₄=σ₃+h₄x₄,ρ₄=h₄x₄  (Equation 4.13)In accordance with the foregoing description, the probability distributions of each b and each p can be computed recursively using convolutions in the linear domain, and LLR vectors of σ₁, σ₂ . . . σ_n-1 and ρ₁, ρ₂ . . . ρ_n-1 can be computed recursively using Equation 4.10 in the log domain. The σ computations represent a forward recursion, and the ρ computations represent a backward recursion. This is a very efficient method to compute these values. However, the band p quantities are not the LLR vectors of the x₁s. Therefore, the question is how can we compute the LLR vectors LLR(x₁), LLR(x₂), LLR(x₃), LLR(x₄) from the LLR vectors of σs . . . and ρs?

As discussed earlier, LLR(x₁), is the shuffle of LLR(σ₁) by (h₁⁻¹)⁻¹=h₁. Note that this is true because we are shuffling by the inverse h₁⁻¹ and the value to shuffle by is the inverse of the shuffle value. LLR(x₄) can similarly be obtained from LLR(σ₄). (4.11) can be written in terms of σs' and ρs' as below.σ₁+h₂x₂+ρ₃  (Equation 4.14)ρ₂+h₃x₃+σ₄  (Equation 4.15)Therefore,σ₁+ρ₃=−h₂x₂  (Equation 4.16)σ₂+ρ₄=−h₃x₃  (Equation 4.17)

Using Equation 4.10 we can obtain LLR(σ₁+ρ₃), LLR(x₂) is obtained by shuffling this distribution by (−h₂⁻¹)⁻¹=h₂ (in GF(2^m), but differs in GF(p^m) where ρ is a prime not equal to 2 and ∈(·)). Similarly proceeding we can obtain LLR(x₃).

This idea can be generalized for obtaining LLR(x_i) for i=1 . . . N.

Methods to Calculate max*: Computation of max*(x,y)=ln(e^x+e^y) is an important component finding the linear combination of RVs in the log domain. To see options for its calculation, consider the Jacobian logarithm:

$\begin{array}{cc}\begin{array}{c}{\max \left(x,y\right)}^{*}=\ln \left(e^x+e^y\right)\\ =\max \left(x,y\right)+\ln \left(1+e^{-❘x-y❘}\right)\end{array}& \left(\mathrm{Equation}4.18\right)\end{array}$ The second equality can be found by assuming x>y and factoring out e^x and then doing the same assuming y>x.

FIG. 14 shows a plot of log(1+e^−|x−|). As can be seen, a comparator and a look up table with eight |x−y| values (sampled at □ points below) from the above graph can implement max(x,y)* with an approximate quantization noise of +/−0.05. This can be realized in hardware as shown in FIG. 15A, assuming D units of clocks and R units of hardware resources.

An implementation of the same is also considered as shown in FIG. 15B. Let us denote D_app units of clocks and R_app units of hardware resources are used for its implementation.

Now consider a 3-input max* (max₃*) as given by Equation 4.19. This enables us a low resource high delay implementation of max₃* as given in FIG. 15C. control-1 in FIG. 15C selects one of the inputs to the max₂* block. At the first cycle (beginning), input x and y are selected as inputs to max₂*; in the subsequent cycle, the output of the current operation and input variable z are selected. The final output from the max₂* is registered using control-2.

$\begin{array}{cc}\begin{array}{c}{\max }^{*}\left(x,y,z\right)=\ln \left(e^x+e^y+e^z\right)\\ =\ln \left(e^x+e^{\ln \left(e^y+e^z\right)}\right)\\ ={\max }^{*}\left[x,\ln \left(e^y+e^z\right)\right]\\ ={\max }^{*}\left[x,{\max }^{*}\left(y,z\right)\right].\end{array}& \left(\mathrm{Equation}4.19\right)\end{array}$

An approximate implementation of the same can be achieved similarly by concatenating FIG. 15B appropriately.

In general,max*(x₁,x₂,x₃, . . . x_n)=max*[x₁ max*(x₂ max*(x₃,max*(x₄. . . x_n−2,max*(x_n−1,x_n)]  (Equation 4.20)

Following the architecture given in FIG. 15C, Equation 4.20 can be implemented. This would use (N−1)×D units of clocks to complete this operation but would use approximately only 1×R hardware resources. This implementation is referred as the serial implementation and is denoted as max_N*.

Now consider the four input max* as below,

$\begin{array}{cc}\begin{array}{c}{\max }^{*}\left(x,y,z,w\right)=\ln \left(e^x+e^y+e^z+e^w\right)\\ =\ln \left(e^{\ln \left(e^z+e^y\right)}+e^{\ln \left(e^z+e^w\right)}\right)\\ =\ln \left(e^{{\max }^{*}\left(x,y\right)}+e^{{\max }^{*}\left(z,w\right)}\right)\\ ={\max }^{*}\left({\max }^{*}\left(y,z\right),{\max }^{*}\left(z,w\right)\right)\end{array}& \left(\mathrm{Equation}4.21\right)\end{array}$

Equation 4.21 points to a parallel architecture (high resource but low delay) for the implementation of max₄* as given in FIG. 15D.

A parallel implementation for max* with N (power of 2) elements (max_N*), will use N−1 max₂* elements and would use log N₂ units of clocks.

Message passing equations from variable to check messages: There are at least two types of messages passed in the SPA: from variable nodes to check nodes (V2C) and check nodes to variable nodes (C2V). First, let us look at the V2C messages. The variable node basically enforces a constraint that all incoming messages to it should agree on its probability of taking on each value. FIG. 16 depicts a variable node (marked with an “=” sign due to its equality constraint) with incoming messages indicating what different nodes in the graph the variable node's probability of taking on each of its values is.

Suppose that the variable node N is connected to K+1 edges with associated nodes x₀, x₁, . . . , x_k. The constraint set for this node is: S_N={(x₀, x₁, . . . , x_k)|(x₀=x₁=x₂ . . . =x_k=v1)}. Let P(x₁=v₁), P(x₂=v₁)·P(x_k=v₁) represent the probabilities of x₁, x₂, . . . , x_k to take the value v₁. Now, the probability of the output variable of the node x₀ to take value v₁ is given by

$\begin{array}{cc}P\left(x_0=v_1\right)=c^{\prime }\times P\left(x_1=v_1\right)\times P\left(x_2=v_1\right)\times \dots \times P\left(x_k=v_1\right)=c^{\prime }\times \stackrel{i=k}{\prod _{i=1}}P\left(x_i=v_1\right)& \left(\mathrm{Equation}4.22\right)\end{array}$ where c′ is a normalization constant that ensures Σ_v∈GF(q)P(x₀=v)=1.

In the log domain, Equation 4.22 becomes

$\begin{array}{cc}\begin{array}{c}\mathrm{LLR}\left(x_0\right)=\ln \frac{p\left(x_0=v_1\right)}{p\left(x_0=0\right)}\\ =\ln \frac{\stackrel{i=k}{\prod _{i=1}}P\left(x_i=v_1\right)}{\stackrel{i=k}{\prod _{i=1}}P\left(x_i=0\right)}\\ =\stackrel{i=k}{\sum _{i=1}}\mathrm{LLR}\left(x_i=v_1\right)\end{array}& \left(\mathrm{Equation}4.23\right)\end{array}$ Note that no normalization constant is needed here. In summary, for an equality node, the outgoing LLR along one edge is the sum of the incoming LLRs along all of the other edges.

Check to Variable Messages: Similar to variable nodes enforcing an equality constraint on incoming messages, check nodes enforce a parity check constraint defined by a row of the parity check matrix H. A parity constant states that a linear combination of variables must equal a particular value (usually 0), such as in the following:h_i,1×v_i,1+h_i,2+ . . . +h_i,k×v_i,k=0  (Equation 4.24)

In the context of the SPA, the k edges entering a check node represent probabilities that the variable node on the other side of the edge takes on each of its possible values. When viewed as k−1 incoming edges and 1 outgoing edge, the k−1 incoming edges and the parity check equation that must be satisfied are used to calculate the probability/LLR vector of the variable node attached to the outgoing edge (note that the outgoing variable node's message is not used). Intuitively, the probability that the node attached to the outgoing edge takes on a value α_i is equal to the probability that nodes attached to the incoming edge sum to the additive inverse of α_i, −α_i (in the case of GF(2^m), α_i=−α_i). To actually calculate the probability/LLR vector of the k^th variable node, the equations derived in earlier sections are used.

In particular, the forward/backward recursion is done using all incoming messages to the check node to calculate each a and p, and then the appropriate σ, ρ LLR vectors are “added” (where added means the operation defined in (4.6) or (4.10)) to form each variable's C2V message.

Tanner Graph and Message Passing: A pictorial representation of the above using Tanner graphs is shown in FIG. 17. As shown therein, C2V1,1 represents the probability that VN1=a1 given the current probabilities of VN4 and VN5 taking on particular values and the entries in the H matrix that permute the probabilities. V2C1,1 represents the probability that VN1=a1 given the C2Vs of neighboring CNs other than CN1.

2.8 Examples of NB-LDPC Decoder Architectures

Layered SPA: The LDPC decoder belongs to the receive chain, and it sits between the Slicer/LLR Computer and the Reed-Solomon (RS) Decoder (FIG. 18). The RS decoder may be bypassed if only the LDPC code is being used, in which case the LDPC decoder passes the data directly to the descrambler. The LDPC decoder can also be bypassed, in which case the RS decoder gets data directly from the Slicer and sends the data to the descrambler. Similarly, they can both be bypassed which allows the data to be sent un-coded.

There are two different options when it comes to decoding algorithms. A flooding type algorithm where each variable node and check node pass information iteratively until convergence and a layered algorithm where only a subset of variable and check nodes pass information iteratively until convergence. In this example implementation the layered algorithm is implemented. It is more easily implemented in hardware and converges faster.

2.8.1 Examples of Partially Parallel Architectures for NB-Decoding Using Layered Schedule

FIG. 19 depicts the architecture for decoding one data that is associated with one circulant sub-matrix of size Q. In this example realization circulant matrix size is taken to be 16×16. The decoder is broken up into seven main components: (1) the variable node (VN), (2) the quasi-cyclic router (qc_router), (3) the LLR permuter (llr_shift), (4) the check node (CN), (5) the recursion controller (recurs_ctrlr), (6) the mapper from LLR values to bits (llr_slicer), and (7) the LDPC Syndrome Computer (synd_computer).

Decoding operation begins with the LLR values coming from the LLR computer (described in section 5). VNs receive this a priori LLR values for each of the VNs and initialize the Q memory with these values. V2C messages are calculated. In the first iteration they are just the initial a priori LLR values). In general, V2C messages are calculated as follows: (Q_new=Q_old+R_new−R_old). C2V messages are responsible for the R values both old and new are used to calculate the extrinsic Q values. After all of the iterations and layers have completed, these Q values (without subtracting the old R values) are sent to the LLR Slicer to be transformed into bits.

A Variable Node (VN), also referred to as the bit node, initially receives the a priori LLR values from the LLR computer. These values initialize the Q memory before any extrinsic or a posterior LLR values have been computed. The VN provides the V2C messages that allow for the CN to calculate the calculate the σ, ρ, and R values which are required in order to calculate the a posterior LLR values. The final LLR values are stored in the Q Memory and ultimately end up in the LLR slicer for conversion from LLRs to bits.

The Quasi-Cyclic Router (QC_ROUTER) takes in as inputs the current submatrix to provide the routing requirements for the given submatrix that is being processed. The QC Router is implemented using a series of mux stages in order to route the inputs to the correct outputs.

The LLR Permuter (LLR_SHIFT) takes in as inputs the current set of 3 LLRs and permutes them based on the input hi,j element. For example, the hi,j element (which is an element of GF(4) {1,2,3} only nonzero values are considered) could be 3. The GF(4) inverse of 3 is 2, so this would permute the incoming LLRs by 2 shifts such that {LLR1, LLR2, LLR3} would become {LLR3, LLR1, LLR2}. The architecture of the LLR Permuter is also known as LLR_Shift.

The Check Node (CN) is used for the computation of σ and ρ, the forward and backward recursion respectively, and ultimately, the computation of R. R is essentially the set of LLR a posterior values for a given code symbol and its value is iterated on until the decoder is complete. The final R values will ultimately end up at the VN where the final Q values will be calculated. The input to the CN is the extrinsic LLR values that are computed by subtracting the new Q values with the previous R values as explained earlier. Internally, the CN will store the previous extrinsic information and that will be used to calculate the new R values. This process will continue until all layers and iterations have completed. The value of the row weight will determine the number of variable nodes that each check node sends a message to. The Check Node is comprised of two elementary check nodes (ECN) to parallelize the σ, ρ, and R calculations.

The Elementary Check Node (ECN) is the building block for the Check Node. Its purpose is to calculate the following equation:

$\ln \left(e^{{\mathrm{LLR}}_1\left(0\right)}+e^{{\mathrm{LLR}}_1\left(h_1^{-1}{\alpha }_i\right)}+e^{{\mathrm{LLR}}_2\left(h_2^{-1}{\alpha }_i\right)}+e^{{\mathrm{LLR}}_2\left(0\right)}\right)+\ln \left(\sum _{v\in \mathrm{GF}\left(q\right)\backslash \left\{0,h_1^{-1}{\alpha }_i\right\}}{e}^{\left[{\mathrm{LLR}}_1\left(v\right)+{\mathrm{LLR}}_2\left(h_2^{-1}\left({\alpha }_i-h_{1}v\right)\right)\right]}\right)-\ln \left(1+\sum _{v\in \mathrm{GF}\left(q\right)\backslash \left\{0\right\}}{e}^{\left[{\mathrm{LLR}}_1\left(v\right)+{\mathrm{LLR}}_2\left(h_2^{-1}\left(-h_{1}v\right)\right)\right]}\right)$

Herein. the above equation may be interpreted as three separate equations, one for each value of α.

Due to the LLR permuters before and after the CN, all values of h and h⁻¹ are equal to 1 since 1 is the inverse of 1 in GF(4). This simplification makes the computation of all the different combinations much less hardware intensive. The Elementary Check Node architecture is shown in FIG. 20.

In this architecture, all combinations of LLR additions are created and sent to the correct max* operation depending on α. The max* operation is in its own module due to the need to approximate it as simply a max operation. Currently it is implemented as purely a max operation but can be quickly adapted to any variety of approximations.

In some embodiments, σ is computed as (given by Eq. 4.12) in the forward recursion. while ρ is computed in the backward (Eq. 4.12) recursion, and R (Eq. 4.8) is computed using σ and ρ, as shown below and with a pictorial representation of it given in FIG. 21.

$\left(“\mathrm{add}\left(\mathrm{eq}.4.8\right)”+\mathrm{shuffle}\right)\mathrm{for}R{R}_{i,1}=h_{i,1}^{-1}{p}_{l-1}{R}_{i,2}=h_{i,2}^{-1}\left({\sigma }_1+p_{l-2}\right)⋮R_{i,l}=h_{i,l}^{-1}{\sigma }_{l-1}$

2.8.2 Log Likelihood Ratio Computer

Received symbols from the equalizer prior to slicing can be represented as,y(k)=γ_kx(k)+n(k)  (Equation 5.1)where y(k) is the received QAM symbol, x(k) is the transmitted QAM symbol, γ_k is a channel quality measure (relative attenuation/fading the transmitted symbol have experienced) and n(k) is Additive White Gaussian Noise (AWGN). In OFDM systems, for example, due to fading, certain sub-carriers undergo erasure and γ_k can be thought of as a quantity inversely related to the intensity of erasure. In OTFS systems, the fading is absent and here we assume γ_k to be always 1.

We use LDPC codes in GF(4). Thus we have 2 bits per each LDPC symbol. LDPC decoder requires a measure of reliability for each symbol, viz. LLR of all the 2²−1 bit sequences to perform the soft decoding (equation 4.7). This can be calculated in two ways, a) symbol wise and b) bit wise. Symbol-wise LLR computation is applicable to even order constellations (QAM4, QAM16, QAM64, QAM256 etc.) whereas bit-wise LLR computer may be used for both even and odd order constellations (QAM4, QAM8, QAM16, QAM32, . . . )

LDPC symbol-wise LLR computer: Consider a QAM constellation. Each constellation point consists of say dR number of bits. For e.g., dR=6 for QAM64 and so on. Now, consider a set with c number of consecutive bits in this constellation. Let's say c=2. then we have 3 such sets associated with each QAM64 symbol (first, middle and last). Consider one such set. It can take 2^c(2²=4 in our example) distinct values in general. Let us assume that one of the constellation points, say, x was transmitted. Let us say y was received. y can fall anywhere on the constellation plane. Out of the 2dR constellation points, let there be a number of constellation points where these c bit positions of x are identical (s^(c)=x₁x₂ . . . x_c) where s is the LDPC symbol). Let there be β number of constellation points where these c bit positions are a 0 (s^(c)=0₁0₂ . . . (·)0_c).

Since we assume AWGN in Equation 5.1, we get,P(x(k)=(k))=a/y(k))=(K/σ)×e^{−(y(k)−a)2/(2σ2)}  (Equation 5.2)where K is a constant and σ² is the noise variance.

From above, LLRs can be written as,

$\begin{array}{cc}\mathrm{LLR}\left(s^{\left(c\right)}=x_1{x}_2\dots x_c\right)=\ln \left[\frac{\sum _{i=1}^{\alpha }P\left(s^{\left(c\right)}=x_1{x}_2\dots x_c\right)/y\left(k\right)}{\sum _{i=1}^{\beta }P\left(s^{\left(c\right)}=0_1{0}_2\dots 0_c\right)/y\left(k\right)}\right]& \left(\mathrm{Equation}5.3\right)\end{array}$

An LLR vector is computed by computing Equation 5.3 for all combinations of x₁x₂ . . . x_c. (Thus there are a total of 2^c−1 number of LLRs in a LLR vector.)

From Equation 5.2, this can be seen to be of the form,

$\begin{array}{cc}\begin{array}{c}\mathrm{LLR}\left(s^{\left(c\right)}=x_1{x}_2\dots x_c\right)=\ln \left[e^{p_1}+e^{p_2}+\dots +e^{p_{\alpha }}\right]-\\ \ln \left[e^{q_1}+e^{q_2}+\dots +e^{q_{\beta }}\right]\\ \approx \ln \left[\underset{i}{\max \left(e^{p_i}\right)}\right]-\ln \left[\underset{i}{\max \left(e^{q_i}\right)}\right]\end{array}& \left(\mathrm{Equation}5.4\right)\end{array}$

For higher order modulations, α and β in the above expression are prohibitively expensive. So, for computational tractability, we limit the search space to a few salient constellation points determined by the position of the current received symbol y(k). This approximation translates to only using the closest constellation points that has s^(c)=x₁x₂ . . . x_c and s^(c)=0₁0₂ . . . 0_c in the computation of LLR(s^(c)=x₁x₂ . . . x_c), and has yielded good results in a gray coded constellation.

FIG. 22A depicts an example of a 16-QAM constellation. The constellation is divided into Quadrants Q1, Q2, Q3 and Q4. Each of them is further sub-divided into QQ1, QQ2, QQ3 and QQ4 as shown in FIG. 22B. Consider a received QAM symbol in Q1-QQ2 as shown by the triangle (solid triangle in upper right quadrant of FIG. 22A). Under low to medium noise conditions, the transmit symbol could be any of the 4 constellation points in Q1 or Q2-QQ1 or Q2-QQ4 or Q4-QQ2 or Q4-QQ1. Now consider the 4 constellation points in Q1. The upper 2 bits of these points do not change within Q1. The lower two bits take values 00, 01, 10 and 11 (marked with a blue circle (four circles around values 00, 01, 10, 11)). It can be seen that incorrect transitions to Q2-QQ1 or Q2-QQ4 or Q4-QQ2 or Q4-QQ1 will not affect the correctness of decoding of the lower two bits. Thus for the two lower bits, distances marked in blue are a measure of reliability. That is, the received QAM symbol will have the lower two bits mapped to the bit pair which has the lowest distance among the 4 (bits 10 in the figure). LLRs of the two lower bits of the received symbol, is thus given by the normalized distances viz. 0, d1−d0, d2−d0, d3−d0 (where d0, d1, d2 and d3 are the distances to the lower two bits—00, 01, 10 and 11—given by the arrows in the figure). Now consider the upper two bits (circles in the figure). Note that they do not change within Q1. The nearest points to a likely transition to 00, 01, 10 and 11 for the upper two bits are shown by the red circles. LLRs of these two bits can be computed exactly as above.

Bit-wise LLR computer: To find LLR(s^(c)=x₁x₂ . . . x_c), we can, instead, look at the LLRs of individual bits and combine them to get the required LLR of a certain group of bits.

For example, the LLR for the previous example is recalculated bit-wise, as shown in FIG. 22B. Proceeding as in the previous example, from the figure, we can see that LLR(s⁽¹⁾)=a2−a, LLR(s⁽²⁾)=a−b2, LLR(s⁽³⁾)=c2−a and LLR(s⁽⁴⁾)=d2−a, where s⁽¹⁾ corresponds to the rightmost bit in the constellation point.

From the definition of LLRs, we know that P(s⁽¹⁾=1)=P(s⁽¹⁾=0)×e^LLR(s(1)). Therefore, LLR(s^(c)) can be calculated from individual-bit LLRs as below:

$\begin{array}{cc}\mathrm{LLR}\left(s^{\left(c\right)}=11\right)=\ln \left[\frac{P\left(s^{\left(1\right)}=0\right)\times P\left(s^{\left(2\right)}=0\right)\times e^{\mathrm{LLR}\left(s^{\left(1\right)}\right)+\mathrm{LLR}\left(s^{\left(2\right)}\right)}}{P\left(s^{\left(1\right)}=0\right)\times P\left(s^{\left(2\right)}=0\right)}\right]=\sum _{i=1}^2\mathrm{LLR}\left(s^{\left(i\right)}\right)& \left(\mathrm{Equation}5.5\right)\end{array}$

Computing similarly we can see that, LLR(s^(c)=10)=LLR(s⁽²⁾)−0, LLR(s^(c)=01)=0+LLR(s⁽¹⁾) and LLR(s^(c)=00)=0+0.

LLR computation described thus, works for both odd and even order constellation whereas the symbol-wise LLR computer works only for even order constellations.

Conversion between symbol-wise and bit-wise LLRs: Given a finite sequence of bits:{b₁,b₂, . . . ,b_n}≡{b_i}  (Equation 5.6)Each bit has an associated probability, P(b_i=1),P(b_i=0) where P(b_i=1)+P(b_i=0)=1. Since the bits are assumed to be independent, then

$\begin{array}{cc}P\left(\left[b_1,b_2,\dots ,b_n\right]=\left[v_1,v_2,\dots ,v_n\right]\right)=\prod _{i=1}^{n}P\left(b_i=v_i\right)& \left(\mathrm{Equation}5.7\right)\end{array}$

Every sequence of bits that b_i can be represented with an unsigned integer (e.g., 3=‘10’). Let P(k) denote the probability that b_i takes the form of the sequence of bits which is the binary representation of the unsigned integer k (i.e., k=b(1)×2⁰+b(2)×2¹+ . . . b(n)×2ⁿ⁻¹). Using this notation, LLR vector of size n sequence (of bits) is:

$\begin{array}{cc}\mathrm{LLR}=\log \left(\frac{\left[P\left(1\right),P\left(2\right),P\left(3\right),\dots ,P\left(2^n-1\right),\right]}{P\left(0\right)}\right)& \left(\mathrm{Equation}5.8\right)\end{array}$

As expected, this LLR vector is of size 2ⁿ−1. Another way to represent this LLR vector is by individually describing each element.

$\begin{array}{cc}{\mathrm{LLR}}_k=\log \left(\frac{P\left(k\right)}{P\left(0\right)}\right)& \left(\mathrm{Equation}5.9\right)\\ {\mathrm{LLR}}_k=\log \left(\frac{\prod _{i=1}^{n}P\left(b_i=k\left[i\right]\right)}{\prod _{i=1}^{n}P\left(b_i=0\right)}\right)& \left(\mathrm{Equation}5.1\right)\\ {\mathrm{LLR}}_k=\log \left(\prod _{i=1}^n\frac{P\left(b_i=k\left[i\right]\right)}{P\left(b_i=0\right)}\right)& \left(\mathrm{Equation}5.11\right)\\ {\mathrm{LLR}}_k=\sum _{i=1}^n\log \left(\frac{P\left(b_i=k\left[i\right]\right)}{P\left(b_i=0\right)}\right)& \left(\mathrm{Equation}5.12\right)\\ {\mathrm{LLR}}_k=\sum _{i=1}^{n}k\left[i\right]\log \left(\frac{P\left(b_i=1\right)}{P\left(b_i=0\right)}\right)& \left(\mathrm{Equation}5.13\right)\end{array}$ Where k[i] denotes the ith bit in the binary representation of the unsigned integer k. Since k|i| can either be 0 or 1, in the case where it is 0 it cancels out with the denominator. We now see the resemblance of an LLR of an individual bit, represented by LLR(b_i) as the LLR of bit b_i:

$\begin{array}{cc}\mathrm{LLR}\left(b_i\right)=\log \left(\frac{P\left(b_i=1\right)}{P\left(b_i=0\right)}\right)& \left(\mathrm{Equation}5.14\right)\\ {\mathrm{LLR}}_k=\sum _{i=1}^{n}k\left[i\right]\mathrm{LLR}\left(b_i\right)& \left(\mathrm{Equation}5.15\right)\end{array}$ In summary, it has been found that

$\begin{array}{cc}{\mathrm{LLR}}_k=\log \left(\frac{P\left(k\right)}{P\left(0\right)}\right)=\sum _{i=1}^{n}k\left[i\right]\mathrm{LLR}\left(b_i\right)& \left(\mathrm{Equation}5.16\right)\end{array}$ if and only if the sequence of bits b_i is independent. Thus a length 2ⁿ−1 LLR vector can be represented with n bit-wise LLRs. In particular, if (LDPC) symbols consist of 2 bits, then a symbol-wise LLR will have three elements: (a, b, c). This result shows that the bits are independent if and only if a+b=c.

LLR calculation: Given a constellation with an associated bit pattern, it can be converted into two tables containing the individual bits (see below, for example):

For each such table of bits, given a soft decision point (output of the equalizer), a single bit LLR can be calculated using:

1) Find the distance to the nearest point containing a 0, let this distance be d₀.

2) Find the distance to the nearest point containing a 1, let this distance be d₁.LLR=d₀²−d₁²  (Equation 5.18).

3) Check to see if this makes sense—if very close to 1, then much farther from 0, and d₀²>d₁², meaning that the LLR will be positive. If we are very close to 0 and far from 1, then the LLR will be negative, as expected with the convention that

$\begin{array}{cc}{\mathrm{LLR}}_k=\log \left(\frac{P\left(k\right)}{P\left(0\right)}\right).& \left(\mathrm{Equation}5.19\right)\end{array}$

In some embodiments, if the constellation bit pattern obeys a regular symmetry (as do the even constellations) then simple computation can be done to deduce the closest 0 point and closest 1 point. If, on the other hand, the constellation bit-pattern does not have such a symmetry, a look-up table based technique is be used to find these points. The look-up table, with finite number of elements, in some cases will work as an approximation to the direct computation (and thus would be not as exact as the direct computation)

In some embodiments, hardware supports symbol-wise LLR computer.

LLR computer Architecture: As shown in FIG. 23, LLR computer receives a) the soft-symbol estimates in (tau, nu) domain from the Decision Feed back equalizer and b) hard symbol estimates from the slicer. The LLR computer outputs a set of LLR values corresponding to each soft estimate. LLR values goes as input to the LDPC decoder.

LLR computer: Even order constellations has even number of bits in each symbol. Each LDPC symbol in GF(4) consists of 2 bits. Each such symbol will have 4 neighbors. Thus in the case of 4-QAM there's only one set of neighbors, in the case of 16-QAM there are 2 sets of neighbors and so on up to 1024-QAM in which case there are 5 sets of neighbors. Each set of 4 neighbors is used to calculate 4 Euclidean distances between the neighbors and the input soft estimate, resulting in sets of 4 such distances which in fact represent LLRs. One such LLR corresponds to the LDPC symbol ‘00’. This LLR will be subtracted from the other 3, (the normalization of LLR). These 3 normalized LLRs will then be sent to the LDPC Decoder to be processed.

The Euclidean distances between the signal y=y_I+jy_Q and a point of the constellation n=n_I+jn_Q are calculated as follows:∥y−n∥²=(y_I−n_I)²+(y_Q−_Q)₂  (Equation 5.20).

A block diagram of the algorithm described above shown in FIG. 23.

The hard decisions from the Slicer (signal s), together with the respective QAM order are used to derive the addresses to a ROM that contains all the “neighbors” associated with every point in all the square QAM constellations.

To calculate the ROM allocated for each constellation, the following may be used:

• • 4-QAM: there are 4 points, each with 1 set of 4 neighbors, so its allocated memory should be 1 block of 4 words.
  • 16-QAM: there are 16 points, each with 2 sets of 4 neighbors, so its allocated memory should be 2 blocks of 16 words each.
  • 64-QAM: there are 64 points, each with 3 sets of 4 neighbors, so its allocated memory should be 3 blocks of 64 words each.
  • 256-QAM: there are 256 points, each with 4 sets of 4 neighbors, so its allocated memory should be 4 blocks of 256 words each.
  • 1024-QAM: there are 1024 points, each with 5 sets of 4 neighbors, so its allocated memory should be 5 blocks of 1024 words each.

3 Exemplary Methods for NB-LDPC Coding in OTFS Systems

FIG. 24 shows an example of a method 2400 for forward error correction in wireless systems. The method 2400 includes, at step 2410, receiving information bits. The information bits may be received from applications or users and may be intended for transmission over the transmission medium of the wireless system.

The method 2400 includes, at step 2420, encoding the information bits via a non-binary low density parity check code, which can be formulated as a matrix with binary and non-binary entries. Section 2 of the present document provides examples of the matrix representation of the NB-LDPC code.

The method 2400 includes, at step 2430, modulating the encoded information bits to generate a signal. In some embodiments, the modulating is performed in accordance with orthogonal time frequency space (OTFS) modulation. In other embodiments, the modulating is performed in accordance with orthogonal frequency division multiplexing (OFDM).

The method 2400 includes, at step 2440, transmitting the signal over a channel. As previously discussed, one advantageous aspect of the use of NB-LDPC is to both use the AWGN statistical properties of noise ingress and also use the low complexity implementation of NB-LDPC to achieve very low BER performance. In particular, because OTFS modulation spreads a symbols over the entire bandwidth of the channel, frequency localized noise ingress still does not degrade performance of NB-LDPC, due to “averaging” or “whitening” effect over the entire bandwidth of the symbol.

In some embodiments, transmitting the signal includes transmitting a radio frequency signal over the air or a wire. In other embodiments, transmitting the signal includes transmitting an optical signal over a fiber optic cable.

FIG. 25 shows another example of a method 2500 for forward error correction in wired or wireless systems. The method 2500 includes, at step 2510, receiving a signal. The signal may be received by a wired or wireless device that is communicating with other devices in the wireless system. The received signal may be modulated using OFDM or OTFS modulation and may include user and control data transmitted by a transmitter. In some embodiments, receiving the signal includes receiving a radio frequency signal over the air or a wire. In other embodiments, receiving the signal includes receiving an optical signal over a fiber optic cable.

The method 2500 includes, at step 2520, demodulating the received signal to produce data. In some embodiments, the demodulating is performed in accordance with orthogonal time frequency space (OTFS) modulation. In other embodiments, the demodulating is performed in accordance with orthogonal frequency division multiplexing (OFDM).

The method 2500 includes, at step 2530, decoding the data via a non-binary low density parity check decoder, which is characterized by a matrix with binary and non-binary entries.

The method 2500 includes, at step 2540, providing the decoded data to a data sink. The data sink may be, for example, applications and services running on the wired or wireless device that receives the signal.

4 Example Embodiments for the Disclosed Technology

FIG. 26 shows an example of an apparatus, in accordance with some example embodiments. The apparatus 2600 may be used to implement methods 2400 and 2500 and/or the processes in the following sections. The apparatus 2600 includes a processor 2602, a memory 2604 that stores processor-executable instructions and data during computations performed by the processor. The apparatus 2600 includes reception and/or transmission circuitry 2606 including, for example, radio frequency or optical operations for receiving or transmitting signals, or read/write heads of a magnetic disk drive.

Aspects disclosed in this patent document include a forward error correction method, including encoding and decoding data which using a non-binary LDPC error correction code. Non-binary LDPC error correction code may be transmitted and received over a wireless or wireline medium, or used in devices such as disk drives. Encoded data may be further modulated using OTFS or OFDM or other modulation. An encoder H matrix is described. The H matrix may be found via a search methodology including the removing of 4 cycles and 6 cycles, followed by interleaving and choosing non-binary values for the circulant matrix. The error floor of a non-binary LDPC code found using this methodology to determine an H matrix has very low error flow far below other codes. A single H matrix may be used to generate punctured codes with a variety of rates such 8/16, 9/16, . . . , 15/16, and others where each code rate is derived from the same H matrix An architecture for the above is disclosed including a partially parallel architecture for the decoder. Compared to binary LDPC, a modified permuter may be used. An architecture for decoding the NB LDPC layered SPA (sum product algorithm) modified for non-binary use and architecture. Two different forms of max* computation are disclosed (the serial and parallel) in the decoder and their architecture. Max* is a modified version for a NB-Code. Normalization of the log likelihood ratio is disclosed. LDPC symbol-wise normalized LLR computation methodology is disclosed. LDPC bit-wise normalized LLR computation methodology is disclosed and an architecture is disclosed.

Various example embodiments of the above-described LDPC encoder and decoder operation may be described using a clause-based description format as follows:

1. A forward error correction method performed at a receiver, comprising: receiving, over a channel, a signal that is modulated using an orthogonal time frequency space (OTFS) or an orthogonal frequency division multiplexing (OFDM) modulation scheme, demodulating the received signal to produce data; decoding the data via a non-binary low density parity check (NB-LDPC) code, by formulating the NB-LDPC code as a matrix with binary and non-binary entries; and providing the decoded data to a data sink.

2. The method of clause 1, wherein the signal received by the receiver undergoes symbol spreading over entire bandwidth of the channel, thereby having error statistics that are mathematically represented as an additive white gaussian noise.

3. The method of clause 1, wherein the NB-LDPC code comprises a structured regular systematic repeat accumulate code over a non-binary field.

4. The method of clause 3, wherein a parity matrix H for the NB-LDPC code comprises a non-binary matrix generated from a binary H matrix. Various examples of the H matrix are described in Section 2.

5. The method of clause 4, wherein the binary H matrix is based on a computer search algorithm.

6. The method of clause 5, wherein the computer search algorithm terminates when no N-cycles are present in a Tanner graph representation of the binary H matrix, and wherein N=4 or 6. Additional description is provided with reference to FIG. 8 and FIG. 17.

7. The method of clause 4, wherein the parity check matrix H is represented as H=[H_1,H_2], where is the parity part and is the systematic part, wherein both and are composed of blocks of circulant permutation matrices and zero matrices of block size Q, where Q is an integer.

8. The method of clause 1, wherein the demodulating the received signal to produce data includes operating a slicer and a log likelihood ratio (LLR) computer stage on intermediate data generated from the received signal.

9. The method of clause 1, wherein the decoding data includes performing decoding using one of a flooding type algorithm or a layered algorithm.

10. The method of clause 8, wherein the LLR computer is either a symbol-wise LLR computer or a bit-wise LLR computer.

11. The method of clause 10, wherein the symbol-wise LLR computer calculates

LLR for a LDPC symbol using:

$\mathrm{LLR}\left(s^{\left(c\right)}=x_1{x}_2\dots x_c\right)=\ln \left[\frac{\sum _{i=1}^{\alpha }P\left(s^{\left(c\right)}=x_1{x}_2\dots x_c\right)/y\left(k\right)}{\sum _{i=1}^{\beta }P\left(s^{\left(c\right)}=0_1{0}_2\dots 0_c\right)/y\left(k\right)}\right]$

where P is a probability function, i is an integer, c is an integer number of consecutive bits of a constellation in the OTFS or OFDM modulated signal, and x and y represent transmitted and received constellation points, respectively.

12. The forward error correction method of clause 1, wherein the receiving the signal includes receiving a radio frequency signal over the air.

13. The forward error correction method of clause 1, wherein the receiving the signal includes receiving a radio frequency signal over a wire.

14. The forward error correction method of clause 1, wherein the receiving the signal includes receiving an optical signal over a fiber optic cable.

15. A forward error correction method performed at a transmitter, comprising: encoding information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries, modulating, using orthogonal time frequency space (OTFS) or orthogonal frequency division multiplexing (OFDM), the encoded information bits to generate a signal; and transmitting the signal over a channel.

16. The method of Clause 15, wherein the signal received by the receiver undergoes symbol spreading over entire bandwidth of the channel, thereby having error statistics that are mathematically represented as an additive white gaussian noise.

17. The method of clause 15, wherein the NB-LDPC code comprises a structured regular systematic repeat accumulate code over a non-binary field.

18. The method of clause 17, wherein a parity matrix H for the NB-LDPC code comprises a non-binary matrix generated from a binary H matrix.

19. The method of clause 15, wherein the data is scrambled prior to encoding with the NB-LDPC code.

20. The method of clause 15, wherein the encoding with the NB-LDPC code comprises processing through a four-stage architecture comprising a top controller, an input interface, a core and a transmit interface for outputting the encoded data.

21. The method of clause 20, further comprising storing information symbols from the data in the core.

22. The method of clause 21, wherein the core comprises an I memory, a G memory, a submatrix processing unit, a readout register and a core controller, wherein the method further includes: holding the information symbols in the I memory during computations; holding a submatrix of calculations in the G memory; computing the parity submatrix and corresponding portion of a message vector by the submatrix processing unit; reading out results of calculations in the core using the readout register; and controlling operation of the core using the core controller.

23. The forward error correction method of clause 15, wherein the transmitting the signal includes transmitting a radio frequency signal over the air.

24. The forward error correction method of clause 15, wherein the transmitting the signal includes transmitting a radio frequency signal over a wire.

25. The forward error correction method of clause 15, wherein the transmitting the signal includes transmitting an optical signal over a fiber optic cable.

26. An apparatus comprising a memory storing instructions and a processor, wherein the instructions, when executed by the processor, cause the processor to perform a method of any of clauses 1 to 25.

27. A computer-readable medium having code stored thereon, the code comprising instructions, when executed, causing a processor to implement a method recited in any one or more of clauses 1 to 25.

Various additional implementation details are provided in the encoder implementation details sections 2.5 and 2.6 and decoder implementation details section 2.8. From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

It will be appreciated that the disclosed techniques can be used to improve reception performance of wireless apparatus and/or reduce complexity of implementation.

The disclosed and other embodiments, modules and the functional operations described in this document can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this document and their structural equivalents, or in combinations of one or more of them. For example, the various LDPC encoder and decoder configurations may be implemented partially in software, and partly in hardware circuits. Matrix operations and iterative calculations, for example, may be implemented in processor-executed code, while division and accumulation operations may be performed in hardware circuits.

The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more them. The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus.

A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

While this patent document contains many specifics, these should not be construed as limitations on the scope of an invention that is claimed or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or a variation of a sub-combination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.

Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations can be made based on what is disclosed.

Claims

1. An apparatus for forward error correction, comprising: a processor-implemented encoder configured to encode information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;a modulator configured to modulate, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; anda transmitter configured to transmit the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, andwherein the binary H matrix is based on a computer search algorithm configured to: add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.

2. The apparatus of claim 1, wherein the computer search algorithm is configured to terminate upon a determination that no N-cycles are present in a Tanner graph representation of the binary H matrix, and wherein N=4 or N=6.

3. The apparatus of claim 1, wherein the parity check matrix H is represented a H=[H1, H2], where H1 is the parity part and H2 is the systematic part, wherein both H1 and H2 are composed of blocks of circulant permutation matrices and zero matrices of block size Q, where Q is an integer.

4. The apparatus of claim 1, wherein the NB-LDPC code comprises a structured regular systematic repeat accumulate code over a non-binary field.

5. The apparatus of claim 1, wherein the information bits are scrambled prior to encoding with the NB-LDPC code.

6. The apparatus of claim 1, wherein the encoder comprises a four-stage architecture, and wherein encoding the information bits comprises processing through the four-stage architecture comprising a top controller, an input interface, a core and a transmit interface for outputting encoded data.

7. The apparatus of claim 6, wherein the information bits are stored in the core.

8. The apparatus of claim 7, wherein the core comprises an I memory, a G memory, a submatrix processing unit, a readout register and a core controller, and wherein the encoding the information bits further includes: holding the information bits in the I memory during computations;holding a submatrix of calculations in the G memory;computing, using the submatrix processing unit, a parity submatrix and a corresponding portion of a message vector;reading out results of calculations in the core using the readout register; andcontrolling operation of the core using the core controller.

9. The apparatus of claim 1, wherein transmitting the signal over the channel comprises transmitting a radio frequency signal over the air, transmitting the radio frequency signal over a wire, or transmitting an optical signal over a fiber optic cable.

10. A method for forward error correcting, comprising: encoding information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;modulating, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; andtransmitting the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, andwherein the binary H matrix is based on a computer search algorithm configured to: add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.

11. The method of claim 10, wherein the computer search algorithm is configured to terminate upon a determination that no N-cycles are present in a Tanner graph representation of the binary H matrix, and wherein N=4 or N=6.

12. The method of claim 10, wherein the parity check matrix H is represented a H=[H1, H2], where H1 is the parity part and H2 is the systematic part, wherein both H1 and H2 are composed of blocks of circulant permutation matrices and zero matrices of block size Q, where Q is an integer.

13. The method of claim 10, wherein the information bits are scrambled prior to encoding with the NB-LDPC code.

14. The method of claim 10, wherein the encoding the information bits comprises: processing the information bits through a four-stage architecture comprising a top controller, an input interface, a core and a transmit interface for outputting encoded data.

15. The method of claim 14, wherein the information bits are stored in the core.

16. The method of claim 15, wherein the core comprises an I memory, a G memory, a submatrix processing unit, a readout register and a core controller, and wherein the processing the information bits comprises: holding the information bits in the I memory during computations;holding a submatrix of calculations in the G memory;computing, using the submatrix processing unit, a parity submatrix and a corresponding portion of a message vector;reading out results of calculations in the core using the readout register; andcontrolling operation of the core using the core controller.

17. A non-transitory computer-readable storage medium having code stored thereon, the code comprising instructions, when executed, causing a processor to implement a method for forward error correction, comprising: instructions for encoding information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;instructions for modulating, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; andinstructions for transmitting the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, andwherein the binary H matrix is based on a computer search algorithm configured to: add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.

18. The computer-readable storage medium of claim 17, wherein the instructions for encoding the information bits comprise: instructions for processing the information bits through a four-stage architecture comprising a top controller, an input interface, a core and a transmit interface for outputting encoded data.

19. The computer-readable storage medium of claim 18, wherein the information bits are stored in the core.

20. The computer-readable storage medium of claim 19, wherein the core comprises an I memory, a G memory, a submatrix processing unit, a readout register and a core controller, and wherein the instructions for processing the information bits comprises: instructions for holding the information bits in the I memory during computations;instructions for holding a submatrix of calculations in the G memory;instructions for computing, using the submatrix processing unit, a parity submatrix and a corresponding portion of a message vector;instructions for reading out results of calculations in the core using the readout register; andinstructions for controlling operation of the core using the core controller.