Patent Application
20050100083
The invention relates to data transmission, and, more specifically, high speed full duplex transmission.
In recent years, bandwidth requirements for digital communications switching equipment have risen to 40 Gb/s per line card. A fundamental limitation for equipment manufacturers is the bottleneck that exists when moving high-speed data back and forth within the chassis of a piece of communications equipment. Recent IEEE standards such as IEEE 802.3ae have defined a four-lane architecture to achieve a 10 Gb/s data communication system. This architecture, also known as XAUI, uses a four-lane parallel structure. The four lane arrangement is used, because a single serial structure would require too high of a symbol rate and the limited bandwidth of printed circuit board (PCB) traces would not be able to support it. Each lane uses differential signaling across two traces (or wires).
The four lane XAUI standard comprises half duplex communication. Thus, in order to achieve full duplex communications, eight lanes are required for the XAUI standard. As data rate per line card exceed 40 Gb/s, material limitations will prove difficult to overcome. It is advantageous to maintain the lowest possible signaling rate, at a minimal power, in order to enable future increases in data rates.
The XAUI standard is defined by IEEE 802.3ae and comprises a four-lane structure. Each lane uses one pair of wires (or PCB traces) and a 2.5 Gb/s data transmission rate. The actual bit rate on each wire pair is 3.125 Gb/s including 8b10b encoding overhead, which is added to maintain the DC balance of the differential pair. A total data rate of 12.5 Gb/s is used for one direction. A similar four-lane structure is needed for the opposite half duplex direction. Therefore, a total of 16 pins, or traces, is required for full duplex communication for the XAUI interface. The binary transmitted signal on each lane, or pair of traces, represents the high and low levels corresponding to the data 1 and 0 respectively. The two state differential transmission corresponds with a two level pulse amplitude modulation (PAM) scheme. The symbol speed of the binary signal is 3.125 Gb/s. Thus, 3.125 Gb/s of information with 8b10b overhead can be transmitted if there are no errors.
There have been attempts to improve the transmission efficiency by using PAM levels greater that two. One example of a system proposes increasing in the increasing the number of PAM levels for the line code from 2 to 4. This increases the number of bits transmitted by each lane and, thus, increases the data rate. For example, by using a 4 level PAM and a 3.125 Gb/s symbol rate, only four lanes are needed to achieve full duplex at 10 Gb/s. This saves half of the lanes one compared to the XAUI interface.
Other attempts to improve transmission efficiency include increasing number of PAM levels from 2 to 5. The fifth level is often used for error coding. This increases the number of bits transmitted by each lane, thereby increasing the data rate. For example, by using a 5 level PAM with a 2.5 Gb/s symbol rate, only four lanes are you needed to achieve full duplex at 10 Gb/s.
Still other attempts include increasing the symbol rate rather than the PAM level. For example, by using a 2 level PAM with a 6.25 Gb/s symbol rate, only four lanes are needed to achieve full duplex at 10 Gb/s. One can speed up the symbol rate even more, to 12.5 Gb/s, for example, to achieve full duplex on only two lanes.
All of these prior art attempts are understood to increase throughput of the data by either increasing the PAM level, increasing the symbol rate, or a combination of both. In fact, the ultimate goal these methods is to reduce the number of pins, or number of PCB traces, to achieve a certain data rate. At the same time, these prior art methods do not address the desirability of a low symbol rate in order to achieve reliable communications.
One skilled in the art will realize that it is almost always advantageous to reduce the number of traces in digital system. There is a need for a full duplex 10 Gb/s or greater communication system with a minimal number of traces, low power consumption, and minimal symbol rates.
This document describes a method and apparatus for high speed duplex data communication.
The number of lanes used for full duplex communication in high speed systems can be cut in half by using full duplex communications on the lanes provided.
Full duplex communication on a lane can be achieved with the use of an echo canceller. Echo cancellers generally remove traces of a transmitted signal from the received signal before a signal decoder receives the far end signal. That way, the signal decoder does not become confused by data transmitted by its own transmitter.
By using this scheme, full duplex communication can be achieved on one lane. For a 10 Gb/s data rate with 8b10b encoding, a symbol rate of 3.125 Gb/s with two level PAM is used over four lanes to achieve full duplex communication.
There may be significant signal integrity gains to be had by using four level PAM in combination with echo cancellation instead of two level PAM. Therefore, one alternate method is to use full duplex 4 level PAM at a 6.25 Gb/s symbol rate on one lane. Another alternate method is to use full duplex 4 level PAM at a 3.125 Gb/s symbol rate on two lanes. Still another alternate method is to use full duplex 4 level PAM at a 1.5625 Gb/s symbol rate on four lanes. Each of these 4 level PAM methods achieves a full duplex 10 Gb/s data rate. One will recognize the pattern and realize that many other combinations are possible with four level PAM when used in combination with echo cancellation.
The automatic gain control equalizer 426 adjusts the level of the incoming signal to ensure the receiver sees a relatively constant range of signals. The decision block 430 determines the PAM level symbol being received. The decision feedback equalizer 432 adjusts the incoming signals based on the errors seen after the data decision is made. The phase detector 424 compares the clock generating by the receive PLL 414 and the incoming data edges. It feeds this delta to the receive PLL 414 for clock adjustment. The de-scrambler 434 returns the scrambled data being received back to its original order. The reference PLL 412 generates a master clock that is used to clock the entire device. The receive PLL 414 adjusts the clock generated by the reference PLL 412 to align it with the data being received. This allows the receiver to sample data at the optimized location.
It will be apparent to one skilled in the art that the described embodiments may be altered in many ways without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be determined by the following claims and their equivalents.
This application claims priority under 35 U.S.C. § 119(e) to provisional application No. 60/512,571 filed on Oct. 16, 2003 titled “Full Duplex 10 Gb/s Transmission Method.”
| Number | Date | Country | |
|---|---|---|---|
| 60512571 | Oct 2003 | US |
