Integrated circuits are generally formed on semiconductor wafers formed from materials such as silicon. The semiconductor wafers are processed to form various electronic devices thereon. The wafers are diced into semiconductor chips, which may then be attached to a package substrate. Such a chip or die may have solder bump contacts on the integrated circuit. The solder bump contacts may extend downward onto contact pads of a substrate. Electronic signals may be provided through the solder bump contacts to and from the integrated circuit. Operation of the integrated circuit generates undesirable heat in the device. Heat is conducted to a surface of the die, and should be conducted away to maintain the temperature of the integrated circuit below a predetermined level for purposes of maintaining functional integrity of the integrated circuit.
One way to conduct heat from an integrated circuit die is through the use of a thermoelectric cooling (TEC) device. The TEC is a structure that is positioned on a device over high heat flux areas to reduce the temperature. In general, a TEC structure may be a solid-state heat pump that acts to transmit heat away from the body to be cooled, and is based on the Peltier Effect, by which a current applied across two dissimilar materials causes a temperature differential to occur. A typical TEC structure may include a series of P-type and N-type doped semiconductor elements (TEC legs or couples) connected in series. The TEC structure may be electrically isolated from the device it cools by an electrically insulative layer.
Embodiments are described by way of example, with reference to the accompanying drawings, which are not drawn to scale, wherein:
FIGS. 2(a)-(d) illustrate a process for forming an assembly in which regions between the legs of a TEC structure are filled with a polymer material, in accordance with certain embodiments; and
FIGS. 3(a)-(d) illustrate a process for forming an assembly in which regions between the legs of a TEC structure are filled with a polymer material, in accordance with certain embodiments;
There are a variety of ways to place TEC elements onto an electronic assembly including a die. One method is to form the structure through chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), or other deposition processes. The structure may include a plurality of rows of TEC elements. Another approach is to form the TEC structure on a separate surface and then transfer the TEC structure to the die. Yet another approach is to form the specific TEC structure elements separately and then transfer each element to the die. The various approaches for forming TEC's generally form a TEC structure in which open spaces exist between the elements (such as, for example, semiconductor elements or legs) of the structure.
Having open spaces (filled with air, for example) within the TEC structure may in certain applications be sufficient. However, certain applications place a thermally conductive material on the exposed (hot) surface of the TEC structure. Such a thermally conductive material may include, for example, a thermal grease or solder. If the thermally conductive material flows into the open spaces around the elements, the resultant high thermal conductivity path for heat conduction from the hot side to the cold side may significantly reduce the performance of the TEC structure.
Certain embodiments relate to electronic assembly structures including a TEC structure and methods for forming such assemblies, including filling the open spaces around the elements with a material in order to enable a TEC structure to efficiently transfer heat away from a die.
The assembly illustrated in
A body 24 such as a heat spreader may be positioned on the TEC structure on electrically insulative region 20. Layers 34 and 36 are positioned between the body 24 and the electrically insulative region 20. Layer 34 may be a material such as a solder for coupling the layers together. Layer 36 generally acts to ensure adequate adhesion between the layers, and may include one or more metal layers. In one embodiment, the layer 36 includes layers of Ti, Ti—Ni, and Au. Heat is transferred through the electrically insulative region 20 to the heat spreader 24. A low thermal conductivity material 22 is positioned within the open regions of the structure adjacent to the TEC legs 14 and 16, between the electrically insulative region 10 and the electrically conductive region 18, and between the electrically insulative region 20 and the electrically conductive region 12.
In accordance with certain embodiments, a number of processes may be used to fill the open regions in the TEC structure with a low thermal conductivity material. Such processes may include one or more of spin-on, reflow, and capillary force methods. Some processes may require a post application operation to clean exposed surfaces of any excess material. Capillary force methods generally act to draw the material (for example, a polymer), into the open regions of the TEC structure. There are factors relating to reliability and processing that may influence the exact material chosen as the low thermal conductivity material. Reliability factors may include, for example, low thermal conductivity, good adhesion to interfaces, and good moisture resistivity. Process related factors include, for example, proper viscosity to fill gaps, stability during processing operations, and ability to flow according to capillary action. Certain embodiments use a polymer material (for example, a filled or unfilled polymer) that can be cured to cross-link the polymer and form a hard encapsulating material.
FIGS. 2(a)-2(d) illustrate a process for forming an assembly in which the open regions of a TEC structure are filled with a polymer material.
The polymer 22 may be formed from a variety of materials. As described above, in certain embodiments, the polymer 22 may be solid at room temperature. Upon heating to a relatively low temperature, for example, about 50-60° C. in certain embodiments, the polymer may melt and flow into the openings in the TEC structure.
In certain embodiments, the polymer may be an epoxy type with anhydride, phenol or amine resin hardener. In other embodiments, the polymer may be a thermoplastic polymer with or without a filler such as silica. The thermal conductivity of epoxy and other resins are typically approximately 0.2-0.3 W/m-K, and the thermal conductivity of silica is normally about 1.5 W/m-K. The overall thermal conductivity of the polymer film with or without filler are low and can be tuned for the specific application. The physical properties of the polymer film such as the coefficient of thermal expansion (CTE), glass transition temperature (Tg), thermal stability, and adhesion can also be fine tuned to meet the specific application requirement. Certain applications may, for example, include modules having different spacings therebetween or different strength requirements. In certain embodiments, it is desired to have a polymer having a coefficient of thermal expansion that is approximately 30-60 ppm and a glass transition temperature of at least 100° C., and a thermal stability that shows no degradation below approximately 300° C.
FIGS. 3(a)- 3(d) illustrate a method for forming an assembly in accordance with certain embodiments. As seen in
As seen in
Block 100 is providing a heat spreader. Block 102 is forming a first electrically insulative layer on the heat spreader using a method such as, for example, sputtering. Block 104 is forming a first electrically conductive layer on the electrically insulative layer using a method such as, for example, sputtering. Block 106 is performing a masking and etching process on the electrically conductive layer to form separate first electrically conductive regions. Block 108 is forming the TEC legs on the electrically conductive regions. Layers such as barrier and solder layers as described above, may be present. Block 110 is forming second electrically conductive regions on the TEC legs. Block 112 is filling the open spaces in the TEC structure (such as between the TEC legs) with a low thermal conductivity material using a method such as those discussed above. Block 114 is forming a second electrically insulative layer on the TEC structure, so that the first and second electrically conductive regions, the TEC legs, and the low thermal conductivity material are positioned between the first and second electrically insulative layers. The second electrically insulative layer may be formed using a method such as, for example, sputtering. Block 116 is forming an adhesion layer (such as the layer 36 discussed earlier, which may include multiple sub-layers) on the second insulative layer. Block 118 is soldering the die to the adhesion layer in order couple the die to the rest of the assembly.
The computer 201 further may further include memory 209 and one or more controllers 211a, 211b . . . 211n, which are also disposed on the motherboard 207. The motherboard 207 may be a single layer or multi-layered board which has a plurality of conductive lines that provide communication between the circuits in the package 205 and other components mounted to the board 207. Alternatively, one or more of the CPU 203, memory 209 and controllers 21la, 211b . . . 211n may be disposed on other cards such as daughter cards or expansion cards. The CPU 203, memory 209 and controllers 211a, 211b . . . 211n may each be seated in individual sockets or may be connected directly to a printed circuit board. A display 215 may also be included.
Any suitable operating system and various applications execute on the CPU 203 and reside in the memory 209. The content residing in memory 209 may be cached in accordance with known caching techniques. Programs and data in memory 209 may be swapped into storage 213 as part of memory management operations. The computer 201 may comprise any suitable computing device, such as a mainframe, server, personal computer, workstation, laptop, handheld computer, telephony device, network appliance, virtualization device, storage controller, network controller, etc.
The controllers 211a, 211b . . . 211n may include a system controller, peripheral controller, memory controller, hub controller, I/O bus controller, video controller, network controller, storage controller, etc. For example, a storage controller can control the reading of data from and the writing of data to the storage 213 in accordance with a storage protocol layer. The storage protocol of the layer may be any of a number of known storage protocols. Data being written to or read from the storage 213 may be cached in accordance with known caching techniques. A network controller can include one or more protocol layers to send and receive network packets to and from remote devices over a network 217. The network 217 may comprise a Local Area Network (LAN), the Internet, a Wide Area Network (WAN), Storage Area Network (SAN), etc. Embodiments may be configured to transmit data over a wireless network or connection. In certain embodiments, the network controller and various protocol layers may employ the Ethernet protocol over unshielded twisted pair cable, token ring protocol, Fibre Channel protocol, etc., or any other suitable network communication protocol.
While certain exemplary embodiments have been described above and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive, and that embodiments are not restricted to the specific constructions and arrangements shown and described since modifications may occur to those having ordinary skill in the art.