Patent Grant
9859394
The present disclosure relates, generally, to field effect transistors, such as integrated field-effect devices, systems including the devices, and methods of using the same for the analysis of biological and/or chemical materials, such as for molecular, e.g., nucleic acid, analysis and/or sequencing. More specifically, the present disclosure relates to field effect transistors having a reaction layer that includes one or two-dimensional materials associated therewith.
The sequencing of Nucleic Acids, such as deoxyribonucleic acid (DNA) or Ribonucleic acid (RNA), is a fundamental part of biological discovery. Such sequencing and/or the detection of the same is useful for a variety of purposes and is often used in scientific research, as well as medical advancement. For instance, the genomics and bioinformatics fields are concerned with the application of information technology and computer science to the field of molecular biology. In particular, bioinformatics techniques can be applied to process and analyze various genomic data, such as from an individual so as to determine quantitative and qualitative information about that data that can then be used by various practitioners in the development of diagnostic, prophylactic, and/or therapeutic methods for detecting, preventing, or at least ameliorating diseased states, and thus, improving the safety, quality, and effectiveness of health care. The need for such diagnostic, therapeutic, and prophylactic advancements have led to a high demand for low-cost sequencing, which in turn has driven the development of high-throughput sequencing, termed as Next generation sequencing (NGS).
Generally, the approach to DNA and/or RNA analysis, such as for genetic diagnostics and/or sequencing, involves nucleic acid hybridization and detection. For example, various typical hybridization and detection approaches include the following steps. Particularly, for genetic analysis, a DNA or RNA sample of a subject to be analyzed may be isolated and immobilized on a substrate. In such instances, the immobilized genetic material acts as a template for new nucleic acid synthesis. A probe of a known sequence identity, e.g., a disease marker, may be labeled and washed across the substrate. If the disease marker is present, a binding event will occur, e.g., hybridization, and because the probe has been labeled the hybridization event may either be or not be detected thereby indicating the presence or absence of the disease marker in the subject's sample.
For DNA sequencing, first, an unknown nucleic acid sequence to be identified, e.g., a single-stranded sequence of DNA of a subject, composed of a combination of unknown nucleotides, e.g., As, Cs, Gs, and Ts, is isolated, amplified, and immobilized on the substrate. Next, a known nucleotide labeled with an identifiable tag is contacted with the unknown nucleic acid sequence in the presence of a polymerase. When hybridization occurs, the labeled nucleotide binds to its complementary base in the unknown sequence immobilized on the surface of the substrate. The binding event can then be detected, e.g., optically or electrically. These steps are then repeated until the entire DNA sample has been completely sequenced, e.g., sequencing by synthesis. Typically, these steps are performed by a Next Gen Sequencer wherein thousands to millions of sequences may concurrently be produced in the next-generation sequencing process.
For example, a central challenge in DNA sequencing is assembling full-length genomic sequence data, e.g., of chromosomal sequences, from a sample of genetic material obtained from a subject. Particularly, such assembling includes one or more genomic analysis protocols, such as employing a mapping and/or an aligning algorithm, and involves mapping and aligning a fragment of identified sample sequence to a reference genome, yielding sequence data in a format that can be compared to a reference genomic sequence, such as to determine the variants in the sampled full-length genomic sequences. In particular, the methods employed in sequencing protocols do not produce full-length chromosomal sequences of the sample DNA.
Rather, in a typical sequencing protocol, sequence fragments, typically from 100-1,000 nucleotides in length, are produced without any indication as to where in the genome they map and align. Therefore, in order to generate full-length chromosomal genomic constructs, or determine their variance with respect to a reference genomic sequence, these fragments of DNA sequences need to be mapped, aligned, merged, and/or compared to the reference genomic sequence. Through such processes the variants of the sample genomic sequences from the reference genomic sequences may be determined.
However, as the human genome is comprised of approximately 3.1 billion base pairs, and as each sequence fragment is typically only from about 100 to 500 to 1,000 nucleotides in length, the time and effort that goes into building such full length genomic sequences and determining the variants therein is quite extensive, often requiring the use of several different computer resources applying several different algorithms over prolonged periods of time. In a particular instance, thousands to millions of fragments or even billions of DNA sequences are generated, mapped, aligned, and merged in order to construct a genomic sequence that approximates a chromosome in length. A step in this process may include comparing the sequenced DNA fragments to a reference sequence so as to determine where in the genome the fragments align.
In such instances, the raw genetic material must be processed so as to derive usable genetic sequence data therefrom. This processing may be done manually or via an automated sequencer. Typically, such processing involves obtaining a biological sample from a subject, such as through venipuncture, hair, etc. and treating the sample to isolate the DNA therefrom. Once isolated the DNA may be denatured, strand separated, and/or portions of the DNA may then be multiplied, e.g., via polymerase chain reaction (PCR), so as to build a library of replicated strands that are now ready to be sequenced, e.g., read, such as by an automated sequencer, which sequencer is configured to “read” the replicate strands, e.g., by synthesis, and thereby determine the nucleotide sequences that makes up the DNA. Further, in various instances, such as in building the library of replicated strands, it may be useful to provide for over-coverage when preprocessing a given portion of the DNA. To perform this over-coverage, e.g., using PCR, may require increased sample preparation resources and time, and therefore be more expensive, but it often gives an enhanced probability of the end result being more accurate.
More particularly, once the library of replicated strands has been generated they may be injected into an automated sequencer that may then “read” the strands, such as by synthesis, so as to determine the nucleotide sequences thereof. For instance, the replicated single stranded DNA may be attached to a glass bead and inserted into a test vessel, e.g., an array. All the necessary components for replicating its complementary strand, including labeled nucleotides, are also added to the vessel but in a sequential fashion. For example, all labeled “A”, “C”, “G”, and “T's” are added, either one at a time or all together to see which of the nucleotides is going to bind at position one. After each addition a light, e.g., a laser, is shone on the array. If the composition fluoresces then an image is produced indicating which nucleotide bound to the subject location. More particularly, where the nucleotides are added one at a time, if a binding event occurs, then its indicative fluorescence will be observed. If a binding event does not occur, the test vessel may be washed and the procedure repeated until the appropriate one of the four nucleotides binds to its complement at the subject location, and its indicative fluorescence is observed. Where all four nucleotides are added at the same time, each may be labeled with a different fluorescent indicator, and the nucleotide that binds to its complement at the subject position may be determined, such as by the color of its fluorescence. This greatly accelerates the synthesis process.
Once a binding event has occurred, the complex is then washed and the synthesis steps are repeated for position two. For example, a marked nucleotide “A” may be added to the mix to determine if the complement at the position is a “T”, and if so, all the sequences having that complement will bind to the labeled “T” and will therefore fluoresce, and the samples will all be washed. Where the binding happened the bound nucleotide is not washed away, and then this will be repeated for all positions until all the over-sampled nucleic acid segments, e.g., reads, have been sequenced and the data collected. Alternatively, where all four nucleotides are added at the same time, each labeled with a different fluorescent indicator, only one nucleotide will bind to its complement at the subject position, and the others will be washed away, such that after the vessel has been washed, a laser may be shone on the vessel and which nucleotide bound to its complement may be determined, such as by the color of its fluorescence. This continues until the entire strand has been replicated in the vessel.
A typical length of a sequence replicated in this manner is from about 100 to about 500 base pairs, such as between 150 to about 400 base pairs, including from about 200 to about 350 base pairs, such as about 250 base pairs to about 300 base pairs dependent on the sequencing protocol being employed. Further, the length of these segments may be predetermined, e.g., engineered, to accord with any particular sequencing machinery and/or protocol by which it is run. The end result is a readout, or read, that is comprised of a replicated DNA segment, e.g., from about 100 to about 1,000 nucleotides in length, that has been labeled in such a manner that every nucleotide in the sequence, e.g., read, is known because of its label. Hence, since the human genome is comprised of about 3.1 billion base pairs, and various known sequencing protocols usually result in labeled replicated sequences, e.g., reads, from about 100 or 101 bases to about 250 or about 300 or about 400 bases, the total amount of segments that need to be sequenced, and consequently the total number of reads generated, can be anywhere from about 10,000,000 to about 40,000,000, such as about 15,000,000 to about 30,000,000, dependent on how long the label replicated sequences are. Therefore, the sequencer may typically generate about 30,000,000 reads, such as where the read length is 100 nucleotides in length, so as to cover the genome once.
However, in part, due to the need for the use of optically detectable, e.g., fluorescent, labels in the sequencing reactions being performed, the required instrumentation for performing such high throughput sequencing is bulky, costly, and not portable. For this reason, a number of new approaches for direct, label-free detection of DNA hybridization reactions have been proposed. For instance, among the new approaches are detection methods that are based on the use of various electronic analytic devices. Such direct electronic detection methods have several advantages over the typical NGS platform. For example, the detector may be incorporated in the substrate itself, such as employing a biosystem-on-a-chip device, such as a complementary metal oxide semiconductor device, “CMOS”. More particularly, in using a CMOS device in genetic detection, the output signal representative of a hybridization event can be directly acquired and processed on a microchip. In such an instance, automatic recognition is theoretically achievable in real time and at a lower cost than is currently achievable using NGS processing. Moreover, standard CMOS devices may be employed for such electronic detection making the process simple, inexpensive, and portable.
However, in order for next-generation sequencing to become widely used as a diagnostic in the healthcare industry, sequencing instrumentation will need to be mass produced with a high degree of quality and economy. One way to achieve this is to recast DNA sequencing in a format that fully leverages the manufacturing base created for computer chips, such as complementary metaloxide semiconductor (CMOS) chip fabrication, which is the current pinnacle of large scale, high quality, low-cost manufacturing of high technology. To achieve this, ideally the entire sensory apparatus of the sequencer could be embodied in a standard semiconductor chip, manufactured in the same fab facilities used for logic and memory chips. Recently, such a sequencing chip, and the associated sequencing platform, has been developed and commercialized by Ion Torrent, a division of Thermo-Fisher, Inc. The promise of this idea has not been realized commercially due to the fundamental limits of applying a metal oxide semiconductor field effect transistor, or MOSFET, as a biosensor. When a MOSFET is used in solution as a biosensor, it is referred to as an ISFET. A particular limitation, however, includes a lack of sensor sensitivity and signal to noise characteristics as the semiconductor node scales down to lower geometries of the transistor (gate length).
More particularly, a field effect transistor, FET, typically includes a source electrode and a drain electrode together forming a gate, and further including a channel region connecting the source and drain electrodes. The FET may also include an insulating barrier separating the gate from the channel. The operation of a conventional FET relies on the control of the channel conductivity, and thus the drain current, by a voltage, VGS, applied between the gate and source. For high-speed applications, and for the purposes of increasing sensor sensitivity, FETs should respond quickly to variations in VGS. However, this requires short gates and fast carriers in the channel.
Unfortunately, FETs with short gates frequently suffer from degraded electrostatics and other problems (collectively known as short channel effects), such as threshold-voltage roll-off, drain-induced barrier lowering, and impaired drain-current saturation, results in a decrease in sensor sensitivity. However, scaling theory predicts that a FET with a thin barrier and a thin gate-controlled region (measured in the vertical direction) will be robust against short-channel effects down to very short gate lengths (measured in the horizontal direction). Nevertheless, these effects make the use of such technologies difficult to employ in sequencing reactions.
Accordingly, the possibility of having channels that are very thin in the vertical dimension would allow for high-speed transmission of carriers as well as for increased sensor sensitivity and accuracy. What is needed, therefore, is a FET device that is configured in such a manner as to include a shorter gate than is currently achievable in present FET applications, which will allow such technologies to be fully deployed in sequencing reactions. Hence, a solution that includes such a FET device designed for use in biological applications, such as for nucleic acid sequencing and/or genetic diagnostics would especially be beneficial.
Provided herein are devices, systems, and methods of employing the same for the performance of genomics and/or bioinformatics analysis. The devices, systems, and methods of the disclosure are directed in part to field effect transistor (FET) sensors, integrated circuits, and arrays employing the same for analyte measurements. The present FET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved FET sensor and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small sensor sizes and dense gFET sensor based arrays. Particularly, improved fabrication techniques, as well as improved sensor devices, and their use, employing one dimensional (1D) or two dimensional (2D) reaction layers and/or having a three-dimensional (3D) structured layer incorporated therein, provide for rapid data acquisition from small sensors to large, including dense arrays of sensors.
Such arrays may be fabricated, as described herein, and employed to detect the presence of an analyte, changes in analyte concentration, and/or the identity of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. More particularly, presented herein are FET based sensor arrays that have been configured to facilitate DNA hybridization and sequencing techniques, as well as the resultant detection of the same, which take place proximate a reaction zone that has been adapted to include a 1D or 2D or 3D surface element. Specifically, in various embodiments, complementary metaloxide semiconductor (CMOS) field effect transistor (FET) devices are provided, where the devices include a plurality of reaction zones that have been adapted to have a 1D or 2D surface characteristic associated therewith so as to decrease sensor length at the same time as increasing sensor sensitivity. Further, in various instances, a 3D structural layer may be included, such as to extend the vertical dimension of the reaction zone. In such instances, the devices may include a number of reaction zones that have been configured to receive a solution containing one or more reactants that when conditions are such to favor a reaction result in a detectable product.
Accordingly, presented herein are improved bio-chemical sensor devices that are configured for detecting changes in a gate region and/or solution that result from the occurrence of a binding event between two reactants proximate a reaction zone of the device, such as within the gate region. In particular instances, the detectable changes may be based on monitoring fluctuations in hydrogen ion concentration (pH), variations in analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis, such as within a gated reaction chamber of a 1D or 2D or 3D based biosensor chip. More specifically, the present disclosure is at least in part directed to a chemically-sensitive field-effect transistor for analysis of biological or chemical materials that solves many of the current problems associated with nucleic acid sequencing and genetic diagnostics. Methods of fabricating such devices as well as their use in the performance of biochemical reactions are also provided.
For instance, in one aspect of the present disclosure, a chemically-sensitive transistor, such as a field effect transistor (FET) that is fabricated on a primary structure, such as a wafer, e.g., a silicon wafer, is provided. In various instances, the primary structure may include one or more additional structures, for instance, in a stacked configuration, such as including at least an insulator material layer. For example, the primary structure may include a secondary structure, such as composed of an insulator material, which may be included on top of, or otherwise be associated with, the primary structure, and may be an inorganic material, such as a silicon oxide, e.g., a silicon dioxide, or a silicon nitride, or an organic material, such as a polyimide, BCB, or other like material.
The secondary structure and/or insulator layer may include a further structure containing one or more of a conductive source and/or a conductive drain, such as separated one from another by a space, and embedded in the primary and/or secondary structure materials and/or may be planar with a top surface of the insulator. In various instances, the structures may further include a processor, such as for processing generated data, such as sensor-derived data. Accordingly, the structures may be configured as, or otherwise include, an integrated circuit, and/or may be an ASIC, a structured ASIC, or an FPGA. In particular instances, the structures may be configured as a complementary metal-oxide semiconductor (CMOS), which in turn may be configured as a chemically-sensitive FET containing one or more of a conductive source, a conductive drain, a gate, and/or a processor. For instance, the FET may include a CMOS configuration having an integrated circuit that is fabricated on a silicon wafer, which may further be adapted to include an insulator layer. In such an instance, the insulator layer may include the conductive source and drain such as where the source and drain are composed of metal, such as a damascene copper source and a damascene copper drain.
In various instances, one or more of the structures may include a surface, e.g., a top surface, which surface may include a channel, such as where the surface and/or channel may be configured to extend from the conductive source to the conductive drain. An exemplary length of the surface and/or channel from the source to the drain may range from about 0.001 microns to about 10 microns, such as from about 0.01 microns to about 5 microns, for instance, from about 0.05 micron to 3 microns, including about 0.1 or about 0.5 microns to about 1 or about 1.5 or about 2 microns in the horizontal and/or vertical directions. An exemplary width of the surface and/or channel from side to side may range from about 0.001 microns to about 10 microns, such as from about 0.01 microns to about 5 microns, for instance, from about 0.05 microns to 3 microns, including about 0.1 or 0.5 microns to about 1 or about 1.5 or about 2 microns.
Particularly, in particular instances, it may be useful to maximize conductance, such as by decreasing the channel length, so as to increase the sensitivity of the sensors, such as in a sensor array. For instance, to achieve enhanced transistor transconductance, the channel may be configured so as to include a short channel length, e.g., as short a length as possible, while at the same time including a larger channel width, e.g., as large as width as possible, within the sensor array, in a manner adapted for keeping the over all dimensions of the array as compact as possible. For example, the equation for transconductance of a field effect transistor, such as for a transistor presented herein, is: gm ∝μCov W/L Vsd; where gm is the transconductance, μ is the carrier mobility, Cov is the overall capacitance of the oxide or other layers over the transistor, W is the channel width, L is the channel length, and Vsd is the voltage from the source to the drain. Since gm directly relates to the sensitivity of the sensor it may be desirable to increase gm through moderating the terms shown in the equation.
In particular increasing the W/L ratio (maximizing W and minimizing L) will increase gm. In particular instances, a useful length of the channel from the source to the drain ranges is less than 1 micron, such as less than 500 nm, such as less than 50 nm, and may be as short as the fabrication process will allow without generating defects or results that render the device unusable. A particularly useful channel length may be 20 nm or less. Conversely, the width of the channel may be as wide as possible. In such instances, the width of the channel is not governed by the fabrication process as much as by the design requirements of the overall sensor chip. In various instances, many millions of sensors may be positioned on the sensor chip. With this large number of sensors the individual sensor size and pitch (e.g., which may directly affect the channel width) may be kept small, such as reasonably small, so as to prevent the chip from being so large as to be unable to be fabricated (e.g., exceeds the photolithography reticle size) or too expensive (due to the effect of defect density on a large chip size). A practical range of channel width in particular instances may be from 0.1 micron to 2 microns, e.g., for a simple rectangular channel design. In some cases, it may be desirable to increase the channel length to channel width ratio through the use of design techniques—for example, structured and/or an interdigitated 3D tooth and comb design can provide for short channel lengths and large channel widths within a relatively compact area.
In certain instances, the surface and/or channel may include a one-dimensional transistor material, a two-dimensional transistor material, a three-dimensional transistor material, and/or the like. In various instances, a one-dimensional (1D) transistor material may be included, which 1D material may be composed of a carbon nanotube or a semiconductor nanowire. In various instances, a two-dimensional (2D) transistor material may be included, which 2D material may be composed of a graphene layer, silicene, molybdenum disulfide, black phosphorous, and/or metal dichalcogenides. In particular instances, a three-dimensional (3D) structural material, such as proximate a reaction zone and/or channel layer may be provided. In various embodiments, the surface and/or channel may further include a dielectric layer. In particular instances, the surface and/or channel may include a graphene layer.
Additionally, in various instances, a reaction layer, e.g., an oxide layer, may be disposed on the surface and/or channel, such as layered or otherwise deposited on the 1D, 2D, e.g., graphene, or 3D layer, and/or an included dielectric layer. Such an oxide layer may be an aluminum oxide or a silicon oxide, such as silicon dioxide. In some embodiments, the oxide layer may have a thickness of about 20 nanometers, such as about 15 nanometers, such as 10 or 9 or 7 or 5 nanometers or less. In various instances, a passivation layer may be disposed on the surface and/or channel, such as layered or otherwise deposited on the 1 D, 2D, or 3D layer and/or on an associated reaction layer on the surface and/or channel. Such a passivation layer may have a thickness of about 0.5 microns or less, such as about 0.1 microns or about 50 nanometers or about 20 nanometers, such as about 15 nanometers, such as 10 or 9 or 7 or 5 nanometers or less.
In particular instances, the primary and/or secondary and/or tertiary structures may be fabricated or otherwise configured so as to include a chamber or well structure in and/or on the surface. For instance, a well structure may be positioned on a portion of a surface, e.g., an exterior surface, of the primary and/or secondary structures. In some instances, the well structure may be formed on top of, or may otherwise include, at least a portion of the 1 D, 2D, and/or 3D material, and/or may additionally include the reaction, e.g., oxide, and/or passivation layers. In various instances, the chamber and/or well structure may define an opening, such as an opening that allows access to an interior of the chamber, such as allowing direct contact with the 1D, e.g., carbon nanotube or nanowire, 2D, e.g., graphene, surface and/or channel. In such instances, the FET device may be configured as a solution gated sensor device.
Accordingly, a further aspect of the present disclosure is a bio-sensor. The bio-sensor includes a CMOS structure that may include a metal containing source, e.g., a damascene copper source, as well as a metal containing drain, e.g., a damascene copper drain, a 1D or 2D layered, e.g., a graphene layered, surface or channel extending from the source to the drain, and a well or chamber structure that may be positioned on a portion of an exterior surface of the 1D or 2D and/or 3D layered well. In particular instances, the well structure may be configured so as to define an opening that allows for direct, fluidic contact with the 1D, e.g., nanotube, nanowire, and/or 2D, e.g., graphene, well or chamber surface. In various instances, the well structure is further configured to include a 3D structural element, such as incorporated into one or more of the well bounding members. Further, an oxide and/or passivation layer may be disposed in or on the chamber surfaces. Hence, in certain instances, a chemically-sensitive transistor, such as a field effect transistor (FET) including one or more nano- or micro-wells may be provided.
In view of the above, in one aspect, the present disclosure is directed to a method of fabricating a field effect transistor, such as a transistor having one or more of a 1 D, 2D, or 3D material associated therewith, such as in proximity to a reaction zone configured within the FET. Any suitable method may be employed in such a fabrication process, however, in various instances, the method may involve the growing and/or transferring of the one-dimensional (1D0 or two-dimensional (2D) material for use as in the sensor. In such an instance, the method may include the growing of the 1D or 2D material layer, such as on a suitable growth platform, which may be a silicon platform or substrate. Particularly, the method may also include releasing the 1D and/or 2D material layer from the growth platform and/or transferring the material layer to the semiconductor structure or substrate.
Accordingly, in some embodiments, the chemically-sensitive field effect transistor may include a plurality of wells and may be configured as an array, e.g., a sensor array. Such an array or arrays may be employed such as to detect a presence and/or concentration change of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or DNA or RNA sequencing reactions. For instance, the devices herein described and/or systems including the same may be employed in a method for the analysis of biological or chemical materials, such as for whole genome analysis, genome typing analysis, micro-array analysis, panels analysis, exome analysis, micro-biome analysis, and/or clinical analysis, such as cancer analysis, NIPT analysis, and/or UCS analysis. In a particular embodiment, one or more surfaces within the wells of the field effect transistor may be configured as a reaction zone, which reaction zone may include an additional structure, such as a 1 D, 2D, e.g., graphene, or 3D layer, and hence, the FET may be a graphene FET (gFET) array.
Such FET sensors as herein described may be employed to facilitate DNA hybridization and/or sequencing techniques, such as based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentrations, and/or binding events associated with chemical processes (e.g., relating to DNA synthesis), such as within a gated reaction chamber or well of the gFET based sensor, such as proximate the reaction zone(s). For example, the chemically-sensitive field effect transistor may be configured as a CMOS biosensor and/or may be adapted to increase the measurement sensitivity and/or accuracy of the sensor and/or associated array(s), such as by including one or more surfaces or wells having a surface layered with a 1D and/or 2D and/or 3D material, a dielectric or reaction layer, a passivation layer, and the like. In particular instances, the increased sensitivity of the sensors may, in part, be due to the presence of the presence of the 1D or 2D material, and/or further enhanced by its relationship to one or more of the reaction and/or passivation layers, which in turn allows for smaller sensor configurations, therefore smaller channels and/or gates, and thus a greater density of sensors and/or arrays.
For instance, in a particular embodiment, a chemically-sensitive graphene containing field effect transistor (gFET), such as a gFET having a CMOS structure is provided, where the gFET sensor, e.g., biosensor, may include a substrate and at least a first insulating layer that may itself be configured so as to incorporate one or more of a 1 D, 2D, and/or 3D structure therein. For example, a 1D structure may be layered within or coated on top of the insulation layer, such as via chemical vapor deposition, e.g., PVC/CNT deposition, spin coating, physical vapor deposition, and the like. Additionally, or alternatively, a 2D structure or material layer may be applied to the first insulating layer of the CMOS structure, such as by the growth, or release, and/or transfer of the 2D material thereon. Particularly, in various embodiments, the 2D material may be graphene, Molybdenum disulfide (MoS2), Phosphorene (black phosphorous), Silicene, Borophene, Tungsten disulfide (WS2), Boron Nitride, WSe2, Stanene (2D tin), Graphane, Germanane, Nickel HITP, and Mxenes (Ti2C, (Ti0.5, Nb0.5), V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3, Ta4C3).
More particularly, in certain embodiments, the 2D material may be grown and/or transferred onto the substrate and/or insulating surface of the CMOS structure, which structure may therefore be a read-out integrated circuit (ROIC). For instance, there are several growth mechanisms that may be implemented for the growth of such a 2D material on a growth substrate, such as including the growth on a metal plate, a metal foil, a thin film metal, or a metal, e.g., silicon, wafer, and the like. Likewise, the 2D material may be applied to the material by chemical vapor deposition (“CVD”) (atmospheric, low or very low pressure), PECVD, ALD, or grown in a hot wall or cold wall reactor. Once gown, the 2D material may be transferred to the CMOS/ROIC structured materials, such as by one or more of the following transfer mechanisms including direct transfer from the growth substrate to a ROIC wafer using Van der Waal's forces, fusion bonding, and/or using temporary bonding. Further, there are several release mechanisms that may be implemented for effectuating the release of the 2D material from the growth medium and/or substrate pursuant to the transfer of the 2D material to the ROIC, which release mechanisms may include aqueous electrolyte electrolysis, e.g., with the growth platform as the cathode, and separation due to hydrogen evolution. Another release mechanism may be by separating a temporary adhesive from the growth platform using a laser, a UV light, a temperature increase, or physical peeling or pulling, and the like.
Additionally, in various embodiments, the CMOS structure may additionally include a further insulating layer, such as positioned on top of the second insulating layer, which first and/or second insulating layer(s) may be positioned one on top of the other, such as with the 1D or 2D material deposited there between. In particular instances, the first and/or second insulating layers may include a well structure, such as a well or chamber having a 3D structural layer, such as within or otherwise associated with a surface of the well or chamber. Further, in various embodiments, the CMOS structure may include an oxide and/or passivation layer, such as a layer that is deposited, e.g., via CVD deposition, or may be otherwise disposed on the surface of the well or chamber so as to increase the measurement sensitivity and/or accuracy of the sensor and/or associated array(s). The oxide layer, when present, may be composed of an aluminum oxide, a silicon oxide, a silicon dioxide, and the like. Particularly, the oxide and/or passivation layers may have a suitable thickness such as of from about 100 nm to about 75 nm, such as from about 50 nm to about 30 nm, from about 40 nm to about 25 nm, such as from about 20 nm to about 10 nm or 9 nm or less, respectively.
Accordingly, the present FET integrated circuits, sensors, and/or arrays of the disclosure may be fabricated such as using any suitable complementary metal-oxide semiconductor (CMOS) processing techniques known in the art. In certain instances, such a CMOS processing technique may be configured to increase the measurement sensitivity and/or accuracy of the sensor and/or array, and at the same time facilitate significantly small gates having relatively smaller sensor sizes and more dense FET chamber sensor regions. Particularly, in various embodiments, the improved fabrication techniques herein described result in sensor devices containing reaction zones employing a 1D or 2D material layer, and/or may include a 3D structural layer. For instance, a 1D or 2D material layer may be grown, such as on a growth platform, and once grown may be released from the growth platform, and then be transferred to a semiconductor structure, such a CMOS substrate, so as to be employed as a sensor therein.
Additionally, during or after manufacture one or more surfaces or layers of the CMOS transistor structure may be treated so as to contain one or more additional reaction layers, such as an oxide and/or passivation layers, which structures and layers, alone or in combination provide for rapid data acquisition, such as from small sensors to large and dense arrays of sensors. In certain embodiments, one or more of such layers may be fabricated along with the manufacture of the array, such as via one or more chemical vapor deposition techniques. Further, in particular embodiments, an ion-selective permeable membrane may be included, such as where the membrane layer may include a polymer, such as a perfluorosulphonic material, a perfluorocarboxylic material, PEEK, PBI, Nafion, and/or PTFE. In some embodiments, the ion-selective permeable membrane may include an inorganic material, such as an oxide or a glass. In more particular embodiments, one or more of the various layers disclosed herein, e.g., the 1D or 2D layer, the reaction, passivation, and/or permeable membrane layers, and the like may be fabricated or otherwise applied by a spin-coating, anodization, PVD, and/or sol gel method.
In a further aspect, a system is provided, such as a system configured for running one or more reactions so as to detect a presence and/or concentration change of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. As such, the system may include an array including one or more, e.g., a plurality of sensors, such as where each of the sensors includes a chemically-sensitive field-effect transistor having a conductive source, a conductive drain, and a reaction surface or channel extending from the conductive source to the conductive drain. In particular instances, the array may include one or more wells configured as one or more reaction chambers having the reaction surface or channel positioned therein. In some instances, the surface and/or channel of the chamber may include a one-dimensional (1D) or two-dimensional (2D) transistor material, a three-dimensional (3D) structural layer may be included, as well as a dielectric or reaction layer, a passivation layer, and/or the like.
The system may further include one or more of a fluidic component, such as for performing the reaction, a circuitry component, such as for running the reaction processes, and/or a computing component, such as for controlling and/or processing the same. For instance, a fluidics component may be included where the fluidic component is configured to control one or more flows of reagents over the array and/or one or more chambers thereof. Particularly, in various embodiments, the system includes a plurality of reaction locations, such as surfaces or wells, which in turn includes a plurality of sensors and/or a plurality of channels, and further includes one or more fluid sources containing a fluid having a plurality of reagents and/or analytes for delivery to the one or more surfaces and/or wells for the performance of one or more reactions therein. In certain instances, a mechanism for generating one or more electric and/or magnetic fields is also included.
The system may additionally include a circuitry component, such as where the circuitry component may include a sample and hold circuit, an address decoder, a bias circuitry, and/or at least one analog-to-digital converter. For instance, the sample and hold circuit may be configured to hold an analog value of a voltage to be applied to or on a selected column and/or row line of an array of a device of the disclosure, such as during a read interval. Additionally, the address decoder may be configured to create column and/or row select signals for a column and/or row of the array, so as to access a sensor with a given address within the array. The bias circuitry may be coupled to one or more surfaces and/or chambers of the array and include a biasing component such as may be adapted to apply a read and/or bias voltage to selected chemically-sensitive field-effect transistors of the array, e.g., to a gate terminal of the transistor. The analog to digital converter may be configured to convert an analog value to a digital value
A computing component may also be included, such as where the computing component may include one or more processors, such as a signal processor; a base calling module, configured for determining one or more bases of one or more reads of a sequenced nucleic acid; a mapping module, configured for generating one or more seeds from the one or more reads of sequenced data and for performing a mapping function on the one or more seeds and/or reads; an alignment module, configured for performing an alignment function on the one or more mapped reads; a sorting module, configured for performing a sorting function on the one or more mapped and/or aligned reads; and/or a variant calling module, configured for performing a variant call function on the one or more mapped, aligned, and/or sorted reads. In particular instances, the base caller of the base calling module may be configured to correct a plurality of signals, such as for phase and signal loss, to normalize to a key, and/or to a generate a plurality of corrected base calls for each flow in each sensor to produce a plurality of sequencing reads. In various instances, the device and/or system may include at least one reference electrode.
Particularly, the system may be configured for performing a sequencing reaction. In such an instance, the FET sequencing device may include an array of sensors having one or more chemically-sensitive field-effect transistors associated therewith. Such transistors may include a cascode transistor having one or more of a source terminal, a drain terminal, and or a gate terminal, such as composed of a damascene copper. In such an instance, the source terminal of the transistor may be directly or indirectly connected to the drain terminal of the chemically-sensitive field-effect transistor. In some instances, a one or two dimensional channel or other suitably configured surface element may be included and may extend from the source terminal to the drain terminal, such as where the 1D channel material may be a carbon nanotube or nanowire, and the two-dimensional channel material may be composed of graphene, silicene, a phosphorene, a molybdenum disulfide, and a metal dichalcogenide. The device may further be configured to include a plurality of column and row lines coupled to the sensors in the array of sensors. In such an instance, each column line in the plurality of column lines may be directly or indirectly connected to or otherwise coupled to the drain terminals of the transistors, e.g., cascode transistors, of a corresponding plurality of sensors and/or pixels in the array, and likewise each row line in the plurality of row lines may be directly or indirectly connected to or otherwise coupled with the source terminals of the transistors, e.g., cascode transistors, of a corresponding plurality of sensors in the array.
In some instances, a plurality of source and drain terminals having a plurality of reaction surfaces, e.g., channel members, extended there between may be included, such as where each channel member includes a one or two or even three dimensional material. In such an instance, a plurality of first and/or second conductive lines, and so forth, may be coupled to the first and second source/drain terminals of the chemically-sensitive field-effect transistors in respective columns and rows in the array, and so forth. Additionally, control circuitry may be provided and coupled to the plurality of column and row lines such as for reading a selected sensor connected to a selected column line and/or a selected row line. The circuitry may also include a biasing component having a bias circuitry such as is configured to apply a read voltage, while the sample and hold circuit may be configured to hold an analog value of a voltage on a selected column line of the array during a read interval. Particularly, the bias circuitry may be configured for applying a read voltage to the selected row line, and/or to apply a bias voltage such as to the gate terminal of a transistor, such as FET and/or cascode transistor of the selected sensor. In a particular embodiment, the bias circuitry may be coupled to one or more chambers of the array and be configured to apply a read bias to selected chemically-sensitive field-effect transistors via the conductive column and/or row lines. Particularly, the bias circuitry may be configured to apply a read voltage to the selected row line, and/or to apply a bias voltage to the gate terminal of the transistor, e.g., cascode transistor, such as during a read interval.
A sense circuitry may also be included and coupled to the array so as to sense a charge coupled to one or more of the gate configurations of a selected chemically-sensitive field-effect transistor. The sense circuitry may be configured to read the selected sensor based on a sampled voltage level on the selected row and/or column line. In such an instance, the sense circuitry may include one or more of a pre-charge circuit, such as to pre-charge the selected column line to a pre-charge voltage level prior to the read interval; and a sample circuit such as to sample a voltage level at the drain terminal of the selected transistor, such as during the read interval. A sample circuit may further be included and contain a sample and hold circuit configured to hold an analog value of a voltage on the selected column line during the read interval, and may further include an analog to digital converter to convert the analog value to a digital value.
In particular embodiments, the computer component of the FET, e.g., CMOS, structure may include a processor configured for controlling the performance of one or more reactions involving a biological or chemical material so as to obtain reaction results, and for analyzing those results, for instance, based on detecting and/or measuring changes in a voltage (V) potential, current (I), or capacitance occurring on the chemically-sensitive field effect transistor. Particularly, the processor, such as a signal processor, may be configured so as to generate one or more current (I) vs. voltage (V) curves, such as where the current I of the I-V curve is the current applied between the source and drain of the chemically sensitive field effect transistor and/or where the gate voltage (Vg) of the I-Vg curve is a gate or channel voltage applied to the chemically-sensitive field effect transistor. In such an instance, the gate voltage Vg of the I-Vg curve is a top and/or a back gate voltage that may be applied to the chemically sensitive field effect transistor through a top (or front) and/or back of the device, respectively. Hence, a suitably configured device of the disclosure may be adapted as a front and/or back-gated device, which may further be configured as a solution gate. Accordingly, in various embodiments, a device of the disclosure may be a field-effect transistor that includes a chamber adapted for measuring ion concentrations in a solution; such as where, when the ion concentration (such as H+ or OH− in a pH scale) within the chamber changes, the current through the transistor, e.g., a gate region thereof, will change accordingly. In such an instance, the solution, when added to the chamber forms, or otherwise serves as, a gate electrode.
Hence, in specific embodiments, the gate voltage Vg of the I-Vg curve may be a solution gate voltage such as applied to the chemically sensitive field effect transistor through a solution flowed over a portion, e.g., a chamber, of the device. In some embodiments, the reference I-Vg curve and/or a chemical reaction I-Vg curve may be generated in response to the biological material and/or chemical reaction that is to be detected and/or occurs over or near the chemically-sensitive field effect transistor, such as within a chamber or well of the FET structure. In various embodiments, the processor may be configured to determine differences in relationships between a generated reference I-Vg curve and/or chemical reaction I-Vg curve. In certain instances, the circuitry component may include at least one analog-to-digital converter that is configured for converting analog signals, such as obtained as a result of the performance of the reaction(s) within the reaction well, or array of wells, into digital signals.
Accordingly, in another aspect, a chemically-sensitive field effect transistor device may be provided, wherein the device may include a structure having a conductive source and drain as well as having a surface or channel or other functionally equivalent surface structure extending from the conductive source to the conductive drain, such as where the surface or channel may include a one-, two-, or three-dimensional transistor material. The device may also include a processor such as where the processor is configured for generating a reference I-Vg curve and/or generating a chemical reaction I-Vg curve, in response to the chemical reaction occurring within a chamber of the chemically-sensitive field effect transistor, and may be configured to determine a difference between the reference I-Vg curve and the chemical reaction I-Vg curve.
In some instances, the difference between the reference I-Vg curve measurement and the chemical reaction I-Vg curve measurement is a shift in a minimum point of the Vg value of the chemical reaction I-Vg curve relative to a minimum point of the Vg value of the reference I-Vg curve. In other instances, the difference between the reference I-Vg curve and the chemical reaction I-Vg curve is a shift in an ion value of the chemical reaction I-Vg curve relative to an ion value of the reference I-Vg curve, for instance, where the ion values are taken from a p-type or n-type section of the I-Vg curve. For example, the measurements of the slopes may be taken from the steepest and/or flatest sections on the p-type and/or n-type portions of the I-Vg curves. In particular instances, the difference between the reference I-Vg curve and the chemical reaction I-Vg curve is a shift in an Ioff value of the chemical reaction I-Vg curve relative to an Ioff value of the reference I-Vg curve. In one embodiment, the difference between the reference I-Vg curve and the chemical reaction I-Vg curve is a change in the slope of the chemical reaction I-Vg curve relative to a change in the slope of the reference I-V g curve. In another embodiment, the difference between the reference I-Vg curve and the chemical reaction I-Vg curve is an overall change in shape of the chemical reaction I-Vg curve relative to an overall change in shape of the reference I-Vg curve. In other embodiments, the difference in overall shape of the I-Vg curves is determined by first fitting a polynomial or other fitting line to each of the I-Vg curves and then comparing the coefficients of those fitting lines. In other embodiments, the difference between a reference I-Vg curve and the chemical reaction I-Vg curve is based on more than one chemical reaction I-V g curve.
Accordingly, in particular embodiments, the FET and/or processor may be configured to respond to a shift in the I-V or I-Vg curve, such as where the curve is shifted in response to the detection of a biological compound and/or the result of a reaction taking place in or on a surface of the FET device. In some instances, the I-V/I-Vg curve may be produced and/or shifted in response to a chemical reaction occurring on a reaction layer and/or the surface of a 1D or 2D, e.g., graphene, surface of the field effect transistor, such as resulting from the detection of a biological compound or reaction occurring within the well structure of the device. Hence, the FET and/or processor may be configured so as to shift the I-V curve or I-Vg curve such as in response to the chemical reaction. In various embodiments, one or more elements and/or methods, as herein described, may be used to shift a reference I-V or I-Vg curve and/or a chemical reaction I-Vg curve so that the difference between the reference I-Vg curve and a chemical reaction I-Vg is more pronounced. For instance, the device may include a structure, such as a membrane, other surface layer, and/or other element configured for enhancing the ability of the processor to determine the difference between various I-V and/or I-Vg curves.
Hence, in a further aspect, a chemically-sensitive FET transistor that is fabricated on a primary structure having a stacked configuration including an inorganic base layer, e.g., a silicon layer; a dielectric and/or an organic or inorganic insulator layer, such as a silicon dioxide layer; a 1 D, 2D, or 3D material layer, such as a carbon nanotube, nanowire, or graphene layer; a reaction, e.g., oxidation, and/or passivation layer; and further having a conductive source and drain embedded in one or more of the layers, such as between and/or forming a gate structure, e.g., a solution gate region, may be provided. In various embodiments, the gate region may be configured so as to form a chamber or well and the 1D or 2D material and/or oxidation layers may be positioned between the conductive source and drain in such a manner as to form a bottom surface of the chamber. The structures may further include or otherwise be associated with an integrated circuit and/or a processor, such as for generating and/or processing generated data, such as sensor derived data.
Accordingly, in particular embodiments, a further structured layer, e.g., a secondary or tertiary structure, may also be provided, such as where the further structured layer may be included and/or present within the well or chamber, such as to enhance the ability of the processor to determine the difference between the current and/or voltages as well as their respective associated curves. More particularly, the additional structure may include an ion-selective permeable membrane, such as an ion-selective permeable membrane that allows ions of interest to pass through the membrane while blocking other ions, such as to enhance the ability of the processor to determine the difference between the reference I-V or I-Vg curve and the chemical reaction I-V or I-Vg curve, and thus enhance the ability of the processor to detect a desired chemical reaction. In various instances, the FET may be configured such that the I-V or I-Vg curve(s) may be shifted so as to better respond to, detect, and/or otherwise determine a biological compound and/or a chemical reaction, such as a biological compound and/or a chemical reaction occurring on the 1D or 2D, e.g., graphene, surface of the chemically-sensitive field effect transistor. In particular instances, the ion-selective permeable membrane may include a 2D transistor material, e.g., graphene, which may or may not be electrically connected to the source and/or drain layer and/or channel.
Accordingly, in various instances, the ion-selective permeable membrane may be positioned within the well and/or over a passivation layer, an ion sensitive or reaction layer, a 1D and/or a 2D transistor material layer, and/or a dielectric layer that itself may be positioned over and/or otherwise form a part of the chamber or channel. In certain embodiments, the membrane layer may be or otherwise be associated with an ion getter material, such as an ion getter material that traps ions that may or may not be relevant to the biological species and/or chemical reaction to be sensed and/or determined, such as to enhance the ability of the processor to determine the difference between the reference I-V or I-Vg curve and/or the chemical reaction I-V or I-Vg curve, e.g., because there are fewer interfering ions, thus enhancing the ability of the processor to detect the desired biological species and/or results of the chemical reactions. Particularly, the ion getter material may be arranged within proximity to the chamber and/or surface thereof so that the action of gettering the unwanted ions improves the detection capability of the chemically-sensitive field effect transistor. In some instances, one or more of the various layers herein, such as the ion getter material may be placed over one or more of the other layers, such as the dielectric layer, oxide layer, or 1D or 2D or 3D layers, positioned in proximity to one or more of the chambers, channels, or surfaces of the FET device.
In particular instances, an additional material, e.g., HMDS, may be included so as to manage the interaction of the chamber and/or channel and/or associated oxide layer and/or underlying 1D or 2D or 3D transistor layer. For instance, a chemically-sensitive field effect transistor of the disclosure may include a secondary or tertiary structure that includes a 2D transistor channel or surface which may include an ion-sensitive material over the channel or surface. In such an instance, the material may be sensitive to ions that are different from the ions associated with the biological molecule or chemical reaction that is to be detected. Particularly, in some instances, the action of sensing ions that are different from the ions associated with the biologics and/or chemical reactions that are to be detected allows the processor to filter out the signal from the unwanted ions from the signal of the ions of interest.
In a further aspect of the present disclosure, a system having a chemically-sensitive transistor, such as a field effect transistor (FET) including one or more chambers, e.g., a plurality of chambers having a well structure(s) formed therein is provided. In such an instance, the well(s) may be structured as a reaction location, wherein one or more chemical reactions may take place. In such an embodiment, the system may include a fluidics component having a fluid source, e.g., a reservoir, containing one or more fluids therein and configured for delivering the fluid from the reservoir to the reaction chamber, such as for the detection of a biologic and/or the performance of one or more chemical and/or biological reactions, such as a nucleic acid sequencing reaction. Hence, the fluidics component, e.g., the fluid source, may be in fluidic communication with the FET device configured for biological and/or chemical analysis.
Accordingly, in certain instances, the fluid may include one or more reactants, such as one or more analytes necessary for performing a sequencing reaction, as herein described. In a particular embodiment, the fluid may include one or more, e.g., a plurality of microbeads, having a nucleic acid template attached thereto, for instance, where the template is a DNA or RNA molecule to be sequenced, and the fluid containing the microbead is to be delivered to the well such as for carrying out the sequencing reaction. In such an embodiment, one or more of, e.g., each, of the plurality of microbeads may be configured so as to have electric charge and/or paramagnetic properties. The device may additionally include an electric and/or magnetic field component, e.g., having an electric and/or magnetic field generator, such as where the electric and/or magnetic field component is configured to generate an electric and/or magnetic field so as to interact with the electric and/or magnetic charge properties of each of the plurality of microbeads to attract the microbeads into a reaction location, such as a reaction surface, a channel, a well, a chamber, and/or a sensor of the FET device, such as by using electrophoresis and/or magnetism.
Hence, one or more, e.g., a plurality of microbeads, may be drawn onto or into a reaction location of the plurality of reaction locations, which locations may be formed as wells, e.g., one or more thin wells. The microbeads may include an analyte such as a biological material or a chemical material, e.g., one or more nucleotide sequences. Particularly, a fluid containing the analyte containing microbeads may be introduced into the wells, such as by a fluidics component of the disclosure. As the analyte may be a nucleic acid sequence having negative charge properties, an electric and/or magnetic field may be applied individually or collectively to the wells, so as to draw an analyte containing microbead onto each reaction location, e.g., into each well or sensor containing channel. In various instances, the electric and/or magnetic field component generates an electric and/or magnetic field so as to interact with the electric charge properties of the microbead thereby drawing it to the reaction location. In certain instances, the microbead itself may be charged and/or may have electric and/or magnetic properties, and thereby may be drawn to the reaction location using electrophoresis and/or magnetism.
The use of electrophoresis and/or magnetism allows for thinner reaction location structures. In particular instances, therefore, an electric and/or magnetic field generator may be configured for drawing and/or positioning a microbead within the well structure, such as in proximity to a channel or chamber of the device, and in other instances, the electric and/or magnetic field generator may be configured for reversing the electrical and/or magnetic field so as to repulse the microbead from the reaction location, channel, and/or chamber. In various instances, an array of reaction locations may be provided each having a magnet that allows for selective filling of the reaction locations with different numbers and/or types of microbeads, such as at select reaction locations. In such an instance, multiple electric and/or magnetic field generators for selective filling of reaction locations, e.g., wells.
Accordingly, one aspect of the present disclosure is a system and/or a method for positioning one or more, e.g., a plurality, of microbeads, e.g., containing one or more DNA and/or RNA templates attached thereto, within a reaction or plurality of reaction locations for biological or chemical analysis, such as for nucleic acid sequencing. The system may include a CMOS FET device having an integrated circuit structure configured for performing a biological or chemical analysis, such as within a plurality of nano- or micro-reaction wells, as described above, having a fluidic component, a circuitry component, and/or a computing component, and the method may include one or more of the following steps.
For instance, the method may include the fluidic component introducing a fluid to be in contact with the device, such as where the fluidics component is configured to control a flow a fluid of reagents over the array, and the fluid may include one or more microbeads that may have electric charge and/or paramagnetic properties. In such an instance, the device may include an integrated circuit structure, a plurality of reaction locations having one or more wells, a plurality of sensors and/or a plurality of channels, and/or an electric and/or magnetic field component. The electric field and/or magnetic field component may be configured to activate the electronic and/or magnetic field, and the method may also include activating an electric and/or magnetic field so as to interact with the electric and/or paramagnetic properties of each of the microbeads. The method may additionally include drawing the one or more microbeads into a reaction location of the plurality of reaction locations using electrophoresis and/or magnetism. In certain instances, the method may include positioning the one or more microbeads within the one or more reaction locations for biological or chemical analysis.
In particular instances, the electric and/or magnetic fields may be generated by the plurality of electric and/or magnetic field generators, e.g., included in the integrated circuit structure, in all or only a subset of the plurality of reaction locations so as to only attract a plurality of microbeads to the subset of reaction locations, such as for selectively filling the plurality of reaction locations with the plurality of microbeads. In such an instance, different types of microbeads may be attracted to different reaction locations, such as by pulsing the voltage and/or magnetic generators and/or keeping the same constant. Particularly, where an electric field generator is provided the voltage applied to the device may be variable or constant and may be less than about 10V, such as about less than 8V, or less than about 6V, including less than about 4V or about 2V or 1V. The voltage may be applied between a location above the fluid and a location on or below the reaction location, such as above the package lid and/or below the metal plate below the package. In certain instances, the location below the reaction location may be a metal or conductive layer such as within the package or package substrate. The method may also include the step of reversing the electric or magnetic field so as to eject the plurality of beads from the plurality of wells, sensors, and/or channels, either entirely or selectively.
Further, as indicated, each or a subset of the plurality of reaction locations may be utilized to generate electric fields to attract a microbead thereby allowing for programmability to each or a subset of reaction locations, for instance, 99% or 95% or 90% or 85%, or 80% or less of the plurality of wells are occupied with a microbead. Hence, the electric and/or magnetic field may be generated in only a subset of the plurality of wells, sensors or channels to only attract a plurality of microbeads to the subset. Likewise, a plurality of electric and/or magnetic field generators for selective filling the plurality of wells, sensors or channels with the plurality of microbeads, and/or ejecting the plurality of beads from the plurality of wells, sensors or channels. In such an instance, the electric and/or magnetic field generator may be an electric source, a permanent magnet and/or an electromagnet. As indicated, the plurality of magnetic field generators is configured to reverse the magnetic field to eject the plurality of microbeads from the plurality of reaction locations or a subset thereof.
Additionally, in one aspect of the present disclosure, a device, system, and/or method for verifying well occupancy for a plurality of wells for analysis of biological or chemical materials may be provided. For instance, a device of the system may include a plurality of wells having a plurality of sensors, such as where each well includes a graphene layer, and each sensor is configured as a field effect transistor. In such instances, the system may include a device for receiving a fluid containing the plurality of microbeads. Particularly, the device may include a processor, a CMOS structure having an integrated circuit, a plurality of wells, and a plurality of sensors within the CMOS structure. Each of plurality of wells may be configured to receive a microbead of the plurality of microbeads, and the CMOS structure may include a mechanism for drawing and/or ejecting the beads into or out of the wells. Hence, the method may include the step of flowing the plurality of microbeads over and/or into the plurality of reaction locations and/or wells and/or may include determining, e.g., through electrical and/or magnetic sensing if a reaction location and/or well is occupied or unoccupied and/or if a well contains one or multiple microbeads.
Consequently, the processor may be configured to determine if a well is unoccupied and/or if the well contains one or more, e.g., multiple microbeads. In certain instances, the processor may also be configured to eliminate or modify one or more of the measurements, such as based on the number of wells occupied or unoccupied, e.g., the number of wells containing none, one or multiple microbeads. For instance, the processor may be configured to eliminate from the measurement the number of wells unoccupied and the number of wells containing multiple microbeads, or compensate in the measurement for the number of wells unoccupied and the number of wells containing multiple microbeads, and the like.
In such instances, the measurement may be a shift in an I-V or I-Vg curve. In particular instances, the processor may be configured to eliminate from the measurement the number of wells unoccupied and the number of wells containing one or multiple microbeads and/or to compensate in the measurement for the number of wells unoccupied and the number of wells containing one or multiple microbeads. Accordingly, in some embodiments, the measurement may be a shift in an I-V or I-Vg curve, such as one or more of: generating a plurality of I-V or I-Vg curves so as to determine a shift in response to a chemical reaction occurring on or near the chemically-sensitive field effect transistor; generating a chemically-sensitive field-effect transistor I-V or I-Vg curve in response to a chemical reaction occurring on or near the chemically-sensitive field-effect transistor so as to detect a change in the slope of the I-V curve; and/or to sense shifts in a capacitance as a function of a gate voltage.
Having briefly described the present technology, the above and further objects, features and advantages thereof will be recognized by those skilled in the pertinent art from the following detailed description of the invention when taken in conjunction with the accompanying drawings.
Having briefly described the present technology, the above and further objects, features and advantages thereof will be recognized by those skilled in the pertinent art from the following detailed description of the invention when taken in conjunction with the accompanying drawings.
Accordingly, provided herein are devices, systems, and methods of employing the same for the performance of one or more chemical and/or bioinformatics analysis operations. Particularly, the devices, systems, and methods of the disclosure are directed in part to 1D, 2D, or 3D field effect transistor (FET) sensors, integrated circuits, and arrays employing the same for analyte measurements. The present FET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved 1D, 2D, or 3D FET sensor and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small sensor sizes and dense sensor array designs.
More particularly, such improved fabrication techniques employing 1D, 2D, e.g., graphene, or 3D materials as a reaction layer or structure provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect the presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization, and/or nucleotide and/or protein sequencing reactions. Accordingly, in particular examples, graphene Field Effect Transistor (gFET) arrays facilitate genetic and/or protein sequencing techniques based on monitoring changes in various reactants within a zone associated with the array, such as changes in ion concentration, e.g., changes in hydrogen ion concentration (pH), or changes in other analyte concentrations, and/or binding events associated with chemical processes relating to sequencing synthesis, such as within a gated reaction chamber of the gFET based sensor. Particularly, the present disclosure is a chemically-sensitive graphene layered field-effect transistor for analysis of biological and/or chemical materials that solves many of the current problems associated with nucleic acid sequencing, genetic, and/or bioinformatics diagnostics.
Accordingly, provided herein is a system for analysis of biological and/or chemical materials. In various embodiments, the system includes a substrate, where the substrate includes one or more chamber and/or channel arrangements therein, such as where the chamber and/or a channel thereof may be associated with one or more sensors. In particular instances, a solution gated well structure is provided, such as where the well structure may be configured such that a biological and/or chemical reaction may take place within the well, such as proximate a channel structure therein. In various instances, the well is positioned on a portion of the substrate so as to align with an exterior surface of the channel of each sensor, such as where the well structure defines an opening allowing for direct fluid contact with the channel.
In various instances, the length of the interior surface, e.g., the channel, of the well, such as from the source to the drain may range from 0.05 micron to 3 microns, and a width of the surface and/or channel may range from 0.5 micron to 2 microns. In particular instances, the well structure may be configured to include or otherwise be associated with a nucleic acid template, such as a nucleic acid that may be directly or indirectly immobilized on a surface of the well. For instance, in certain instances, the nucleic acid template may be bound to an interior surface of the well chamber, such as on the substrate itself, or a layer associated therewith, e.g., a layer composed of a one- or two-dimensional transistor material. In various embodiments, the nucleic acid template may be bound to a secondary substrate, such as a bead positioned within the well, such as proximate the graphene layer.
Accordingly, in one aspect of the present disclosure, the sensor substrate may be configured as a chemically-sensitive field-effect transistor (FET). Particularly, in certain embodiments, a field effect transistor may be provided, such as where the FET includes a chamber having a channel structure incorporated therein. In particular embodiments, the chamber and/or the channel and/or a structure thereof may be optimized in such a manner so as to maximize the ratio of channel width (W) to channel length (L). For instance, the channel may include a 1D or 2D or 3D structure, such as where the channel and/or the channel structure includes a geometry that has been optimized to maximize the ratio of channel width (W) to channel length (L). This can be done through the use of interdigitated source and drain electrode geometries in a single plane or through the use of 2D and/or 3D electrode structures, such as a 3D interdigitated well structure.
In such an instance, the transistor may include a conductive source and a conductive drain forming the channel structure, which channel structure extends from the conductive source to the conductive drain. In such an instance, the opening of the well is positioned in relation to the channel so that the opening aligns with the positioning of the source and drain, and more particularly with the associated sensor. As indicated, in various embodiments, a bounding surface of the well includes a one-dimensional (1D) transistor material, such as a carbon nanotube (CNT) or a semiconductor nanowire, or a two-dimensional (2D) transistor material, such as composed of graphene, molybdenum disulfide, other metal dichalcogenides, and black phosphorous. In various instances, a three-dimensional (3D) structure may be included such as set forth in
For example, the transconductance through the channel may be modified in various manners, so as to modulate, e.g., increase, the sensitivity of the sensors, such as in the sensor array. Particularly, in various instances, it may be useful to configure the chamber and/or well so as to have a short channel length and a wide channel width, such as the shortest channel length and largest channel width possible, given the configuration of the one or more chambers in the one or more sensor arrays. More particularly, the equation for transconductance of the field effect transistors disclosed herein is: gm ∝μCov W/L Vsd where gm is the transconductance, μ is the carrier mobility, Cov is the overall capacitance of an included oxide or other layers over the transistor, W is the channel width, L is the channel length and Vsd is the voltage from the source to the drain. Since gm directly relates to the sensitivity of the sensor it is desirable to increase gm through the terms shown in the equation. In particular increasing the W/L ratio (maximizing W and minimizing L) will increase gm.
In particular instances, the length of the channel from the source to the drain ranges is less than 1 micron, such as less than 500 nm, including less than 50 nm, and in particular instances: as short as the fabrication process will allow without generating defects or results that render the device unusable. In one particular embodiment the channel length may be 20 nm or less. Conversely, the width of the channel may be as wide as feasible and/or possible. In such an instance as this, the width of the channel need not be governed by the fabrication process as much as by the design requirements of the overall sensor chip. For instance, in specific instances, hundreds of thousands to millions of sensors may be included in an exemplary sensor chip.
However, with such a large number of sensors, each individual sensor size and/or pitch, e.g., which may directly affect the channel width, should be kept reasonably small so as to prevent the chip from being so large as to be unable to be fabricated (e.g., such as exceeding the photolithography reticle size) or too expensive (e.g., due to the effect of defect density on a large chip size). Hence, in one implementation, e.g., of a rectangular channel design, a practical range of the channel width may be from 0.1 micron to 2 microns. As indicated above, in some instances, it may be desirable to increase the channel length to channel width ratio, such as through the use of various design techniques. In one particular exemplary instance, a structure, such as an interdigitated tooth and comb structure, can be provided such as for short channel lengths and large channel widths, such as within a relatively compact area, such as shown in
Another aspect of the present disclosure is the application of an ion sensitive layer to the channel to improve the sensitivity of the 1D or 2D or 3D material of the field effect transistor. Hence, the 1D and/or 2D layer may further be associated with an insulator material. For instance, the insulator material for the well structure may be an organic material, such as a polyimide or BCB, and/or may be an inorganic material, such as silicon oxide or silicon nitride. Alternatively, the channel is composed of a silicene. Additional alternative materials for the channel include borophene, WS2, boron nitride, stanene (2D tin), germanane, nickel HITP, and Mxenes (Ti2C, (Ti0.5, Nb0.5), V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3 and Ta4C3), and the like.
In particular instances, a reaction layer may be provided, such as a layer associated with the 1D or 2D, e.g., graphene, layer. For instance, in one embodiment, a thin (0.01 micron) passivation or etch stop layer may be placed over the graphene layer, such as in the case where a well etch process affects the graphene layer. In various instances, an oxide layer may be included, such as disposed within the chamber and/or channel thereof. Particularly, in various embodiments, a method for depositing the dielectric layer may include Atomic Layer Deposition (ALD). Another method for creating an analyte-sensitive layer may be to first deposit a metal layer (e.g., by sputtering or evaporation) onto the 1 D, 2D, or 3D material layer and then oxidizing the metal to form a metal oxide layer. It is further possible to combine material layers using different deposition processes such as to create an analyte-sensitive layer—for example a first layer may be comprised of sputtered metal that is oxidized, followed by a layer comprised of an ALD deposited oxide. It is also possible to combine two or more analyte-sensitive layers, such as comprised of different materials to create an overall analyte-sensitive layer stack. For example a first layer of metal, e.g., aluminum oxide, may be formed over the channel material and then a second layer of metal, e.g., tantalum oxide, may be formed over the aluminum oxide. In some embodiments an analyte-sensitive dielectric layer need not br required nor used.
However, where employed, the oxide layer may be configured so as to prevent the nucleic acid template, e.g., present on a micro- or nano-bead, as presented herein, from contacting the 1D or 2D material or other reaction layer of the chamber directly. The oxide layer may be composed of an aluminum oxide, tantalum oxide, and/or a silicon oxide. In various instances, the oxide layer may have a thickness of 9 nanometers or less. In further instances, the chemically-sensitive field-effect transistor can read through the oxide layer. In particular instances, the well structure may include a permeable membrane associated with the graphene layer.
In one aspect of the present disclosure is a chemically-sensitive transistor, such as a field effect transistor (FET) that is fabricated in a stacked configuration including a primary structure, such as a wafer, e.g., a silicon wafer, as well as one or more additional structures. For instance, an insulator material layer may also be included on top of the primary structure, and may be an inorganic material. The first and second structures may include a further structure containing one or more of a conductive source and/or a conductive drain, such as separated one from another by a space, and embedded in the primary and/or secondary structures and/or may be planar with a top surface of the secondary structure or a further layer or structure associated therewith. In various instances, the structures may further include a processor, such as for processing generated data, such as sensor-derived data. Accordingly, the structures may be configured as, or otherwise include, an integrated circuit, and/or may be an ASIC, a structured ASIC, or an FPGA.
For instance, as can be seen with respect to
The structured primary 10 and/or insulator layers 20 may further include a reaction layer 26. For instance, the stacked structured layers may be configured to include a further structure, such as a channel structure, which in turn may be adapted as the reaction layer 26. Particularly, in certain instances, the insulator layer 20 may include a channel 26, such as containing one or more of a conductive source 22 and/or a conductive drain 22, such as separated one from another by a space 26, and embedded in the primary structure 10 and/or insulator material 20, and/or may be planar with a top surface 21 of the insulator layer 20. The source 22 and drain 24 may be composed of metal, such as damascene. In various instances, the insulator material for the channel structure 26 may be an organic or an inorganic material. In a particular instance, the organic material may be a polymer, polyimide, BCB or other like material. In another instance, the inorganic material may be a silicon oxide, e.g., a silicon dioxide, or a silicon nitride or other metal oxide or nitride.
In particular instances, the structures may be configured as a complementary metal-oxide semiconductor (CMOS) 1, which in turn may be configured as a chemically-sensitive FET containing one or more of a conductive metal source 22, a conductive metal drain 24, a channel or other reaction zone 26, and/or a processor. For instance, the FET 1 may include a CMOS structure having an integrated circuit that is fabricated on a silicon wafer 10, which further includes a silicon dioxide insulator layer 20, including a conductive damascene copper source 22 and a conductive damascene copper drain 24, which may be embedded in at least the insulator layer 20. In various instances, the structures may include a surface 21, e.g., a top surface, which surface may include the channel 26, such as where the surface and/or channel may be configured as a reaction zone 26 that extends from the conductive source 22 to the conductive drain 24. An exemplary length of the surface and/or channel 26 from the source to the drain may range from about 0.001 microns to about 10 microns, such as from about 0.01 microns to about 5 microns, for instance, from about 0.05 micron to 3 microns, including about 0.1 or about 0.5 microns to about 1 or about 1.5 or about 2 microns. An exemplary width of the surface and/or channel from side to side may range from about 0.001 microns to about 10 microns, such as from about 0.01 microns to about 5 microns, for instance, from about 0.05 microns to 3 microns, including about 0.1 or 0.5 microns to about 1 or about 1.5 or about 2 microns.
In certain instances, the surface and/or channel region may form a reaction layer 26 that may include a material layer 30, which material layer may be a one-dimensional (1D) transistor material, a two-dimensional (2D) transistor material, a three-dimensional (3D) transistor material, and/or the like. Accordingly, in various instances, a 1D transistor material may be included, which 1D material may be composed of a carbon nanotube or a semiconductor nanowire. In other instances, a 2D transistor material may be included, which 2D material may include a graphene layer, silicene, molybdenum disulfide, black phosphorous, and/or metal dichalcogenides. In various instances, a 3D material may also be provided.
For instance, in various embodiments, the material layer may be a single layer, 2D material, such as a graphene layer 30. Particularly, as can be seen with respect to
Particularly, the single-layer, two-dimensional structure of graphene gives it at least three important characteristics with respect to its use herein: it creates the presence of a bandgap, it makes the graphene layer a semimetal, and it promotes rapid charge transport (mobility and high-field transport) at room temperature. Hence, in various instances, a graphene FET, as herein described performs better as a biological sensor than a typical CMOS-FET device not having such a reaction layer. For instance, with respect to hybridization detection and/or sequencing, a traditional MOSFET transistor may have fundamental limitations in its sensitivity (due to channel thickness and intervening insulating layers), whereas the present gFET with its single atom thickness can be employed to form a solution gated reaction zone and/or channel, wherein the graphene layer may be in direct contact with the chemical reaction zone. Specifically, the reaction layers may include a 1 D, 2D, and/or 3D structure 30 may be configured so as to have a much higher carrier mobility than the typical doped silicon commonly used in MOSFET or ISFET devices. This gives the herein disclosed 1 D, 2D, and/or 3D FET sensor devices increased sensitivity to and faster detection of chemical reactions. Further, in various instances, the surface and/or channel 26 may include or make up a dielectric layer, such as for further increasing sensor sensitivity and/or functioning.
Additionally,
In various instances, as can be seen with respect to
In various instances, a passivation layer 36 may be disposed or otherwise be included on the surface and/or channel 26, such as layered or otherwise deposited on the 1 D, 2D, e.g., graphene, or 3D layer 30 and/or on an associated reaction or oxidation layer 34 on the surface and/or channel 26. More particularly, the oxide and/or passivation layers may have a suitable thickness such as of from about 100 nm or about 75 nm to about 10 nm or 9 nm or less, such as about 0.5 microns or about 0.1 microns or about 50 nanometers or less to about 20 nanometers, such as about 15 nanometers, such as about 7 or about 5 nanometers or less, respectively.
As can be seen with respect to
Accordingly, as presented with respect to
In this instance, the surface structure 26 completely overlaps the source 22 and drain 24 regions. A further layer of material 35 may be positioned over the surface and/or channel region 26, which layer of material may further be etched or otherwise configured to include a well or chamber structure 38 having a bottom surface that may be positioned on or proximate a portion of an exterior surface of the 1D or 2D or 3D layer, such as to be coincident with the channel region 26. In such an instance, the well structure 38 may be a layered structure and may include a plurality of surfaces, such as first 39a and second 39b wall structures, such as extending from or otherwise being coincident with the surface of the reaction zone 26. For instance, the wall structures 29a and 29b may partially overlap the surface structure 26. Accordingly,
In particular instances, the well structure 38 may be configured so as to define an opening 37 that allows for direct contact with the surface 26, and thereby contact with the 1D, e.g., nanotube, nanowire, and/or 2D, graphene, layer. Hence, in various embodiments, the cavitated FET device may be configured so as to include a plurality of graphene wells or other chamber surfaces. In various instances, the FET device may be configured as a CMOS biosensor having a well structure 38 that further includes an oxide and/or passivation layer 34, as shown in
In some embodiments, as can be seen with respect to
In a particular embodiment, a multiplicity of the wells 38 of the chemically-sensitive device may include a reaction zone 26 containing a graphene layer 30 so as to form a graphene FET (gFET) array 1. As herein described, the gFET array 1 may be employed to facilitate DNA sequencing techniques, such as based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentrations, and/or binding events associated with chemical processes relating to DNA synthesis and/or hybridization reactions, such as within the gated reaction chamber or well 38 of the gFET based sensor 1. For example, the chemically-sensitive field effect transistor 1 may be configured as an array of CMOS biosensors and/or may be adapted to increase the measurement sensitivity and/or accuracy of the sensor(s) and/or associated array(s), such as by including one or more surfaces 26a-e or wells 38a-e having a surface layered with a 1D and/or 2D and/or 3D material 30, such as graphene, a dielectric or reaction layer 34, a passivation layer 36, and the like.
For instance, in a particular embodiment, illustrated in
Particularly, in various embodiments, each sensor of the plurality of sensors includes a graphene field effect transistor. For instance,
In various embodiments, one or more of the solution gates may include a graphene layered surface 30a-e, which in various instances may further include one or more oxide 34 and/or passivation 36 layers, such as layers that are disposed on the surface(s) of the bounding members of the wells or chambers 37 so as to increase the measurement sensitivity and/or accuracy of the sensors and/or associated array(s). Like above, in such instances, the solution gated chambers 37 of the arrays of the CMOS device may be configured as an ISFET, and be adapted for receiving the reactants necessary for performing various analyses of biological and/or chemical materials, for instance, one or more hybridization and/or sequencing reactions.
Accordingly, in one aspect, a system is provided, such as a system configured for running one or more reactions on biological and/or chemical materials so as to detect a presence and/or concentration change of various analyte types in a wide variety of chemical and/or biological processes. For instance, in some instances, the biological material may be a nucleic acid or other biological molecule, such as a protein, or the like. Hence, in particular instances, the system may be adapted for performing a DNA hybridization and/or sequencing reaction. In other instances, the analysis to be performed is for whole genome analysis, genome typing analysis, genomic panels, exome analysis, micro-biome analysis, and clinical analysis. In further analysis procedures, one or more clinical analysis may be performed such as a cancer analysis, NIPT analysis, and/or UCS analysis.
As such, the system may include an array 130 including one or more, e.g., a plurality of sensors, such as where each of the sensors includes or is otherwise associated with a chemically-sensitive field-effect transistor having a conductive source, a conductive drain, and a reaction surface or channel extending from the conductive source to the conductive drain. In particular instances, the array 130 may include one or more wells configured as one or more reaction chambers having the reaction surface or channel positioned therein. In some instances, the surface and/or channel of the chamber may include a one-dimensional (1D), or two-dimensional (2D), or three-dimensional (3D) transistor material, a dielectric or reaction layer, a passivation layer, and/or the like.
As can be seen with respect to
As can be seen with respect to
Additionally, as can be seen with respect to
Particularly, the system may be configured for performing a sequencing reaction. In such an instance, the device for performing the sequencing reaction may be adapted from a complementary metal-oxide semiconductor reformed to include one or more reaction chambers, e.g., micro or nano-wells, so as to form an array 130. The array 130 may be associated with one or more sensors having one or more chemically-sensitive field-effect transistors linked therewith. Such transistors may include a cascode transistor having one or more of a source terminal, a drain terminal, and or a gate terminal, such as forming a reaction zone. In such an instance, the source terminal of the transistor may be directly or indirectly connected to the drain terminal of the FET. In some instances, the gate terminal may be or may otherwise include a channel configuration, and may further include a one or two dimensional material associated with the gate. The 1D or 2D material may extend from the source terminal to the drain terminal, such as where the 1D channel material may be a carbon nanotube or nanowire, and the 2D channel material may be composed of graphene, silicene, a phosphorene, a molybdenum disulfide, and a metal dichalcogenide. The device may further be configured to include a plurality of arrays, such as arranged as one or more lines of columns and rows coupled to the sensors in the array of sensors. In such an instance, each column line in the plurality of column lines may be directly or indirectly connected to or otherwise be coupled with the drain terminals of the transistors, e.g., cascode transistors, of a corresponding plurality of sensors or pixels in the array, and likewise each row line in the plurality of row lines may be directly or indirectly connected to or otherwise coupled with the source terminals of the transistors, e.g., cascode transistors, of a corresponding plurality of sensors in the array.
In some instances, a plurality of source and drain terminals having a plurality of reaction surfaces, and/or associated channel members, extended there between may be included, such as where each channel member includes a one or two dimensional material. In such an instance, a plurality of first and/or second conductive lines may be coupled to the first and second source/drain terminals of the chemically-sensitive field-effect transistors in respective columns and rows in the array. Additionally, control circuitry 140 may be provided and coupled to the plurality of column and row lines such as for reading a selected sensor connected to a selected column line and/or a selected row line. The circuitry may also include a biasing component 142 such as may be configured for applying a read voltage to the selected row line, and/or to apply a bias voltage such as to the gate terminal of a transistor, such as FET and/or cascode transistor of the selected sensor. In a particular embodiment, the bias circuitry 142 may be coupled to one or more chambers of the array 130 and be configured to apply a read bias to selected chemically-sensitive field-effect transistors via the conductive column and/or row lines. Particularly, the bias circuitry 142 may be configured to apply a read voltage to the selected row line, and/or to apply a bias voltage to the gate terminal of the transistor, e.g., cascode transistor, such as during a read interval.
A sense circuitry may be included and coupled to the array so as to sense a charge coupled to one or more of the gate configurations of a selected chemically-sensitive field-effect transistor. Sense circuitry may also be configured to read the selected sensor based on a sampled voltage level on the selected row and/or column line. In such an instance, the sense circuitry may include one or more of a pre-charge circuit, such as to pre-charge the selected column line to a pre-charge voltage level prior to the read interval; and a sample circuit such as to sample a voltage level at the drain terminal of the selected transistor, e.g., cascode transistor, such as during the read interval. The sample circuit may also be included and contain a sample and hold circuit 143 configured to hold an analog value of a voltage on the selected column line during the read interval, and may further include an analog to digital converter 141 to convert the analog value to a digital value.
In a further aspect, as seen with respect to
The well structure 38 may further include one or more additional structures and/or layers, such as a 1D or 2D or 3D material 30 and/or an oxidation 34 and/or passivation 36 layers that may be positioned between the conductive source 22 and drain 24 and/or between wall members 39a and 39b in such a manner as to form a bottom surface and/or reaction zone 26 of the chamber 37. In various instances, one or more of the structures may further include or otherwise be associated with an integrated circuit and/or a processor, such as for generating and/or processing generated data, such as sensor derived data, e.g. indicative of a sequencing and/or hybridization reaction taking place within the well structure 38. In particular embodiments, a further structured layer 40, e.g., a secondary or tertiary or quartier structure, may also be provided, such as where the further structured layer may be included and/or present on a surface 26 or otherwise within the well or chamber 37, such as to enhance the ability of the sensor and/or the processor to determine the difference between a current and/or voltage applied across the source 22 and/or drain 24 of the transistor, as well as their respective associated charge curves, as described herein.
For instance, in the exemplary embodiment of
For example, in particular instances, the membrane material 40 may be an organic or an inorganic material. A suitable membrane may be an inorganic material such as an oxide. An alternative material may be a separate layer, such as an additional 1D or 2D material, e.g., of graphene, which is not electrically connected to the FET or its component parts, e.g., the source 22 and drain 24. Another alternative material may be a polymer, such as Nafion, PEEK, a perfluorosulphonic, and/or a perfluorocarboxylic material. Alternatively, the material may be a HMDS or other siloxane, such as positioned under a graphene layer 30. Yet another alternative may be a getter material, such as containing a positive ion, e.g., NA+, which may be positioned within the chamber 37, or may be positioned elsewhere on the sensor, such as a wall 39a and/or 39b thereof, and/or in a package that is adapted to attract unwanted ions. In another embodiment, the sensor enhancement material 40 may be an ion-selective functional layer(s) that is positioned over the sensor and adapted so as to detect contaminants, unwanted ions, or other impurities that may react with the reactants within the well 38 such that their interactions with the sensor 1 and thus the various determinations that the sensor 1 makes with respect to the reactions taking place therein, such as in relation to detecting the presence or absence of a desired ion, can be filtered out.
Accordingly, the chemically-sensitive field-effect transistors, as presented herein, for a system for analysis of biological and/or chemical materials, may be configured as solution gated field effect transistor devices having rows and columns of reaction chambers formed therein. In various instances, the field-effect transistors comprise a structure having or otherwise being associated with a channel and a processor. In such instances, the structure may include one or more of an insulating structure, a conductive source, a conductive drain, and/or a channel extending from the conductive source to the conductive drain, such as where the source and drain are embedded in the insulator and may be positioned therein so as to be planar with a top surface of the insulator. As indicated, in certain embodiments, the source and drain may each composed of a damascene copper material. Further, the channel may be composed of a one dimensional transistor material or a two-dimensional transistor material. And where desired, a reaction layer may be associated with the graphene layer, and in some instances, may include a passivation layer or etch stop layer that may be placed over the channel, such as between the two layers and/or above the graphene layer.
As can be seen with respect to
The source 22 and the drain 24 are separated from one another and positioned relative to the graphene layer 30 so as to form a gate structure 26. In this embodiment, the gate structure 26 is further bounded by chamber walls 29a and 29b, which together form the well 28 into which a fluid may be delivered, such as for the performance of a bio-chemical reaction, and thus, forming a solution gate configuration. Particularly, an additional layer 35, which may also be composed of silicon dioxide, may be positioned above the first silicon dioxide layer 20, and be configured, e.g., via micro etching, to form a micro- or nano-well 38 so as to form a chamber 37, which chamber 37 may be adapted to receive a solution so as to form the solution gate region. The graphene layer 30 is disposed between the first 20 and second 35 silicon dioxide layers such as to form the bottom surface of the chamber 37. In this instance, the FET sensor is configured to detect a change in ion concentration, e.g., pH, which occurs within the well 38 such as when a solution containing reactants is added to the gate region within the chamber 37, and the reactants interact with an additional element contained within the chamber, such as a bound nucleic acid template.
Particularly, one or more solutions may be added to the chamber 37, such as in the performance of a bio-chemical reaction. For instance, a first solution including a nano- or micro-bead 60 may be added to the well 38. The nano- or micro-bead may be treated so as to be associated with one or more biopolymers, such as a DNA and/or RNA template 65. Once the nano- or micro-bead containing solution is added to the well 38, in such a manner that the bead 65 is retained therein, one or more additional solutions containing reactants, such as for the performance of a biological and/or chemical reaction, may then be added to the well 38. For example, where the biological and/or chemical reaction is a nucleotide synthesis reaction, the analyte containing solution to be added to the well 38 may include a nucleotide and/or polymerase composition that if the conditions are suitable within the chamber 37 will result in a binding event occurring between the template molecule 65 and the nucleotide reactant, thus resulting in the reaction taking place. Additionally, where the biological and/or chemical reaction is a hybridization reaction, the bound template molecule 65 may be configured as a probe, and the analyte containing solution to be added to the well 38 may include an additional DNA/RNA molecule of interest, which if the conditions within the chamber 37 are suitable will hybridize to the bound probe, thus resulting in the reaction taking place.
In either instance, the sensor 1 may be configured for detecting the occurrence of a reaction event taking place, such as by detecting a change in the ionic concentration within the solution within the chamber 37. Particularly, if the conditions are suitable for a reaction to take place, e.g., the appropriate reactants are present, a binding event will occur in such a manner that an ion, such as an H+ ion, will be released into solution, such as within the chamber 37 and/or proximate the solution gate 26. In such an instance, the sensor 1 may be configured to sense the evolution of the ion, appreciate the change in pH, and detect that a reaction has taken place. In such a manner as this, a DNA/RNA molecule may be synthesized and/or a hybridization event determined.
Accordingly, as illustrated with respect to
In some instances, it may be useful to provide a mechanism for assisting the targeting of the microbead(s) 60 to the reaction zone 26 of the FET 1. Particularly, as can be seen with respect to
More particularly, the reaction zone 26 of the FET 1 may be configured to include a channel region that is formed to correspond to the region, e.g., point, of contact between the surface of the graphene layer 30 and the bead 60. Further, to facilitate this contact, the FET 1 may include an attracting mechanism 70 that is configured to attract or otherwise draw the bead 60 in to proximity of the reaction zone and/or channel 26. For instance, in particular instances, the nano- or micro-bead 60 may include a charged and/or metallic element, and the attracting mechanism 70 may be configured so as to generate an electric and/or magnetic field, such as for drawing the bead 60 to the reaction zone 26. For example, in some embodiments, the electric field generator 70 may be a pulse generator, and in other embodiments, such as illustrated in
Particularly, as shown in
Alternatively, in other embodiments, such as presented in
For example, the bead 60 may be configured to have an electric charge property and the bead attracting mechanism 60 may be configured to emit an electric field that is opposite in nature to the charge on the bead and is thereby adapted for draw the bead 60 into proximity of the reaction surface 26. In such an instance, an electric field component generates an electric field to interact with the electric charge properties of the microbead. Hence, the microbead may be drawn to the reaction location using electrophoresis. In other instances, the bead 60 may be configured to include paramagnetic properties so as to assist it in being drawn or otherwise attracted toward reaction surface 26, e.g., into the well 38, and into proximity of the reaction zone, where the reaction may take place. The device, therefore, may include a magnetic field generating component 70 that is configured to apply an electro-magnetic field that is focused within the chamber 38 so as to interact with the paramagnetic properties of the bead 60 thereby drawing it into the chamber 38 and/or proximate the reaction surface 26, such as via magnetism. Particularly, in various embodiments, the bead attracting mechanism 60 may be configured to emit a magnetic field that is opposite in polarity to the paramagnetic properties of the bead and is thereby adapted for draw the bead 60 into proximity of the reaction surface 26. In such an instance, a magnetic field component generates a magnetic field to interact with the polar properties of the microbead. The use of magnetism and/or electrophoresis allows for thinner reaction location structures.
Additionally, as illustrated in
As illustrated in
Particularly, as set forth in
Particularly, in a further aspect of the present disclosure, a system having an array of chemically-sensitive transistors, such as field effect transistors (FET) including a plurality of chambers 37a-e having well structures formed therein is provided. In such an instance, the wells 38a-e may be structured as or may otherwise include reaction locations, 26a-e, wherein one or more chemical reactions may take place. In such an embodiment, the system may include one or more fluidics components having one or more fluid sources, e.g., reservoirs, containing one or more fluids therein and configured for delivering the fluid from the reservoir to the reaction chamber, such as for the detection of a biologic and/or the performance of one or more chemical and/or biological reactions, such as a nucleic acid sequencing reaction. Accordingly, the fluidics component, e.g., the fluid source, may be in fluidic communication with the FET device configured for biological and/or chemical analysis, and may be configured for controlling a flow of reagents over the array.
Accordingly, in certain instances, the fluid may include one or more reactants, such as one or more analytes necessary for performing a sequencing reaction, as herein described. In a particular embodiment, the fluid may include one or more, e.g., a plurality of microbeads 60, having a nucleic acid template 65 attached thereto, for instance, where the template is a DNA or RNA molecule to be sequenced, and the fluid containing the microbead 60 is to be delivered to the well 38 such as for carrying out the sequencing reaction. In such an embodiment, one or more of, e.g., each, of the plurality of microbeads may be configured so as to have electric charge and/or paramagnetic properties. The device may additionally include an electric and/or magnetic field component, e.g., having an electric and/or magnetic field generator, such as where the electric and/or magnetic field component is configured to generate an electric and/or magnetic field so as to interact with the electric and/or magnetic charge properties of each of the plurality of microbeads to attract the microbeads into a reaction location, such as a reaction surface, a channel, a well, a chamber, and/or a sensor of the FET device, such as by using electrophoresis and/or magnetism.
Hence, one or more, e.g., a plurality of microbeads 60a-e, may be drawn onto or into a reaction location of the plurality of reaction locations 37a-e, which locations may be formed as wells, e.g., one or more thin wells. The use of magnetism or electrophoresis allows for thinner reaction location structures. In particular instances, electric and/or magnetic field generator may be configured for drawing and/or positioning the microbeads within the well structure 37, such as in proximity to a channel or chamber of the device, and in other instances, the electric and/or magnetic field generator may be configured for reversing the electrical and/or magnetic field so as to repulse the microbead(s) 60 from the reaction location, channel, and/or chamber 37. In various instances, an array of reaction locations may be provided each having a magnet 70a-e that allows for selective filling of the reaction locations with different numbers and/or types of microbeads 60, such as at select reaction locations 37a-e. In such an instance, multiple electric and/or magnetic field generators for selective filling of reaction locations, e.g., wells.
Accordingly, one aspect of the present disclosure is a system and/or a method for positioning one or more, e.g., a plurality, of microbeads 60 within a reaction or plurality of reaction locations 37 for biological or chemical analysis, such as for nucleic acid sequencing. The system may include a CMOS FET device having an integrated circuit structure configured for performing a biological or chemical analysis, such as within a plurality of nano- or micro-reaction wells, as described above, having a fluidic component 120, a circuitry component 140, and/or a computing component 150, and the method may include one or more of the following steps. For instance, the method may include the fluidic component 120 introducing a fluid to be in contact with the device 1, such as where the fluidics component is configured to control a flow a fluid of reagents over the array 1, and the fluid may include one or more microbeads 60 that may have electric charge and/or paramagnetic properties. In such an instance, the device may include an integrated circuit structure, a plurality of reaction locations 37 having one or more wells, a plurality of sensors and/or a plurality of channels, and/or an electric and/or magnetic field component 70. The electric field and/or magnetic field component 70 may be configured to activate the electronic and/or magnetic field, and the method may also include activating an electric and/or magnetic field so as to interact with the electric and/or paramagnetic properties of each of the microbeads 60. The method may additionally include drawing the one or more microbeads 60 into proximity with a reaction zone 26 of the plurality of reaction locations 37 using electrophoresis and/or magnetism. In certain instances, the method may include positioning the one or more microbeads within the one or more reaction locations for biological or chemical analysis.
In particular instances, the electric and/or magnetic fields may be generated by the plurality of electric and/or magnetic field generators 70, e.g., included in the integrated circuit structure, in all or only a subset of the plurality of reaction locations 37 so as to only attract a plurality of microbeads 60 to the subset of reaction locations, such as for selectively filling the plurality of reaction locations 37 with the plurality of microbeads. In such an instance, different types of microbeads may be attracted to different reaction locations, such as by pulsing the voltage and/or magnetic generators and/or keeping the same constant. Particularly, where an electric field generator 70 is provided the voltage applied to the device 1 may be variable or constant and may be less than about 10V, such as about less than 8V, or less than about 6V, including less than about 4V or about 2V or 1V. The voltage may be applied between a location above the fluid 72 and a location on or below the reaction zone 26, such as above the package lid and/or below the metal plate below the package. In certain instances, the location below the reaction location may be a metal or conductive layer such as within the package or package substrate. The method may also include the step of reversing the electric or magnetic field so as to eject the plurality of beads from the plurality of wells, sensors, and/or channels, either entirely or selectively.
Further, as indicated, each or a subset of the plurality of reaction locations may be utilized to generate electric fields to attract a microbead thereby allowing for programmability to each or a subset of reaction locations, for instance, 99% or 95% or 90% or 85%, or 80% or less of the plurality of wells are occupied with a microbead. Hence, the electric and/or magnetic field may be generated in only a subset of the plurality of wells 38a-e, sensors or channels to only attract a plurality of microbeads 60a-e to the subset. Likewise, a plurality of electric and/or magnetic field generators 70a-e for selective filling the plurality of wells 38, sensors or channels with the plurality of microbeads, and/or ejecting the plurality of beads 60 from the plurality of wells 38, sensors or channels. In such an instance, the electric and/or magnetic field generator may be an electric source, a permanent magnet and/or an electromagnet. As indicated, the plurality of magnetic field generators is configured to reverse the magnetic field to eject the plurality of microbeads 60 from the plurality of reaction locations 37 or a subset thereof.
Additionally, in one aspect of the present disclosure, a device, system, and/or method for verifying well occupancy for a plurality of wells 38a-e for analysis of biological or chemical materials may be provided. The system may include a device for receiving a fluid containing the plurality of microbeads 60. Particularly, the device may include a processor, a CMOS structure having an integrated circuit, a plurality of wells 38, and a plurality of sensors within the CMOS structure. Each of plurality of wells 38 may be configured to receive a microbead 60 of the plurality of microbeads, and the CMOS structure may include a mechanism 70 for drawing and/or ejecting the beads into or out of the wells. Hence, the method may include the step of flowing the plurality of microbeads 60 over and/or into the plurality of reaction locations 26/37 and/or wells 38 and/or may include determining, e.g., through electrical and/or magnetic sensing if a reaction location 26/37 and/or well 38 is occupied or unoccupied and/or if a location 26/37 contains one or multiple microbeads 60.
Consequently, the processor 140 may be configured to determine if a well is unoccupied and/or if the well contains one or more, e.g., multiple microbeads. In certain instances, the processor 140 may also be configured to eliminate or modify one or more of the measurements, such as based on the number of wells occupied or unoccupied, e.g., the number of wells containing none, one or multiple microbeads. For instance, the processor 140 may be configured to eliminate from the measurement the number of wells unoccupied and the number of wells containing multiple microbeads, or compensate in the measurement for the number of wells unoccupied and the number of wells containing multiple microbeads, and the like. In such instances, the measurement may be a shift in an I-V or I-Vg curve, as explained below. In particular instances, the processor 140 may be configured to eliminate from the measurement the number of wells unoccupied and the number of wells containing one or multiple microbeads and/or to compensate in the measurement for the number of wells unoccupied and the number of wells containing one or multiple microbeads. Accordingly, in some embodiments, the measurement may be a shift in an I-V or I-Vg curve, such as one or more of: generating a plurality of I-V or I-Vg curves so as to determine a shift in response to a chemical reaction occurring on or near the chemically-sensitive field effect transistor; generating a chemically-sensitive field-effect transistor I-V or I-Vg curve in response to a chemical reaction occurring on or near the chemically-sensitive field-effect transistor so as to detect a change in the slope of the I-V curve; and/or to sense shifts in a capacitance as a function of a gate voltage.
As indicated above, in particular embodiments, the field effect transistor may be configured as a complementary oxide semiconductor that is further adapted so as to be cavitated, so as to include one or more reaction chambers that are positioned so as to align with a gate region of the FET. In such instances, the FET may be in contact with a fluidic source so as to form an ISFET. Accordingly, the CMOS-ISFET may be configured to run one or more chemical and/or biological reactions within its various chambers, such as a DNA sequencing reaction, and the like, such as proximate a solution gated reaction zone. For these purposes, the ISFET may include a processor configured for controlling the performance of the one or more reactions, e.g., involving a biological or chemical material, so as to obtain reaction results, and for analyzing those results, for instance, based on detecting and/or measuring changes in a voltage (V) potential, current (I), or capacitance occurring within the gate region on the chemically-sensitive field effect transistor.
Particularly, as can be seen with respect to
Accordingly, in another aspect of the disclosure, a chemically-sensitive field effect transistor device 1 may be provided, wherein the device may include a structure having a conductive source 22 and drain 24 as well as having a surface or channel 26 extending from the conductive source to the conductive drain, such as where the surface or channel may include a one-, two-, or three-dimensional transistor material 30. The device 1 may also include a computing component 150 having or otherwise being associated with a processor such as where the processor is configured for generating a reference I-Vg curve and/or generating a chemical reaction I-Vg curve, in response to the chemical reaction occurring within a chamber 37 of the chemically-sensitive field effect transistor 1, and may be configured to determine a difference between the reference I-Vg curve and the chemical reaction I-Vg curve. Specifically,
Particularly, as can be seen with respect to
In other instances, as can be seen with respect to
Additionally, in particular instances, the difference between the reference I-Vg curve and the chemical reaction I-Vg curve may be a shift in an Ioff value of the chemical reaction I-Vg curve relative to an Ioff value of the reference I-Vg curve. Particularly,
It is to be noted, with respect to
Accordingly, as can be seen with respect to
For instance,
Hence, in various aspects of the disclosure, one or more elements and/or methods, as herein described, may be used to shift a reference I-V or I-Vg curve and/or a chemical reaction I-Vg curve so that the difference between the reference I-Vg curve and a chemical reaction I-Vg curve is more pronounced. However, in various embodiments, to make such a difference more pronounced, and thus, better able to be detected, the device may include a further structure 40, such as a membrane or other element that is configured for enhancing the ability of the processor to determine the difference between various I-V and/or I-Vg curves. (See, for instance,
Accordingly, as can be seen with respect to
In particular embodiments, therefore, as seen with respect to
Accordingly, in various instances, the chemically-sensitive field effect transistor 1 may be fabricated on an integrated circuit wafer that includes a primary 10 and/or secondary 20 structure as well as a channel structure 26, a processor and/or a tertiary structure 35, such as a structure forming one or more wells 38. For instance, the first and/or secondary structures may include a conductive source 22 and a conductive drain 24, which together with the other components of the FET 1 form a channel region 26. The channel 26 extends from the conductive source 22 to the conductive drain 24, with the channel 26 formed between the two, where a one-dimensional or two-dimensional transistor material layer 30 may be positioned above and/or may otherwise be in contact with the source 22 and drain 24. As indicated above, the FET 1 may include a processor, such as where the processor is configured for generating one or more of a reference I-Vg curve and a chemical reaction I-Vg curve, such as in response to a chemical reaction that is to be detected, for instance, a reaction occurring over or near a reaction zone 26 of the chemically-sensitive field effect transistor 1. In particular embodiments, the processor is configured for determining a difference between the reference I-Vg curve and the chemical reaction I-Vg curve. Hence, in various embodiments, an additional structure 40 may be included, such as a structure that is configured for enhancing the ability of the processor to determine this and other associated differences.
Particularly, in various embodiments, the additional structure may be an ion-selective permeable membrane 40 that allows one or more ions of interest to pass through the membrane 40 while blocking other ions. More particularly, the additional structure 40 may be configured so as to enhance the ability of the processor to determine the difference between the reference I-Vg curve and the chemical reaction I-Vg curve, and thus further enhances the ability of the processor to detect a desired chemical reaction. Accordingly, in various instances, the ion-selective permeable membrane 40 may be positioned within the well 38 and/or over a passivation layer 36, an ion sensitive or reaction layer 34, a 1D and/or a 2D or a 3D transistor material layer 30, and/or a dielectric layer 35 that itself may be positioned over and/or otherwise form a part of the chamber 37 or channel 26. In certain embodiments, the membrane layer 40 may be or otherwise be associated with an ion getter material, such as an ion getter material that traps ions that may or may not be relevant to the biological species and/or chemical reaction to be sensed and/or determined, such as to enhance the ability of the processor to determine the difference between the reference I-V or I-Vg curve and/or the chemical reaction I-V or I-Vg curve. This may be useful because reducing the number and/or amount of interfering ions, enhances the ability of the processor to detect the desired biological species and/or results of the chemical reactions. Particularly, the ion getter material may be arranged within proximity to the chamber 37 and/or surface 21 thereof so that the action of gettering the unwanted ions improves the detection capability of the chemically-sensitive field effect transistor 1. In some instances, one or more of the various layers herein, such as the ion getter material may be placed over or between one or more of the other layers, such as the dielectric layer 20/35, oxide layer 34, or 2D or 1D layers 30, positioned in proximity to one or more of the chambers, channels, or surfaces of the FET device 1.
In particular instances, the ion-selective permeable structure 40 may include a polymer such as perfluorosulphonic material, a perfluorocarboxylic material, PEEK, PBI, Nafion or PTFE. In other instances, the ion-selective permeable structure may be composed of an inorganic material such as an oxide or a glass. In particular instances, the ion-selective permeable structure 40 may be applied to a surface, e.g., 21, of the FET such as by being deposited thereon, such as by a spincoating, anodization, PVD, or other sol gel methods. An additional material, e.g., HMDS, may also be included so as to manage the interaction of the chamber 37 and/or channel 26 and/or associated oxide layer 20/35 and/or an underlying 2D or 1D transistor layer 30. For instance, a chemically-sensitive field effect transistor 1 of the disclosure may include an additional structure that includes a 2D transistor channel or surface which may include an ion-sensitive material over the channel or surface. In such an instance, the material may be sensitive to ions that are different from the ions associated with the biological molecule or chemical reaction that is to be detected. Particularly, the ion-selective permeable structure 40 may additionally be composed of an ion sensitive 1D or 2D transistor material, such as graphene, that is in addition to the 1D or 2D material layer 30, and is not electrically connected to the channel 26.
In certain instances, the ion-selective permeable structure 40 may be positioned over the ion sensitive layer 30 that itself may be positioned over the channel structure or surface 26. As indicated, the additional structure 40 may be composed of an ion getter material, wherein the ion getter material is configured to trap ions that are not relevant to the chemical reaction to be determined. Accordingly, in some instances, a suitably configured membrane 40 and/or additional structure, e.g., HMDS or other siloxane, may be useful because the action of sensing ions that are different from the ions associated with the biologics and/or chemical reactions that are to be detected allows the processor to filter out the signal from the unwanted ions from the signal of the ions of interest. In particular instances, the HMDS material may be positioned under the graphene. Accordingly, in various instances, an exemplary ion-selective permeable membrane 40 and/or an additional getter structure may be positioned over a channel structure 26, where these structures are configured so as to only allow ions of interest to travel through them. In particular instances, the getter material may be positioned within the chamber 37 or elsewhere on the chip or in the package so as to attract unwanted ions. Another alternative would be to include another ion-selective functional layer(s) over some of the sensors which can detect the presence of contaminants or unwanted ions so that their interaction with the sensor and thus the determination of the sensor reaction to the desired ion can be filtered out.
In all of these instances, the action of trapping ions that are not relevant to the chemical reaction to be determined enhances the ability of the processor to determine the difference between the reference I-V g curve and the chemical reaction I-Vg curve, e.g., because there are fewer interfering ions. In such instances, the membrane 40 and/or ion getter material may be arranged within proximity to a reaction zone 26 that is in proximity to a channel region so that the action of gettering the unwanted ions improves the detection capability of the chemically-sensitive field effect transistor. Alternatively, the ion getter material may be placed over a dielectric layer that is in proximity to one or more of the reaction zones 26 and/or channels.
In another aspect, the present gFET integrated circuits, sensors, and/or arrays of the disclosure may be fabricated such as using any suitable complementary metal-oxide semiconductor (CMOS) processing techniques known in the art. In certain instances, such a CMOS processing technique may be configured to increase the measurement sensitivity and/or accuracy of the sensor and/or array, and at the same time facilitate significantly small sensor sizes and dense gFET chamber sensor regions. Particularly, the improved fabrication techniques herein described employing a 1 D, 2D, 3D, and/or oxide as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. In particular embodiments, where an ion-selective permeable membrane is included, the membrane layer may include a polymer, such as a perfluorosulphonic material, a perfluorocarboxylic material, PEEK, PBI, Nafion, and/or PTFE. In some embodiments, the ion-selective permeable membrane may include an inorganic material, such as an oxide or a glass. One or more of the various layers, e.g., the reaction, passivation, and/or permeable membrane layers may be fabricated or otherwise applied by a spin-coating, anodization, PVD, and/or sol gel method.
Accordingly, when using the device for sequencing a nucleic acid sample, the target nucleic acid sample may be coupled to or in proximity with the graphene coated surface of the reaction zone. This template sequence may then be sequenced and/or analyzed by performing one or more of the following steps. For example, a primer, and/or a polymerase, e.g., an RNA and/or DNA polymerase, and/or one or more substrates, e.g. deoxynucleotide triphosphates dATP, dGTP, dCTP, and dTTP, may be added, e.g., sequentially, to the reaction chamber, such as after the hybridization reaction begins so as to induce an elongation reaction. Once the appropriate substrate hybridizes to its complement in the template sequence, there will be a concomitant change in the individual electrical characteristic voltage, e.g., the source-drain voltage (Vsd), measured as a result of the new local gating effect.
Hence, for every elongation reaction with the appropriate, e.g., complementary, substrate there will be a change in the characteristic voltage. For instance, as described herein, a field-effect device for nucleic acid sequencing and/or gene detection is disposed in a sample chamber of a flow cell, and a sample solution, e.g., containing a polymerase and one or more substrates, may be introduced to the sample solution chamber. In various embodiments, a reference electrode may be disposed upstream, downstream or in fluid contact with the field effect device and/or the source and/or drain may themselves serve as electrodes, such as for hybridization detection, and gate voltage may be applied whenever needed.
Particularly, in an exemplary elongation reaction, polynucleotides are synthesized if the added substrate is complementary to the base sequence of the target DNA primer and/or template. If the added substrate is not complementary to the next available base sequence, hybridization does not occur and there is no elongation. Since nucleic acids, such as DNAs and RNAs, have a negative charge in aqueous solutions, hybridization resulting in elongation can be incrementally determined by the change in the charge density in the reaction chamber 30. And because the substrates are added sequentially, it can readily be determined which nucleotide bound to the template thereby facilitating the elongation reaction. Accordingly, as a result of elongation, the negative charge on the graphene gate surface, insulating film surface, and/or the sidewall surface of the reaction chamber will be increased. This increase may then be detected, such as a change in the gate source voltage, as described in detail herein. By determining the addition of which substrate resulted in a signal of change in gate-source voltage, the base sequence identity of the target nucleic acid can be determined and/or analyzed.
More specifically, the field-effect transistor, such as for nucleic acid elongation and/or hybridization detection, may be associated with a buffered solution that is added to the reaction chamber, which can then be used to determine if an elongation reaction has taken place. Particularly, once the template is associated with the substrate, the reaction mixture containing a polymerase, e.g., a Taq polymerase, and a first nucleic acid substrate, e.g., a dATP, is added to the buffer solution to carry out the elongation reaction on the graphene gate coated insulating film of the reaction chamber surface. If the dATP is a complement to the next available reaction site in the isolated template a binding event, e.g., a hybridization reaction, will occur and the antisense strand of the growing sequence will be elongated, and detected by the GFET transistor.
For example, if adenine (A) is complementary to the base thymine (T) on the target template adjacent to the 3′-terminus of the nucleic acid template, an elongation reaction occurs, resulting in synthesis of one adenine. In such instance, the enzyme, Taq DNA polymerase, and the substrate may be washed away from the gate portion and reaction chamber, and a buffer solution, e.g., a phosphoric acid buffer solution, e.g., having a pH of about 6, may be introduced on the graphene gate surface to measure changes in the source-drain voltage. If hybridization has occurred there will be a change in the source-drain voltage and it will be detected. However, if the dATP is not a match, there will be no hybridization, and if no hybridization, there will be no elongation. Consequently, a second reaction mixture containing another, different nucleotide substrate, e.g., dCTP and the enzyme polymerase, and the like will be added to the reaction chamber under conditions suitable for hybridization, which if it occurs will be detected by the GFET. If not, then the steps will be repeated with the next substrate. These steps may be repeated until the nucleic acid sample has been completely sequenced. In various instances, the temperature within the reaction chamber may be controlled, for instance, it may be set to 74° C., such as by using a temperature sensor and/or a heater integrated in the field-effect device.
Consequently, if a hybridization reaction takes place there will be a resultant change to the threshold voltage, which will be increased, e.g., by 4 mV, from before the elongation reaction. The shift of the threshold voltage in the positive direction indicates that a negative charge was generated on the graphene gate surface. It can be understood from this that synthesis of one base caused by the elongation reaction was detectable as a change in threshold voltage. A second elongation reaction may then take place and be repeated until the entire target nucleic acid has been sequenced.
Accordingly,
More particularly, in such a configuration as represented in the figures, the drain current of the transistor may be modulated by the electrical charge carried by the nucleotide molecules involved in the hybridization and/or sequencing reactions. For example, after a binding event, the charge in the reaction zone increases resulting in a change in the output current that may be measured. Such a measurement may be made in accordance with the following equation:
More particularly, in such a configuration as represented in the figures, the drain 26 current of the transistor 20 may be modulated by the electrical charge carried by the nucleotide molecules involved in the hybridization and/or sequencing reactions. For example, after a binding event, the charge in the reaction zone increases resulting in a change in the output current that may be measured. Such a measurement may be made in accordance with the following equation:
Such as where CC represents the current at the control capacitor, and CF represents the current at the parasitic capacitor. VTHF represents the effective threshold voltage of the transistor 20, and VTH0 represents the native threshold voltage. Q0 represents the electric charge initially trapped in the floating gate, and QDNA represents the total charge of hybridization complex.
For instance, a nucleic acid from a sample to be sequenced or representative of a probe to be targeted may be immobilized on the bottom surface or the sidewall of the sample solution well chamber. A Taq DNA polymerase and a nucleotide substrate may then be introduced to the sample solution chamber to induce an elongation reaction. As a result, DNAs may be synthesized along the surface in the vertical or lateral direction, e.g., in parallel to the surface of the graphene coated gate surfaces. In such an instance, as the source-drain current vs gate voltage characteristic changes by the electrostatic interaction with the charged particles (electrons) in the well, and the synthesis of the DNA is in the direction that is transverse or parallel to the graphene gate surface, this keeps the distance between the DNA and the electrons constant, thereby helping to maintain a constant electrostatic interaction. Thus, the base sequence of a template nucleic acid having a large base length can be sequenced and/or analyzed. In other embodiments, a nucleic acid probe may be immobilized on the surface of the reaction zone, as described above, and used in a hybridization reaction so as to detect genetic variation and/or the presence of a genetic disease.
In various instances, in order to conduct parallel analysis of a plurality of nucleic acid templates, the number of the transistors may be equal to or higher than the number and/or types of DNAs to be sequenced and/or analyzed. In certain instances, each nucleic acid template or probe may be an oligonucleotide or a fragment of DNA or RNA that may be constituted from about 100 to about 1000 bases, such as from 200 to about 800 bases, for instance, from about 300 or about 500 bases to about 600 or 700 bases or more or somewhere in between. However, in various instances, a fragment of nucleic acid having 100 bases or fewer may also be used.
Additionally, as indicated above, the present device may also be used in various different DNA/RNA hybridization reactions, such as for the purpose of determining a genetic variation and/or for detecting the presence of a genetic marker for a disease. In such an instance, a nucleic acid probe may be coupled to a bottom or side graphene coated surface of the reaction chamber, per above. As indicated, the probe may be of any suitable length but in various instances from about 5 or 10 to about 1000 bases, such as from 20 or about 50 to about 700 or about 800 bases, for instance, from about 100 or about 200 bases to about 300 bases including about 400 or about 500 bases to about 600 or 700 bases or more or somewhere in between.
For instance, in one exemplary instance, a nucleic acid probe containing about 10 to 15 bases coding for a gene sequence of interest that has been previously amplified, such as by polymerase chain reaction (PCR), may be immobilized on the gate, gate insulating film or side surface of the reaction chamber of the field-effect transistor. For example, once isolated and amplified, the base of the template may be modified so as to be attached to the graphene coated surface, and/or may be coupled to a secondary substrate, such as a glass or plastic bead that has been chemically treated so as to be coupled therewith. Once immobilized, the reaction chamber containing the probes, either on a secondary substrate or directly coupled with a chamber surface, may be reacted with a sample solution containing a number genes including a target gene of interest to be measured such that when a nucleic acid probe having a complementary base sequence to the target gene is immobilized on the gate, gate insulating film or the sidewall surface of the sample solution well structure, or on a secondary substrate immobilized within the reaction chamber of the field-effect device for gene detection, the target gene hybridizes with the nucleic acid probe under appropriate reaction conditions and the target gene and the nucleic acid probe form a double strand, the result of which hybridization reaction may be detected.
As depicted in
Accordingly, as can be seen with respect to
A row decoder may also be provided as part of the system. In such an instance, the row decoder may be configured so as to provide up to sixteen pairs of complementary row select signals, wherein each pair of row select signals may be adapted so as to simultaneously or sequentially enable one sensor in each column so as to provide a set of column output signals from the array, e.g., based on the respective source voltages VSa through VSb, etc. of the enabled row of GFETs. The row decoder may be implemented as a conventional four-to-sixteen decoder (e.g., a four-bit binary input ROW1-ROW4 to select one of 24 outputs). The set of column output signals VSa through VSb for an enabled row of the array is applied to switching logic, which may be configured to include up to sixteen transmission gates Sa through Sb (e.g., one transmission gate for each output signal).
As above, each transmission gate of the switching logic may be implemented using an n-channel or p-channel MOSFET, in a bottom or top gate configuration, or both to ensure a sufficient dynamic range for each of the output signals VSa through VSb. The column decoder, like the row decoder, may be implemented as a conventional four-to-sixteen decoder and may be controlled via the four-bit binary input COL1-COL4 to enable one of the transmission gates Sa through Sb of the switching logic at any given time, so as to provide a single output signal VS from the switching logic. This output signal VS may be applied to a 10-bit analog to digital converter (ADC) to provide a digital representation D1-D10 of the output signal VS corresponding to a given sensor of the array.
As noted earlier, individual GFETs and arrays of GFETs such as those discussed above may be employed as sensing devices in a variety of applications involving chemistry and biology. In particular, such GFETs may be employed as pH sensors in various processes involving nucleic acids such as DNA. In general, the development of rapid and sensitive nucleic acid hybridization and sequencing methods, as herein described, e.g., utilizing automated DNA sequencers, may significantly advance the understanding of biology.
It should be noted, that with respect to the various arrays disclosed herein according to various embodiments of the present disclosure may be fabricated according to conventional CMOS fabrication techniques, as described above, as well as modified CMOS fabrication techniques (e.g., to facilitate realization of various functional aspects of the GFET arrays discussed herein, such as additional deposition of graphene and/or other passivation materials, process steps to mitigate trapped charge, etc.) and other semiconductor fabrication techniques beyond those conventionally employed in typical CMOS fabrication (e.g., BiCMOS). Additionally, various lithography techniques may be employed as part of an array fabrication process. For example, in one exemplary implementation, a lithography technique may be employed in which appropriately designed blocks are “stitched” together by overlapping the edges of a step and repeat lithography exposures on a wafer substrate by approximately 0.2 micrometers. In a single exposure, the maximum die size typically is approximately 21 millimeters by 21 millimeters. By selectively exposing different blocks (sides, top & bottoms, core, etc.) very large chips can be defined on a wafer (up to a maximum, in the extreme, of one chip per wafer, commonly referred to as “wafer scale integration”).
In one embodiment, as can be seen with respect to
Various power supply and bias voltages useful for array operation are provided to the array via electrical connections (e.g., pins, metal pads) and labeled for simplicity in block as “supply and bias connections.” The array may also include a row select shift register, one or more, e.g., two sets of column select shift registers, and one or more, e.g., two, output drivers, which output drivers are configured to provide two parallel output signals from the array, Vouta and Voutb, representing sensor measurements. The various power supply and bias voltages, control signals for the row and column shift registers, and control signals for the column bias/readout circuitry may be provided by an array controller, which controller may also read the output signals Vouta and Voutb (and other optional status/diagnostic signals) from the array. Configuring the array such that multiple regions (e.g., multiple columns) of the array may be read at the same time via multiple parallel array outputs (e.g., Vouta and Voutb) facilitates increased data acquisition rates.
Accordingly, in various instances, an integrated circuit for performing a sequencing reaction is provided, such as where the sequencing reaction involves the sequencing of strands of nucleic acids, as described herein. In various instances, the integrated circuit may include a substrate and an array of graphene field effect transistors arranged on the substrate. In such an instance, one or more of, e.g., each, of the graphene field effect transistors may include a primary layer forming a base layer, and a secondary, e.g., intermediary, layer positioned over or otherwise associated with the primary layer, the secondary layer being formed of a first nonconductive material and including a source and a drain formed in the first nonconductive material, the source and drain being separated one from the other by a channel, and being formed of an electrically conductive material. In certain instances, a tertiary layer may be positioned over the secondary layer, such as where the tertiary layer includes a gate formed over the channel to electrically connect the source and the drain. In such an instance, the gate may be formed of a graphene layer. The tertiary layer may additionally include a surface structure that overlaps the source and the drain in the secondary layer, the surface structure further defining a well having side walls and a bottom that extends over at least a portion of the graphene layer of the gate so as to form a reaction chamber for the performance of the sequencing reaction. In particular embodiments, a chemically-sensitive bead provided in one or more wells of the array of graphene field effect transistors, such as where one or more, e.g., each, chemically-sensitive bead may be configured with one or more reactants to interact with portions of the strands of nucleic acids such that the associated graphene field effect transistor detects a change in ion concentration of the reactants by a change in current flow from the source to the drain via an activation of the graphene layer.
It should be noted that, in various embodiments of the array, one or more of the columns, e.g., the first and last columns, as well as the first and/or last sensors of each of the columns may be configured as “reference” or “dummy” sensors. For instance, the dummy sensors of an array, e.g., the topmost metal layer of each dummy sensor may be tied to the same metal layer of other dummy sensors and may be made accessible as a terminal of the chip, which in turn may be coupled to a reference voltage VREF. Such reference voltage VREF may be applied to the bias/readout circuitry of respective columns of the array. In some exemplary implementations, preliminary test/evaluation data may be acquired from the array based on applying the reference voltage VREF and selecting and reading out dummy sensors, and/or reading out columns based on the direct application of VREF to respective column buffers (e.g., via the CAL signal), to facilitate offset determination (e.g., sensor-to-sensor and column-to-column variances) and array calibration.
The calibration data can be stored for each sensor location either just prior to a sequencing session, or preferentially at the end of the device manufacturing process. The calibration data can be stored on-chip in non-volatile memory.
Additionally, in a further aspect of the present disclosure, a field effect transistor having a chamber and/or channel including a 1D or 2D and/or 3D material may be provided, such as where the 1D or 2D and/or 3D material is present within and/or proximate the chamber and/or channel and configured in such a manner so that the chamber and/or channel geometry may be optimized so as to maximize the ratio of channel width (W) to channel length (L). In various instances, this can be done through the use of interdigitated source and drain electrode geometries, such as in a single plane or, in other embodiments, such optimization may be achieved through the use of one or more 3D electrode structures, such as configured to at least partially or fully circumscribe the chamber or well. For instance, as can be seen with respect to
In various instances, the source 22 and drain electrodes 24, as set forth in
More particularly, as can be seen with respect to
Additionally, as shown in
Further, with respect to
For example, one possibility for forming the source 22 and drain 24 electrodes in the well 38, such as in a 3D structure as set forth herein, is to use a photopatterning or photolithographic process. In such an instance, a mask with the desired pattern(s) may be used to transfer a pattern onto a photosensitive photoresist material. The pattern in the photoresist material can be used to likewise define a pattern in the conductive electrodes (e.g., by etching, lift-off, plating, and/or other processes known in the art). For instance, it is possible by employing the right optics to expose photoresist into deep trenches and/or wells so as to be able to define conductive traces in those deep trenches or wells. An example of this is shown in
Particularly, in various instances, once the source 22 and drain 24 electrodes are formed on the sides 39 of the well 38 the channel 26 may be formed over the electrodes. The process used to form the transistor channel 26 may be by any suitable process, but may depend on the materials being deposited and the presence of process limits imposed by other devices incorporated into the sensor. For instance, a silicon-based CMOS wafer with conventional transistors (e.g., formed from doped regions in the silicon and polysilicon or metal gates) will typically have a processing temperature limit of 350 to 400 degrees C., above which damage to those transistors may occur. So for a CMOS wafer with added sensors, the deposition of the materials making up those sensors will typically be lower than 400 degrees C., which can be accomplished either by a low temperature in-situ deposition processes, and/or by creating the desired sensor materials separately and transferring them to the appropriate locations on the CMOS wafer.
In some instances, a 1D or 2D transistor material 30 can be formed separate from the CMOS wafer and then be transferred onto the electrode structures in the wells 38, as shown in
For instance, in particular embodiments, improved fabrication techniques for producing a CMOS sensor device containing reaction zones employing a 1D or 2D material layer are provided. Specifically, in certain instances, a 1D or 2D material layer may be grown, such as on a growth platform, and once grown may be released from the growth platform, and then be transferred to a semiconductor structure, such a CMOS substrate, so as to be employed as a sensor device as herein described. In particular embodiments, the 1D material may be a carbon nanotube or a semiconductor nanowire, e.g., grown on a substrate, and in other embodiments, the 2D material may be graphene, Molybdenum disulfide (MoS2), Phosphorene (black phosphorous), Silicene, Borophene, Tungsten disulfide (WS2), Boron Nitride, WSe2 Stanene (2D tin), Graphane, Germanane, Nickel HITP, and Mxenes (Ti2C, (Ti0.5, Nb0.5), V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3, Ta4C3).
There are several growth mechanisms that may be implemented for the growth of the 1D or 2D material on a substrate. In certain instances, the growth substrate may be a metal plate, a metal foil, or other thin film metal, such as a metal positioned on or over a wafer, such as a silicon wafer. The 1D or 2D material may be deposited on the growth substrate, such as for growing, by any suitable mechanism, such as by chemical vapor deposition (“CVD”) (atmospheric, low or very low pressure), PECVD, ALD, submergence within a hot wall or cold wall reactor, and the like. Likewise, there are several transfer mechanisms for transferring the growing or grown 1D or 2D structure to a substrate, such as a substrate containing an integrated circuit, such as by direct transfer from the growth substrate to the wafer, e.g., a ROIC (Read-out Integrated Circuit)/CMOS wafer, such as by using Van der Waal's forces, fusion bonding, or other suitable form of temporary bonding. Additionally, there are several release mechanisms for effectuating the release of the 1D or 2D material from the growth substrate and the attachment to the ROIC wafer, including aqueous electrolyte electrolysis, where the growth platform acts as the cathode and separation is produced due to hydrogen evolution. Another release mechanism may include separation caused by use of a temporary adhesive from the growth platform, and/or by use of a laser, a UV light, a temperature increase, or physical peeling or pulling.
Particularly, a direct transfer method is set forth as
More particularly, an effective method for producing such a transfer, e.g., involving a Van Der Waals Bond transfer mechanism, is illustrated in
A further direct transfer method involves fusion bonding, as shown in
Accordingly, in the direct transfer fusion-bonding process, the 2D material may be encapsulated with SiO2 and then the growth wafer may be fusion bonded to the CMOS wafer. Platinum, copper, or another suitable metal may be used as the thin metal for growing the 2D material. A release or separation mechanism (e.g., the bubble process described above) may then be used to separate the 2D material from the metal layer. In such instances, the growth wafer may be composed of any suitable material upon which the 1D or 2D material may be grown, but is typically silicon, sapphire (Al2O3), or other suitable substrate that is capable of sustaining high temperatures and CTE. Alternatively, the present wafer format may be replaced with a panel or sheet, such as a thin metal panel or sheet. Various encapsulating materials may be utilized such as SiO2, Si, Si3N4. The same process may also utilize other materials that can effectuate the releasable bonding such as various polymers.
The glass carrier used may be transparent to UV light, which allows both for curing of the adhesive material and to effectuate release, e.g., by an infrared laser, in the glass release step. As indicated, LTHC is a useful release layer. Particularly, the adhesive material may be filled with Carbon black to absorb IR 1064 laser energy, may be heated to a high temperature, and thereby decomposed. In certain instances, LTHC may be spun on in a thin layer. In particular embodiments, the adhesive material may be an acrylate, such as PMMA. More particularly, the adhesive material may be spun on so as to form an approximately 50 um thick layer. Such adhesive materials are typically available in several different, e.g., four, different tacks, and where desired, other materials may be added to further reduce tackiness. An adhesive material 5032 4% may be employed such as a low tack material.
For bonding, the surface to be bonded may be brought in close proximity to the adhesive material layer (<1 mm) in a vacuum. A top wafer may be dropped onto the adhesive material layer on the glass carrier via gravity. UV or other high intensity light or heat may be applied until fully cured. The adhesive material may be such that it is resistant to solvents, and can be exposed up to 220 C. The 2D material may then be released, such as from a metal backing layer, e.g., composed of copper, silver, gold, or platinum, such as through a bubble bath mechanism or a mechanical peel process, as herein described. This process allows for continuous probing of the material layers to insure the presence and/or uniformity of the 2D material. After the carrier with the 2D material is placed on the target wafer, it may be adhesion baked, such as at 150 C for a short period of time, e.g., two minutes. The mechanism for the release from the glass may be to raster the structure with a UV laser for another short period of time, e.g., two minutes. The tape may be applied by a manual vacuum chuck to hold the wafer, and then a roller tape may be applied, e.g., manually. Alternatively dicing tape may be used. After peeling off the tape and the adhesive layer, anneal cleaning is performed at 400 C.
Accordingly, in one aspect of the present disclosure a method for forming a semiconductor wafer is provided, wherein the wafer is configured as transistor on which a 1D or 2D material layer may be positioned. The method may include providing a wafer, such as a wafer configured as or to otherwise include an integrated circuit, so as to form a semiconductor wafer. The wafer may include a substrate, such as a silicon substrate. An insulating layer may be applied to the substrate, such as via CVD of a silicon dioxide layer. A 1D or 2D material may then be applied, hence, the method may include patterning the 1D or 2D material layer so as to define 1D or 2D material channels or chambers or wells, where such channels may be aligned with interconnect lines on the semiconductor wafer.
In various instances, the method may also include depositing a first dielectric layer over the channels, chambers, or wells. The method may also include opening holes or trenches in the first dielectric layer wherein some of the holes may be aligned to the channels, chambers, or wells, and some of which may be aligned to the interconnect lines. The method may also include depositing conductive material on the 1D or 2D material layer, such as in the holes or trenches so as to create vias that contact the interconnect lines and/or the channels, chambers or wells. Additionally, the method may include depositing and patterning a set of second interconnect lines over the dielectric layer and contacting the vias. In some embodiments, the method may include depositing a second dielectric layer over the first dielectric layer and the second interconnect lines. Particularly, the method may also include patterning and opening holes or trenches in the second dielectric layer to expose portions of the second interconnect lines to be used as pads. The method may also include patterning and opening holes or trenches in the second and first dielectric layers to expose portions of the channels.
Hence, in particular embodiments, a method for forming a semiconductor wafer with transistors on which a 1D or 2D material layer may be deposited is provided. The method may include providing a semiconductor wafer having a substrate and/or insulating layer upon which a 1D and or 2D material layer is deposited. The method may then include patterning the 1D or 2D material layer to define 1D or 2D material channels, chambers, or wells, where the channels, chambers, or wells may be aligned with interconnect lines on the semiconductor wafer. The method may also include depositing an etch stop layer over or within the channels, chambers, or wells. The method may also include depositing a first dielectric layer over the etch stop layer, opening holes or trenches in the first dielectric layer, such as where some of the holes or trenches are aligned to the channels, wells, and/or chambers, and some of which are aligned to the interconnect lines.
The method may also include depositing conductive material in the holes or trenches to create vias that contact the interconnect lines and the channels. In such an instance, the method may include depositing and patterning a set of second interconnect lines over the dielectric layer and contacting the vias. The method also includes depositing a second dielectric layer over the first dielectric layer and the second interconnect lines. The method may include patterning and opening holes or trenches in the second dielectric layer to expose portions of the second interconnect lines to be used as pads. The method may additionally include patterning and opening holes or trenches in the second and first dielectric layers to expose the etch stop layer over the channels. The method also includes opening holes or trenches in the etch stop layer to expose portions of the channels, chambers, or wells.
Particularly, another aspect of the present disclosure is a method for forming a semiconductor wafer with transistors on which is a 2D material layer. The method may include patterning the 2D material layer to define 2D material channels, chambers, or wells, said channels, chambers, or wells being aligned with interconnect lines on the semiconductor wafer. The method also includes depositing an etch stop layer over the channels and/or depositing a first dielectric layer over the etch stop layer. Holes or trenches may be opened in the first dielectric layer and aligned to the channels, chambers, or wells and/or aligned to the interconnect lines. Conductive material may be deposited in the holes or trenches so as to create vias that may be configured to contact the interconnect lines and the channels, chambers, and/or wells. A set of second interconnect lines may be deposited and patterned over the dielectric layer so as to contact the vias. A second dielectric layer may also be deposited over the first dielectric layer and/or the second interconnect lines, and holes or trenches may be patterned to provide openings in the second dielectric layer so as to expose portions of the second interconnect lines, which may be used as pads. In such an instance, the method may also include patterning and opening holes or trenches in the second and first dielectric layers using an anisotropic etching process to expose the etch stop layer over the channels, wells, or chambers. The method may also include opening holes or trenches in the etch stop layer to expose portions of the channels, chambers, or wells.
In certain instances, a method for forming a semiconductor wafer having one or more transistors on which a 1D or 2D material layer may be deposited, as herein described. The method may include patterning the 1D or 2D material layer to define 2D material channels, said channels being aligned with interconnect lines on the semiconductor wafer. The method may also include depositing an etch stop layer over the channels. The method includes depositing a first dielectric layer over the etch stop layer and/or opening holes or trenches in the first dielectric layer, where some of which may be aligned to the channels and some of which may be aligned to the interconnect lines. In various instances, the method also includes depositing conductive material in the holes or trenches to create vias that contact the interconnect lines and the channels. In such an instance, the method may include depositing and patterning a set of second interconnect lines over the dielectric layer and contacting the vias. In certain instances, a second dielectric layer may be deposited over the first dielectric layer and the second interconnect lines. In such an instance, the method may include patterning and opening holes or trenches in the second dielectric layer to expose portions of the second interconnect lines that may be used as pads. The method may include patterning and opening holes or trenches in the second and first dielectric layers, such as by using an anisotropic etching process to expose the etch stop layer over the channels.
Accordingly, in particular instances, the semiconductor structure may include a plurality of 1D or 2D material channels, chambers, or wells composed of a 1D or 2D material, an etch stop layer, a plurality interconnect lines on a semiconductor wafer, a first dielectric layer comprising a plurality of holes or trenches, a conductive material, a second plurality of interconnect lines, and a second dielectric layer having a plurality of holes or trenches. And in some instances, the semiconductor structure comprises a plurality of 1D or 2D material channels, chambers, or wells composed of a 1D or 2D material, a plurality interconnect lines on a semiconductor wafer, a first dielectric layer comprising a plurality of holes or trenches, a conductive material, a second plurality of interconnect lines, and a second dielectric layer having a plurality of holes or trenches.
In view of the above, in various embodiments,
In the direct transfer fusion bonding process, the 2D material, e.g., graphene, may be encapsulated with SiO2 and then the growth wafer may be fusion bonded to a CMOS wafer. Platinum, gold, silver, copper or another suitable metal may be used for growing the 2D material. A release or separation mechanism (e.g., bubble process) is used to separate the 2D material from the platinum or other metal. The growth wafer may be a silicon, sapphire (Al2O3), or other suitable substrate capable of sustaining high temperatures and CTE. Alternatively, a wafer format may be replaced with a panel or sheet. Various encapsulating materials may be utilized such as SiO2, Si, Si3N4. The same process may also utilized with other materials that can be bonded such as polymers. Alternative methods for growing and transferring 2D materials are disclosed in Hoffman et al., U.S. Provisional Patent Application No. 62/175,351, filed on Jun. 14, 2015, for System And Method For Growing And Transferring Graphene For Use As A FET, which is hereby incorporated by reference in its entirety.
To demonstrate the desirability of forming 3 dimensional electrode structures on the well surfaces 39 and/or 21, a comparison of the ratio of channel width to channel length (W/L) can be made of a device that only has electrodes 22, 24 on the well bottom 21 versus one with electrodes on the well bottom 21 and well walls 39. For instance, with respect to the well structure depicted in
For example, for 6 gaps, where the well diameter is 1000 nm, the channel width due to the sidewall structures is: Wvertical=2πrN=6.3×500 nm×number of levels=3150 nm×6=18900 nm. Further, if the channel width at the well bottom is added, a total channel width is 19845 nm and a W/L of 198. This is more than a 20 times higher W/L than the case with an electrode structure only on the well bottom. As described above, the electrode structures 22, 24 on the well sidewalls 39 and at the well bottom 21 may be covered by a transistor material, such as depicted in
In various instances, the source 22 and drain 24 electrodes can form electrode pairs that are separated one from the other by a distance such as to from an interdigitated source 22 and drain 24 electrode pair. As presented in
The next step, shown in
These process steps may be repeated in
Additionally,
Accordingly, in various aspects of the disclosure, a chemically-sensitive field effect transistor (FET) having a multi-layered structure is provided. For instance, the chemically-sensitive FET may include a first layer such as a substrate layer. The substrate layer, like all layers disclosed herein, may have an extended body including a proximal portion having a proximal end, a distal portion having a distal end, and a pair of opposed side portions, all of which together define a circumference for the substrate layer. Additionally, a second layer, e.g., a first non-conductive material layer, may be included wherein the first non-conductive material layer may be an insulating layer and be positioned above the extended body of the substrate layer. In various embodiments, a second non-conductive material layer, which may also be an insulating layer, may also be included and positioned above the first non-conductive material layer.
In various embodiments, one or more conductive elements (e.g., composed of an electrically conductive material), such as one or more electrodes, such as a source electrode and a drain electrode for a transistor, may be provided. In various instances, the conductive elements may be separated one from the other and positioned within one or more of the non conductive layers so as to from a channel between the electrodes. In particular embodiments, the source and drain electrodes may have a planar arrangement and may be in an opposed configuration to one another, where one or both of the source and drain electrodes have a geometrical formation or pattern designed to maximize the ratio of the channel width to channel length. For instance, the source and drain electrodes may be configured, e.g., within the insulating layer such that the channel length is less than about 1000 nm, less than about 500 nm, less than about 100 nm, may be less than about 50 nm, or may be less than about 10 nm, less than about 5 or 3 nm or less.
Further, in various embodiments, the chemically-sensitive field effect transistor (FET) may include a well structure, provided at least within the first and/or second non-conductive material layers. In such an instance, the well structure may include a chamber, such as a chamber that may be bounded by one or more bounding members. For instance, the bounding member may be configured as a plurality of walls or a circular circumferential surface member. In particular embodiments, the bounding member(s) and/or the surrounding insulating layer(s) may be configured to include the source and drain electrodes. For example, one or more, e.g., both of the source and drain electrodes may be configured so as to be included within a bottom and/or a side surface on the well bounding member. In such an instance, the source and drain electrodes may be configured so as to increase the channel width to length ratio. Particularly, the source and drain electrodes may have a three-dimensional (3D) configuration and may be incorporated on or within the bottom surface member of the chamber and/or be incorporated within one or more side or circumferential surface members of the chamber. In such instances, the source and drain electrodes may be configured so as to increase the channel width to length ratio by a factor of about 10 or 20 or more, e.g., compared to an electrode pattern only at the bottom of the well, such as by a factor of 100 or more, such as a geometric electrode pattern that increases the channel width to length ratio by a factor of 1000 or more.
Particularly, in certain embodiments, the source and drain electrodes may be separated one from the other by one or more spaces, and thus, may be configured to not only have a 3D structure but to also be in an opposed but interdigitated relationship to one another. For instance, one or more of the source and drain electrodes may be formed so as to include an impingement member, and one or more of the source and drain electrodes may be formed so as to include a receiving member, such as where the impingement member is configured for being inserted within the receiving member, and the receiving member is configured for receiving the impingement member, while maintaining a distance between one another, such as to form one or more channels there between.
Hence, in various instances, the source and drain electrodes may have one or more, e.g., a plurality of, prongs or tines so as to give the electrode a fork like configuration, such as can be seen with respect to
Thus, in various embodiments, the chemically sensitive FET may be configured to include a channel, such as a channel that includes or is otherwise composed of a transistor channel material, such as is formed over and/or between the electrodes, e.g., the source and drain electrodes. For instance, a 1 D, 2D, e.g., a graphene layer, and/or 3D structured layer, may be positioned between the first and second non-conductive material layers. For example, the transistor material channel material may be a 1D material may be comprised of carbon nanotubes or semiconducting material such as in a nanowire form, such as including Si, Ge or a metal oxide. In other instances, the 2D material may be composed of one or more of graphene, Molybdenum disulfide (MoS2), MoSe2, Phosphorene (black phosphorous), Silicene, Borophene, Tungsten disulfide (WS2), Boron Nitride, WSe2, Stanene (2D tin), Graphane, Germanane, Nickel HITP, Mxenes (Ti2C, (Ti0.5, Nb0.5), V2C, Nb2C, Ti3C2, Ti3CN, Nb4C3, Ta4C3), and/or transition metal dichalcogenides. The transistor material may be a bulk transistor material such as Si, amorphous Si, Ge, and/or metal oxide. In particular instances, the channel transistor material may be configured so as to extend between a surface portion of the source electrode and a surface portion of the drain electrode. In such an instance, positioning of the transistor channel material between the source and drain electrodes is designed to form the channel and thereby control and/or regulate conductivity between the electrodes. Hence, the FET may include a gate structure.
In certain instances, as herein disclosed, the FET may be configured for performing a chemical reaction, such as for the detection of one or more analytes, such as a reactant from a chemical reaction. Accordingly, in various instances, the FET may include an analyte-sensitive layer. In various embodiments, e.g., to facilitate the performance of a chemical reaction, the field effect transistor may include a well structure, within which a chemical reaction may take place. For instance, one or more of the layers of the FET, such as the first and/or second insulating layers may include a chamber, such as a chamber to which the reactants may be added for the performance of the chemical reaction. In such an instance, the gate structure of the FET may be formed within the chamber and over the channel so as to electrically connect the source and the drain electrodes. Further, one or more solutions, such as containing one or more reactants may be added to the chamber thereby forming a solution gate. In various instances, the gate structure may include the graphene layer.
Further, in various embodiments, the chemically-sensitive field effect transistor and/or the chamber thereof may be configured such that the electrodes, e.g., the source and drain electrodes, are positioned on or in the bounding member of the chamber. For instance, in various instances, the surfaces or walls of the chamber may include one or more trenches, wherein the trench includes one or more of the electrode structures, and/or may include the 1D or 2D structure, such as the graphene layer. Hence, the electrodes of the source and drain may be included in a bottom or side or circumferential surface of the well or trench. In such an instance, an analyte-sensitive layer may be formed on the well or trench bottom and/or sidewalls and/or may cover the electrodes and/or channel material. In some instances, the 1D channel material may be a vertically-oriented 1D channel material. Consequently, the chamber may be configured for sensing and/or measuring the analyte such as a reactant that results from the reaction taking place within the chamber.
For example, one or more surfaces of the substrate and/or a well and/or a chamber thereof may be fabricated in such a manner so as incorporate the electrodes therein. Particularly, one or more of the electrodes disclosed herein may be formed by any suitable method, such as by being lithographically photopatterned, which may utilize a light source and/or optics that allow patterning of deep trenches and/or wells. More particularly, in various instances, an electron beam, laser or plasma beam may be utilized to pattern the wells and/or trenches and/or the electrodes. In various instances, the well structure is comprised of alternating vertical layers of source and drain electrodes, such as to define the channel width and the channel length. In particular embodiments, the well structure is comprised of electrodes on a well bottom and/or in conjunction with alternating vertical layers of source and drain electrodes so as to define a channel width and/or channel length. As stated above, the electrodes may have a transistor channel material and/or an analyte-sensitive material over and/or between them, such as in the alternating vertical layer configuration. In various embodiments, the analyte-sensitive material may be formed by PVD deposition of a metal and oxidization of that metal and/or the analyte-sensitive material may be formed by ALD deposition of a metal oxide, such where the PVD deposition is a sputter or e-beam deposition, and/or the oxidation is a thermal or plasma oxidation. In particular instances, the analyte-sensitive material may be comprised of multiple layers, which material may be formed by any process or a combination of processes so as to cover a bottom and/or side of the well, and in certain instances, the analyte-sensitive material at the bottom of the well may be different from the analyte-sensitive layer coating the well or trench walls.
Accordingly, in a further aspect of the disclosure, a method for producing a field effect transistor is provided, such as a FET that is configured for performing a chemical reaction and sensing one or more of the products thereof. In such instances, the FET may include a plurality of electrodes, and in various instances may be in an alternating, vertical and/or interdigitated layered configuration. In such an instance, the method may include forming alternating layers of source electrodes, dielectric material and drain electrodes, as well as forming a well or trench within a central portion of the source and drain electrode patterns. The method may include forming a well or trench in one or more of the layers of the FET, such as one or more of the insulating layers, such as in an etching process, such as by wet etching or plasma etching, or the like.
Hence, in various instances, the method for producing a sensor may include forming alternating and/or interdigitated layers of source electrodes, dielectric material, and/or drain electrodes, forming a well or trench within a central portion of the source and drain electrode patterns, and/or forming a transistor channel material over or between the source and drain electrodes, such as where an analyte-sensitive layer may be formed over the transistor channel layer. For instance, a first layer of transistor channel material may be formed over a first electrode layer, a dielectric layer may be formed over the first electrode layer, a trench may be patterned in the dielectric layer, a second electrode layer may then be formed within the trench. In various embodiments, the second electrode layer and dielectric layer may be planarized, a second layer of transistor channel material may then be formed over the second electrode and second dielectric layer and this process may then be repeated so as to produce the desired number of electrode and channel layers.
A useful detailed description is set forth in van Rooyen et al., U.S. Patent Publication Number 20140371110 for Bioinformatics Systems, Apparatuses, and Methods Executed On An Integrated Circuit Processing Platform, which is “hereby incorporated by reference in its entirety.
A useful detailed description is set forth in van Rooyen et al., U.S. Patent Publication Number 20140309944 for Bioinformatics Systems, Apparatuses, and Methods Executed On An Integrated Circuit Processing Platform, which is hereby incorporated by reference in its entirety.
A useful detailed description is set forth in van Rooyen et al., U.S. Patent Publication Number 20140236490 for Bioinformatics Systems, Apparatuses, and Methods Executed On An Integrated Circuit Processing Platform, which is hereby incorporated by reference in its entirety.
A useful detailed description is set forth in van Rooyen et al., U.S. Patent Publication Number 20140200166 for Bioinformatics Systems, Apparatuses, and Methods Executed On An Integrated Circuit Processing Platform, which is hereby incorporated by reference in its entirety.
A useful detailed description is set forth in McMillen et al., U.S. Provisional Patent Application No. 62/127,232, filed on Mar. 2, 2015, for Bioinformatics Systems, Apparatuses, And Methods Executed On An Integrated Circuit Processing Platform, which is hereby incorporated by reference in its entirety.
A useful detailed description is set forth in van Rooyen et al., U.S. Provisional Patent Application No. 62/119,059, filed on Feb. 20, 2015, for Bioinformatics Systems, Apparatuses, And Methods Executed On An Integrated Circuit Processing Platform, which is hereby incorporated by reference in its entirety.
A useful detailed description is set forth in van Rooyen et al., U.S. Provisional Patent Application No. 61/988,128, filed on May 2, 2014, for Bioinformatics Systems, Apparatuses, And Methods Executed On An Integrated Circuit Processing Platform, which is hereby incorporated by reference in its entirety.
A useful detailed description of a GFET is set forth in van Rooyen, U.S. Provisional Patent Application No. 62/094,016, filed on Dec. 18, 2014, for Graphene FET Devices, Systems, And Methods Of Using The Same For Sequencing Nucleic Acids, which is hereby incorporated by reference in its entirety.
A useful detailed description of a GFET is set forth in Hoffman et al., U.S. Provisional Patent Application No. 62/130,594, filed on Mar. 9, 2015, for Chemically Sensitive Field Effect Transistor, which is hereby incorporated by reference in its entirety.
A useful detailed description of a GFET is set forth in Hoffman et al., U.S. Provisional Patent Application No. 62/130,598, filed on Mar. 9, 2015, for Method And System For Analysis Of Biological And Chemical Materials, which is hereby incorporated by reference in its entirety.
A useful method for growing and transferring graphene is disclosed in Hoffman et al., U.S. Provisional Patent Application No. 62/175,351, filed on Jun. 14, 2015, for a System And Method For Growing And Transferring Graphene For Use As A FET, which is hereby incorporated by reference in its entirety.
A use for two dimensional materials is disclosed in Hoffman et al., U.S. Provisional Patent Application No. 62/175,384, filed on Jun. 14, 2015, for a CMOS Integration Of A Two-Dimensional Material, which is hereby incorporated by reference in its entirety.
The following U.S. patent applications discuss the processing component of the a system for analysis of biological and chemical materials: U.S. patent application Ser. No. 14/279,063, titled, Bioinformatics Systems, Apparatuses, and Methods Executed on an Integrated Circuit Processing Platform, filed May 15, 2014; U.S. patent application Ser. No. 14/180,248, titled Bioinformatics Systems, Apparatuses, and Methods Executed on an Integrated Circuit Processing Platform, filed Feb. 13, 2014; U.S. patent application Ser. No. 14/179,513, titled Bioinformatics Systems, Apparatuses, and Methods Executed on an Integrated Circuit Processing Platform, filed Feb. 12, 2014; U.S. patent application Ser. No. 14/158,758, titled Bioinformatics Systems, Apparatuses, and Methods Executed on an Integrated Circuit Processing Platform, filed Jan. 17, 2014; U.S. patent application Ser. No. 14/279,063; U.S. Provisional Application No. 61/826,381, titled System and Method for Computation Geneomic Pipeline, filed May 22, 2013; U.S. Provisional Application No. 61/943,870, titled Dynamic Genome Reference Generation For Improved NGS Accuracy And Reproducibility, filed Feb. 24, 2014; all of which are hereby incorporated by reference in their entireties herein.
From the foregoing it is believed that those skilled in the pertinent art will recognize the meritorious advancement of this invention and will readily understand that while the present invention has been described in association with a preferred embodiment thereof, and other embodiments illustrated in the accompanying drawings, numerous changes modification and substitutions of equivalents may be made therein without departing from the spirit and scope of this invention which is intended to be unlimited by the foregoing except as may appear in the following appended claim. Therefore, the embodiments of the invention in which an exclusive property or privilege is claimed are defined in the following appended claims.
This application claims the benefit of priority to U.S. Provisional Application Ser. No. 62/175,351, filed on Jun. 14, 2015; U.S. Provisional Application Ser. No. 62/175,384 filed on Jun. 14, 2015; U.S. Provisional Application Ser. No. 62/175,649 filed Jun. 15, 2015 and is a Continuation in part of U.S. application Ser. No. 15/065,744, filed on Mar. 9, 2016 which claims the benefit of priority to U.S. Provisional Application Ser. No. 62/130,598, filed on Mar. 9, 2015; U.S. Provisional Application Ser. No. 62/130,594, filed on Mar. 9, 2015; U.S. Provisional Application Ser. No. 62/130,601, filed on Mar. 9, 2015; U.S. Provisional Application Ser. No. 62/130,621, filed on Mar. 10, 2015; and a continuation in part of U.S. application Ser. No. 14/963,253, filed on Dec. 9, 2015, which in turn claims benefit of U.S. Provisional Application Ser. No. 62/094,016, filed on Dec. 18, 2014.
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