Patent Application
20250056858
The present disclosure generally relates, amongst others, to a semiconductor structure and to a method of growing thereof. More particularly, it relates to a semiconductor structure comprising Group III-nitride grown onto Silicon-On-Insulator, wherein the semiconductor structure achieves outstanding performance for high-power and high-frequency applications, and to a method of growing thereof.
Group III-nitride-based heterostructures are very suited for high-power and high-frequency applications due to their high electron velocity and high critical electric field. For example, AlGaN/GaN heterostructures are conventionally used for the manufacturing of field effect transistors also called FETs. In this heterostructure, a two dimensional electron gas, also referred to as 2DEG, is generated by the spontaneous and piezoelectric polarization between the two active layers, i.e., between AlGaN and GaN.
Group III-nitride-based heterostructures are typically manufactured on top of conventional silicon substrates. With the ever increasing need for high-power and high-frequency solutions, the telecommunication industry is faced with the challenge of making such Group III-nitride-based heterostructures compatible with existing technologies. For example, Group III-nitride-based heterostructures should allow the continued miniaturization of microelectronic devices and the continued improvement of their performance.
For high-power and high-frequency applications, it is essential to maximize the resistivity of the underlying substrate of the devices. However, measurements performed with spreading resistance profiling on gallium-nitride epitaxially grown onto a silicon substrate demonstrate a significant drop in resistivity versus depth in the heterostructure.
More generally, measurements performed with spreading resistance profiling on Group III-nitride heterostructures epitaxially grown on a silicon substrate demonstrate a similar drop in resistivity at the interface between the Group III-nitride heterostructure and the silicon substrate and similar presence of p-type dopants at the interface between the Group III-nitride heterostructure and the silicon substrate. Such presence of p-type dopants at the interface between Group III-nitride heterostructure and silicon is attributed to the diffusion or migration of impurities from the initial growth layer of the epitaxial layers of the Group III-nitride heterostructure to the silicon substrate. The impurities act as a p-type impurity for the silicon substrate. More particularly, such presence of p-type dopants at the interface between Group III-nitride heterostructure and silicon is attributed to the diffusion or migration of Group III elements into the silicon substrate in which they act as p-type impurities for the silicon substrate. For example, in the sample investigated in
Several problems arise from such diffusion of Group III elements into the silicon substrate. For high-power and high-frequency applications, the presence of a high concentration of p-type dopants at the interface between gallium nitride and silicon will cause a capacitive coupling resulting in significant power dissipation and RF losses for components manufactured from this structure. Additionally, the diffusion of Group III elements into the silicon substrate will cause linearity problems to arise due to the generation of harmonic frequencies in components manufactured from this structure.
It is thus an object of embodiments of the present disclosure to propose a semiconductor structure and a manufacturing method that do not show the inherent shortcomings of the prior art. More specifically, it is an object of embodiments of the present disclosure to propose a semiconductor structure with improved performance at high-power and high-frequency and a manufacturing method thereof.
There is a need for a semiconductor structure that demonstrates improved resistivity, and reduced power losses and linearity problems. Additionally, there is a need for a semiconductor structure that, from a manufacturing perspective, is compatible with existing technologies.
This object is achieved, according to a first example aspect of the present disclosure, by a semiconductor structure comprising:
As previously mentioned, presence of p-type dopants at the interface between the Group III-nitride heterostructure and a silicon substrate onto which the Group III-nitride heterostructure is, for example, epitaxially grown can be measured with, for example, spreading resistance profiling measurements. Such presence of p-type dopants at the interface between Group III-nitride heterostructure and silicon is attributed to the diffusion or migration of impurities from the initial growth layer of the epitaxial layers of the Group III-nitride heterostructure to the silicon substrate. The impurities act as a p-type impurity for the silicon substrate. More particularly, such presence of p-type dopants at the interface between Group III-nitride heterostructure and silicon is attributed to the diffusion or migration of Group III elements into the silicon substrate in which they act as p-type impurities for the silicon substrate.
With the semiconductor structure according to the present disclosure, the diffusion or migration of Group III elements from the epitaxial layers of the Group III-nitride heterostructure into the Silicon-On-Insulator substrate is contained in a surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure, for example, in the top layer and optionally close to the interface between the intermediate layer and the top layer. Indeed, the intermediate layer of the Silicon-On-Insulator substrate according to the present disclosure confines the diffusion or migration of Group III elements within the surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure, for example, in the top layer and optionally close to the interface between the intermediate layer and the top layer, thereby shortening the diffusion distance of the impurities into the Silicon-On-Insulator substrate.
With the semiconductor structure according to the present disclosure, the n-type doping of the top layer of the Silicon-On-Insulator substrate compensates for the concentration of Group III elements that diffuses from the epitaxial layers into the Silicon-On-Insulator substrate. In other words, the n-type doping of the top layer of the Silicon-On-Insulator substrate according to the present disclosure balances out a concentration of p-type dopants at the interface between the epitaxial layers and the Silicon-On-Insulator substrate, wherein the concentration of these p-type dopants results from a diffusion of Group III atoms from the epitaxial III-N semiconductor layer stack into the top layer of the Silicon-On-Insulator substrate.
This way, the semiconductor structure according to the present disclosure demonstrates improved performance at high-power and high-frequency, improved resistivity, and reduced power losses and linearity problems.
The use of a trap-rich layer has been proven as one of the most effective techniques to reduce these parasitic effects and to enhance the high-resistivity properties of silicon, while being compatible with industrial SOI wafer fabrication and with the important thermal budget of standard CMOS process. The traps of the trap-rich layer capture the free carriers at the interface between the silicon and the intermediate layer, thereby enabling the Silicon-On-Insulator substrate to recover its nominal resistivity, linearity, eliminating the DC dependency and leading to a substantial reduction of RF losses and crosstalk. In the context of the present disclosure, the trap-rich layer has a defect density suitable for trapping free charges that may be generated in the Silicon-On-Insulator substrate. The trap-rich layer may provide a trapping effect as well. The trap-rich layer has a thickness of several tens of nanometers to several microns, for example, 50 nm to 3 microns. The trap-rich layer comprises silicon, or amorphous silicon carbide, or polycrystalline silicon also referred to as polysilicon.
In the context of the present disclosure, a two-dimensional electron gas, also referred to as 2DEG, is a gas of electrons free to move in two dimensions, but tightly confined in the first. This tight confinement leads to quantized energy levels for motion in that direction. The electrons appear to be a 2D sheet embedded in a 3D world.
In the context of the present disclosure, Group III-nitride refers to semiconductor compounds formed between elements in Group III of the periodic table, for example, Boron, also referred to as B, Aluminum, also referred to as Al, Gallium, also referred to as Ga, Indium, also referred to as In, and Nitrogen, also referred to as N. Example of binary Group III-nitride compounds are GaN, AIN, BN, etc. Group III-nitride also refers to ternary and quaternary compounds such as, for example, AlGaN and InAlGaN.
In the context of the present disclosure, the first active III-N layer comprises one or more of N, P, As, and one or more of B, Al, Ga, In and Tl. The first active III-N layer, for example, comprises GaN. The second active III-N layer comprises one or more of N, P, As, and one or more of B, Al, Ga, In, and Tl. The second active III-N layer, for example, comprises AlGaN. The term AlGaN relates to a composition comprising Al, Ga and N in any stoichiometric ratio (AlxGayN) wherein x is between 0 and 1 and y is between 0 and 1. Alternatively, the second active III-N layer, for example, comprises AIN. Alternatively, the second active III-N layer comprises InAlGaN. A composition such as InAlGaN comprises In in any suitable amount. Alternatively, both first active III-N layer and second active III-N layer comprise InAlGaN, and the second active III-N layer comprises a bandgap larger than a bandgap of the first active III-N layer and wherein the second active III-N layer comprises a polarization larger than the polarization of the first active III-N layer. Alternatively, both first active III-N layer and second active III-N layer comprise BInAlGaN, and the second active III-N layer comprises a bandgap larger than a bandgap of the first active III-N layer and wherein the second active III-N layer comprises a polarization larger than the polarization of the first active III-N layer. Compositions of the active layer may be chosen in view of characteristics to be obtained, and compositions may vary accordingly. For example, good results were obtained with a first active III-N layer comprising GaN of about 150 nm thickness and a second active III-N layer comprising AlGaN of about 20 nm thickness.
In the context of the present disclosure, the base layer of the Silicon-On-Insulator substrate comprises bulk silicon and a resistivity of the base layer of the Silicon-On-Insulator substrate is typically between 3 and 5 kOhm·cm, and is preferably higher than 1 kOhm·cm. This way, the resistivity of the substrate underlying the epitaxial III-N semiconductor layer stack is maximized for high-power and high-frequency applications.
In the context of the present disclosure, the technology of Silicon-On-Insulator, also referred to as SOI, corresponds to the manufacturing of semiconductor devices in a layered silicon-insulator-silicon substrate. The choice of insulator depends largely on the intended application of the semiconductor devices. Several types of Silicon-On-Insulator substrates may be used within the context of the present disclosure.
Due to the isolation from the bulk silicon of the base layer of the Silicon-On-Insulator substrate, parasitic capacitance within the semiconductor devices manufactured from the Group III-nitride heterostructure is lowered, thereby improving their power consumption and their performance. The semiconductor devices manufactured on Silicon-On-Insulator also demonstrate a higher resistance to latchup and a higher performance at equivalent VDD than semiconductor devices integrated on other types of substrates. The temperature dependency of the semiconductor devices manufactured on SOI is reduced compared to semiconductor devices integrated on other types of substrates. Due to the isolation, the semiconductor devices manufactured on SOI demonstrate lower leakage currents and consequently higher power efficiency.
Radio-Frequency Silicon-On-Insulator substrates, also referred to as RF-SOI substrates, enable high RF performance on silicon films compatible with standard CMOS processes, high linearity RF isolation and power signals, low RF loss, digital processing and power management integration.
For example, an enhanced signal integrity substrate for RF application comprises a base layer comprising high-resistive silicon, a trap rich layer formed on top of the base layer, a buried insulator formed on top of the trap rich layer, and a top layer formed on top of the buried insulator, wherein the top layer comprises a monocrystal. A resistivity of the base layer is typically over 3 kOhm·cm. A thickness of the top layer is typically between 50 nm and 200 nm. The addition of a trap-rich layer provides outstanding RF performances. Such substrate is particularly suited for devices with stringent linearity specifications. Applications typically target, for example, LTE-Advanced and 5G specifications and address different performance requirements. Compared to a high-resistive SOI substrate, an enhanced signal integrity substrate demonstrates better linearity, lower RF losses, lower crosstalk, improved quality factors for passives, smaller die sizes and higher thermal conductivity. Enhanced signal integrity substrates further typically demonstrate a harmonic quality factor lower than −80 dBm.
Another example of a RF-SOI comprises a base layer comprising mid-resistive silicon, a trap-rich layer formed on top of the base layer, a buried insulator formed on top of the trap-rich layer, and a top layer comprising a thin monocrystal. Such substrate is particularly suited for, for example, cost sensitive highly integrated devices, and is particularly well suited to, for example, WI-FI®, IoT and other consumer applications specifications.
Another example of a RF-SOI called high-resistive SOI targets, for example, devices with lower linearity specifications and 2G and 3G specifications. Such substrate comprises a base layer comprising high-resistive silicon, a buried insulator formed on top of the base layer and a top layer comprising a thin monocrystal.
Power Silicon-On-Insulator substrates address the requirements for integrating, for example, high-voltage and analog functions in intelligent, energy-efficient and highly reliable power IC devices, for automotive and industry markets. They provide excellent electrical isolation and are perfect for integrating devices operating at different voltages from a few volts to several hundred volts while reducing die area and improving reliability. These substrates are ideal for applications such as CAN/LIN transceivers, switch mode power supplies, brushless motor drivers, LED drivers, and more. A power SOI comprises a base layer comprising silicon, a buried insulator formed on top comprising oxide, and a top layer comprising silicon. A thickness of the buried insulator is typically between 0.4 μm to 1 μm and a thickness of the top layer is typically between 0.1 μm and 1.5 μm.
Photonics Silicon-On-Insulator substrates address the requirement of optical function integration onto, for example, a CMOS chip for low-cost and high-speed optical transceivers. Such a substrates comprises a base layer comprising silicon, a buried insulator formed on top of the base layer and comprising oxide, and a top layer formed on top of the buried insulator and comprising monocrystalline silicon. A thickness of the buried insulator is typically between 0.7 μm to 2 μm and a thickness of the top layer is comprised typically between 0.1 μm and 0.5 μm. The crystalline silicon layer on insulator can be used to fabricate, for example, optical waveguides and other optical devices, either passive or active, e.g., through suitable implantations. The buried insulator enables, for example, the propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air, e.g., for sensing applications, or covered with a cladding, for example, made of silica.
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried insulator and concerns about differential stress in the top layer comprising silicon.
According to example embodiments, an n-type doping concentration of the top layer is within the range of 1.1015 cm−3 to 5.1015 cm−3.
This way, the n-type doping of the top layer of the Silicon-On-Insulator substrate compensates and balances out for the concentration of Group III elements that diffuses from the epitaxial layers into the top layer of the Silicon-On-Insulator substrate.
According to example embodiments, a thickness of the top layer is between 50 and 200 nm. Alternatively, a thickness of the top layer is lower than 100 nm.
This way, the intermediate layer confines the diffusion or migration of Group III elements within the thin silicon layer formed by the top layer. In other words, the intermediate layer confines the diffusion or migration of Group III elements to the surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure. The semiconductor structure then demonstrates improved performance at high-power and high-frequency, improved resistivity, and reduced power losses and linearity problems.
According to example embodiments, the top layer comprises n-type doped silicon, wherein an orientation of the n-type doped silicon of the top layer is (111).
According to example embodiments, the top layer comprises monocrystalline silicon.
This way, the monocrystalline silicon of the top layer can be used to fabricate, for example, optical waveguides and other optical devices, either passive or active, e.g., through suitable implantations. The buried insulator enables, for example, the propagation of infrared light in the silicon of the top layer on the basis of total internal reflection. The top surface of the waveguides manufactured within the top layer can be either left uncovered and exposed to air, e.g., for sensing applications, or covered with a cladding, for example, made of silica.
According to example embodiments, the buried insulator comprises amorphous silicon carbide and the trap-rich layer comprises amorphous silicon carbide.
This way, amorphous silicon carbide acts as a trap-rich and as a barrier containing the diffusion or migration of Group III elements from the epitaxial layers of the Group III-nitride heterostructure into the Silicon-On-Insulator substrate in a surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure, for example, in the top layer and optionally close to the interface between the intermediate layer and the top layer. Alternatively, the trap-rich layer comprises silicon or polysilicon.
According to example embodiments, the buried insulator comprises silicon dioxide and the trap-rich layer comprises silicon.
According to example embodiments, the buried insulator comprises silicon dioxide and the trap-rich layer comprises amorphous silicon carbide.
Alternatively, the trap-rich layer comprises polysilicon.
According to example embodiments, the buried insulator comprises a layer comprising silicon nitride confined between two layers comprising silicon oxide; and the trap-rich layer comprises amorphous silicon carbide.
In this example embodiment, the buried insulator comprises an ONO dielectric stack, wherein ONO stands for oxide-nitride-oxide. The buried insulator results in better thermal conduction than silicon dioxide without excessively deteriorating parasitic capacitive coupling nor jeopardizing high-speed performance of, for example, active devices manufactured from the semiconductor structure according to the present disclosure. Additionally, the buried insulator comprising a layer comprising silicon nitride further enhances the technical effect of containing the diffusion or migration of Group III elements from the epitaxial layers of the Group III-nitride heterostructure into the Silicon-On-Insulator substrate in a surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure, for example, in the top layer and optionally close to the interface between the intermediate layer and the top layer. Blocking the diffusion of Group III elements from the epitaxial layers of the Group III-nitride heterostructure into the Silicon-On-Insulator substrate is more efficient in a semiconductor structure comprising a buried insulator comprising silicon nitride than in a semiconductor structure comprising a buried insulator comprising only silicon dioxide. Alternatively, the trap-rich layer comprises silicon or polysilicon.
According to example embodiments, the silicon carbide is amorphous.
The traps of the amorphous silicon carbide of the trap-rich layer capture the free carriers at the interface between the silicon of the top layer and the intermediate layer, thereby enabling the Silicon-On-Insulator substrate to recover its nominal resistivity, linearity, eliminating the DC dependency and leading to a substantial reduction of RF losses and crosstalk.
According to example embodiments, a thickness of the trap-rich layer is between tens of nanometers and several micrometers. For example, a thickness of the trap-rich layer comprising amorphous silicon carbide can reach a few tens of nanometers. Alternatively, a thickness of the trap-rich layer comprising polysilicon can reach a few micrometers.
According to example embodiments, a thickness of the buried insulator is between 100 nm and 500 nm.
According to example embodiments, a thickness of the intermediate layer comprising the buried insulator and the trap-rich layer is between a few hundreds of nanometers and a few micrometers.
According to example embodiments, the epitaxial III-N semiconductor layer stack further comprises a spacer layer formed between the first active III-N layer and the second active III-N layer.
This way, the spacer layer epitaxially grown between the first active III-N layer and the second active III-N layer enhances the electron mobility within the epitaxial III-N semiconductor layer stack.
According to example embodiments, the first active III-N layer comprises gallium nitride and wherein the second active III-N layer comprises aluminum gallium nitride.
Preferably, the first active III-N layer is grown epitaxially and comprises pure gallium nitride, preferably a monolayer of gallium nitride.
According to example embodiments, the first active III-N layer comprises InAlGaN, and the second active III-V layer comprises InAlGaN, and the second active III-N layer comprises a bandgap larger than a bandgap of the first active III-N layer and the second active III-N layer comprises a polarization larger than the polarization of the first active III-N layer.
This way, the use of different materials in adjacent first active III-N layer and second III-V layer causes polarization that contributes to a conductive 2DEG region near the junction between the first active III-N layer and the second active III-N layer, in particular, in the first active III-N layer that comprises a bandgap narrower than the bandgap of the second active III-N layer.
The first active III-N layer, for example, has a thickness between 20 and 500 nm, preferably between 30 and 300 nm, more preferably between 50 and 250 nm, such as, for example, from 100 to 150 nm. The second active III-N layer, for example, has a thickness between 10to 100 nm, preferably between 20 to 50 nm. Such a combination of thicknesses provides good characteristics for the active layer, for example, in terms of the 2DEG obtained.
According to example embodiments, the spacer layer comprises aluminum nitride.
Preferably, the spacer layer is grown epitaxially and comprises pure aluminum nitride.
According to example embodiments, a thickness of the spacer layer is lower than 2 nm.
This way, the spacer layer is kept thin enough to minimize the roughness of the spacer layer. With minimized roughness, the spacer layer prevents the diffusion or the migration of Group III atoms into at least the first active III-N layer. This way, the thermal stability of the semiconductor structure is further improved. In other words, the thinner the spacer layer, the better the thermal stability of the semiconductor structure. Preferably, the thickness of the spacer layer is between 0.5 nm and 1.5 nm. Even more preferably, the thickness of the spacer layer is between 0.8 nm and 1 nm.
According to example embodiments, the epitaxial III-N semiconductor layer stack further comprises an epitaxially grown buffer layer grown between the substrate and the epitaxial active layer.
The buffer layer may be of a different nature than the substrate, in that, for instance, the bandgap of the substrate and buffer layer are relatively far apart such as 1.1 eV and 6.2 eV, respectively, in the sense that the buffer layer has a high bandgap, in order to provide present characteristics, such as high break down voltage, e.g., higher than 250 V, preferably higher than 500 V, even more preferably higher than 1000 V, such as higher than 2000 V, or even much higher. The buffer layer is, for example, a III-V buffer layer with a high bandgap. Therein III refers to Group III elements, such as B, Al, Ga, In, TI, Sc, Y and Lanthanide and Actinide series. Therein V refers to Group V elements, such as N, P, As, Sb, Bi. The buffer layer may comprise a stack of layers, in an example typically the first one being a nucleation layer.
According to example embodiments, the semiconductor structure further comprises a passivation stack formed on top of the epitaxial III-N semiconductor layer.
The passivation stack is formed in-situ with the formation of the epitaxial III-N semiconductor layer stack. The passivation stack is, for example, formed on top of the second active III-N layer. This way, a fully crystalline passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. Alternatively, a partially crystalline passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. The passivation stack may also be formed by ex-situ deposition with the help of epitaxy tools like atomic layer deposition, also referred to as ALD, chemical vapor deposition, also referred to as CVD, or physical vapor deposition, also referred to as PVD. Alternatively, the passivation stack may be formed by in-situ deposition in a MOCVD or an MBE chamber. Alternatively, the passivation stack may be formed by depositing an amorphous film of the same material and recrystallizing it using thermal anneal. The passivation stack on top of the second active III-N layer, for example, comprises Gallium Nitride. Alternatively, the passivation stack on top of the second active III-N layer comprises Gallium Nitride and Silicon Nitride.
A passivation stack is formed between the epitaxial III-N semiconductor layer stack and, for example, a gate of a transistor. The passivation stack may be formed only under the gate and may serve additionally as gate dielectric. Alternatively, the passivation stack may be formed on top of the epitaxial III-N semiconductor layer stack and may fully cover the epitaxial III-N semiconductor layer stack. Alternatively, the passivation stack may be formed on top of the epitaxial III-N semiconductor layer stack and partially cover the surface of the epitaxial III-N semiconductor layer stack, for example, it may be formed in the ungated area between the source and the drain of a high mobility electron transistor, where it serves as passivation and prevents the depletion of the underlying 2DEG.
According to example embodiments, the passivation stack further comprises an oxide layer and/or silicon nitride.
This way, the passivation layer of the semiconductor structure according to a first example aspect of the present disclosure comprises silicon nitride and/or an oxide layer that acts as a passivation layer. The oxide layer exhibits an electrically clean interface to the second active III-N layer, a high dielectric constant to maximize electrostatic coupling between electrical contacts formed onto the semiconductor structure and the 2DEG, which results in an increase of, for example, the transconductance of high electron mobility transistors manufactured with the semiconductor structure and a sufficient thickness to avoid dielectric breakdown and leakage by quantum tunneling.
According to a second example aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, wherein the method comprises the steps of:
As previously mentioned, presence of p-type dopants at the interface between the Group III-nitride heterostructure and a silicon substrate onto which the Group III-nitride heterostructure is, for example, epitaxially grown can be measured with, for example, spreading resistance profiling measurements. Such presence of p-type dopants at the interface between Group III-nitride heterostructure and silicon is attributed to the diffusion or migration of impurities from the initial growth layer of the epitaxial layers of the Group III-nitride heterostructure to the silicon substrate. The impurities act as a p-type impurity for the silicon substrate. More particularly, such presence of p-type dopants at the interface between Group III-nitride heterostructure and silicon is attributed to the diffusion or migration of Group III elements into the silicon substrate in which they act as p-type impurities for the silicon substrate.
With the method for manufacturing a semiconductor structure according to the present disclosure, the diffusion or migration of Group III elements from the epitaxial layers of the Group III-nitride heterostructure into the Silicon-On-Insulator substrate is contained in a surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure, for example, in the top layer and optionally close to the interface between the intermediate layer and the top layer. Indeed, with the method according to the present disclosure, the intermediate layer of the Silicon-On-Insulator substrate confines the diffusion or migration of Group III elements within the surface region of the Silicon-On-Insulator substrate close to the epitaxial layers of the Group III-nitride heterostructure, for example, in the top layer and optionally close to the interface between the intermediate layer and the top layer, thereby shortening the diffusion distance of the impurities into the Silicon-On-Insulator substrate.
With the method for manufacturing a semiconductor structure according to the present disclosure, the n-type doping of the top layer of the Silicon-On-Insulator substrate compensates for the concentration of Group III elements that diffuses from the epitaxial layers into the Silicon-On-Insulator substrate. In other words, the n-type doping of the top layer of the Silicon-On-Insulator substrate balances out a concentration of p-type dopants at the interface between the epitaxial layers and the Silicon-On-Insulator substrate, wherein the concentration of these p-type dopants results from a diffusion of Group III atoms from the epitaxial III-N semiconductor layer stack into the top layer of the Silicon-On-Insulator substrate.
This way, the semiconductor structure manufactured with the method according to the present disclosure demonstrates improved performance at high-power and high-frequency, improved resistivity, and reduced power losses and linearity problems.
The epitaxial III-N semiconductor layer stack comprises an epitaxial active layer that comprises the first active III-N layer, optionally a spacer layer, and the second active III-N layer. The epitaxial active layer is formed in-situ by epitaxial growth in a metal-organic chemical vapor deposition epitaxial chamber, also referred to as MOCVD, or in a metal-organic vapor phase epitaxial chamber, also referred to as MOVPE, or in a molecular beam epitaxial chamber, also referred to as MBE, or in a chemical beam epitaxial chamber, also referred to as CBE.
The semiconductor structure can be formed by epitaxial growth by metal-organic chemical vapor deposition (MOCVD) or metal-organic vapor phase epitaxy (MOVPE) or be molecular beam epitaxy (MBE) or chemical beam epitaxy (CBE). In the MOVPE or in the MOCVD process, the epitaxial III-N semiconductor layer stack is epitaxially grown on a Silicon-On-Insulator substrate, typically at pressures, for example, between 5 mBar and 1 Bar and typically at temperatures, for example, between 600° C. and 1200° C. The precursor materials can be but are not limited to ammonia (NH3) for nitrogen; tri-methyl-Ga (TMGa) or tri-ethyl-Ga (TEGa) for gallium, tri-methyl-Al (TMAl) or tri-ethyl-Al (TEAl) for aluminum; tri-methyl-Indium (TMIn) for indium; and silane (SiH4) or disilane (SiH3)2 for silicon.
The Silicon-On-Insulator substrate may comprise a buried insulator that comprises silicon oxide. The Silicon-On-Insulator substrate may then be produced by several methods such as, for example, a Separation by IMplantation of Oxygen, known as SIMOX, or wafer bonding, or by a seed method.
According to example embodiments, the providing a top layer comprising n-type doped silicon comprises doping the silicon of the top layer by thermal diffusion of n-type dopants into the silicon of the top layer.
Preferably, an n-type doping concentration of the top layer is within the range of 1.1015 cm−3 to 5.1015 cm−3.
According to example embodiments, the providing a top layer comprising n-type doped silicon comprises doping the silicon of the top layer by ion implantation of n-type dopants into the silicon of the top layer.
Preferably, an n-type doping concentration of the top layer is within the range of 1.1015 cm−3 to 5.1015 cm−3.
According to example embodiments, the n-type dopants comprise one or more of the following:
Some example embodiments will now be described with reference to the accompanying drawings.
The drop in resistivity at the interface between the gallium nitride and the silicon substrate is further investigated with spreading resistance profiling measurements. The results of such measurements are, for example, depicted on
Although the present disclosure has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present disclosure may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes that come within the scope of the claims are therefore intended to be embraced therein.
It will furthermore be understood by the reader of this disclosure that the words “comprising” or “comprise” do not exclude other elements or steps, that the words “a” or “an” do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms “first,” “second,” “third,” “a,” “b,” “c,” and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms “top,” “bottom,” “over,” “under,” and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention can operate according to the present disclosure in other sequences, or in orientations different from the one(s) described or illustrated above.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2113655 | Dec 2021 | FR | national |
This application is a national phase entry under 35 U.S.C. § 371 of International Patent Application PCT/EP2022/082085, filed Nov. 16, 2022, designating the United States of America and published as International Patent Publication WO 2023/110267 Al on Jun. 22, 2023, which claims the benefit under Article 8 of the Patent Cooperation Treaty to French Patent Application Serial No. FR2113655, filed Dec. 16, 2021.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/082085 | 11/16/2022 | WO |
