Patent Application
20100148153
Most integrated circuits today are based on silicon, a Group IV element of the Periodic Table. Compounds of Group III-V elements such as gallium arsenide (GaAs), indium antimonide (InSb), indium phosphide (InP), and indium gallium arsenide (InGaAs) are known to have far superior semiconductor properties than silicon, including higher electron mobility and saturation velocity. These materials may thus provide superior device performance.
In various embodiments, an apparatus and method relating to the formation of a group III-V material semiconductor device are described. In the following description, various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order, in series or in parallel, than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
In the illustrated embodiment, the device 100 includes a substrate 102, which may be any material or materials on which the device 100 may be made. In some embodiments the substrate 102 may be a substantially single-crystal silicon material, a substantially single-crystal silicon material that is doped, a multi-crystal or multi-layer substrate 102. The substrate 102 may not comprise silicon in some embodiments, but may instead comprise a different substrate material, such as a GaAs or InP. The substrate 102 may include one or more material(s), device(s), or layer(s), or may be a single material without multiple layers.
There is a buffer region 104 on the substrate 102 in the illustrated embodiment. The buffer region 104 may function to accommodate for a lattice mismatch between the substrate 102 and regions above the buffer region 104 and to confine lattice dislocations and defects.
There is a lower barrier region 106 on the buffer region 104, a delta-doped region 108 on the lower barrier region 106, a spacer region 110 on the delta-doped region 108, a channel region 112 on the spacer region 110, and an upper barrier region 114 on the channel region 112 in the illustrated embodiment. The delta-doped region 108 is doped according to the design of the device 100 and the targeted threshold voltage of the device 100. Note that the term “delta-doped region” as used herein also encompasses a modulation doped region, and some embodiments of the device 100 may have a modulation doped region 108 instead of a delta-doped region 108; the term “delta-doped region” as used herein encompasses both embodiments. The delta-doped region 108 is below the channel region 112, which allows the distance between the channel region 112 and the gate 118 to be less than if the delta-doped region 108 were above the channel region 112. The channel region 112 and delta-doped region 108 are sandwiched between the upper and lower barrier regions 114, 106.
There is a gate dielectric 116 on the upper barrier region 118. On the high-k gate dielectric layer 116 is a gate electrode 118, the material of which may be chosen based on a desired work function. The device 100 also has source and drain regions 120 and 122. As illustrated, the device 100 is a recessed gate 118 device 100, although in other embodiments it may be a different type of device 100 that lacks a recessed gate 118.
The substrate 102 surface on which the device 100 is to be formed may have a resistance between about 1 ohm and about 50,000 ohms per centimeter. The high resistivity may be achieved by a low dopant concentration, lower than about 1016 carriers/cm3.
In some embodiments the substrate 102 may be a substantially single-crystal silicon material, a substantially single-crystal silicon material that is doped, a multi-crystal or multi-layer substrate 102. In various embodiments, the substrate 102 could comprise germanium, germanium on silicon, or could be a silicon-on-insulator substrate 102. The substrate 102 may not comprise silicon in some embodiments, but may instead comprise a different material, such as a different semiconductor or a group III-V material such as GaAs or InP. The substrate 102 may include one or more material(s), device(s), or layer(s), or may be a single material without multiple layers.
The nucleation region 130 comprises gallium arsenide in one embodiment, although other materials such as GaSb or AlSb may be used in other embodiments. (Note that as used herein, when materials designated by their elements without subscripts, these designations encompass any mix of percentages of the elements. For example, “InGaAs” encompasses InxGa1-xAs, with x ranging between zero (GaAs) and one (InAs). Similarly, InAlAs encompasses In0.52Al0.48As.) It is formed by molecular beam epitaxy (MBE), migration enhanced epitaxy (MEE), metal-organic chemical vapor deposition (MOCVD), atomic layer epitaxy (ALE), chemical beam epitaxy (CBE), or another suitable method. It has a thickness of less than about 500 angstroms in some embodiments. In embodiments where the substrate 102 is a vicinal silicon material, the nucleation region 130 may be made sufficiently thick to fill all the terraces of the silicon substrate 102. In an alternative embodiment, other suitable nucleation region 130 materials or thicknesses may be used, or the nucleation region 130 may be ommitted.
On the nucleation region 130 is a first buffer region 132 in the illustrated embodiment. In an embodiment, the first buffer region 132 comprises a GaAs material, although other materials, such as InAlAs, AlSb, or other materials may be used. In an embodiment, the first buffer region 132 consists substantially the same material as the nucleation region 130. The buffer region 132 may also be formed by molecular beam epitaxy (MBE), migration enhanced epitaxy (MEE), metal-organic chemical vapor deposition (MOCVD), atomic layer epitaxy (ALE), chemical beam epitaxy (CBE), or another suitable method. The first buffer region 132 may have a thickness of less than one micron, between 0.3 microns and one micron, or another thickness in various embodiments.
The first buffer region 132 may be formed by the same process used to form the nucleation region 130 in some embodiments. In such an embodiment, the growth of the first buffer layer 108 may be performed at a higher temperature than that used for the nucleation layer 104. While first buffer region 132 may considered and is shown as a separate region than nucleation region 130, both regions 130, 132 may be considered buffers, with region 132 thickening the III-V buffer region started by nucleation region 130, and gliding dislocations. The film quality of region 132 may be superior to that of the nucleation region 132 because it may be formed at a higher growth temperature. Also, during the formation of region 132, the flux rate can be relatively high because the polar nucleation region 130 may eliminate danger of anti-phase domains (APD) formation.
In the illustrated embodiment, there is a graded buffer region 134 on the first buffer region 132. In the illustrated embodiment, the graded buffer region 134 comprises indium aluminum arsenide InxAl1-xAs, with x ranging between zero (or another selected starting amount) and the amount of In desired in the bottom barrier region, although the graded buffer region 134 may comprise other materials and may be doped. For example, the graded buffer region 134 may comprise AlAs adjacent the first buffer region 132 (thus, x=0), with increasing amounts of In present (although not necessarily at a linear increase rate) higher in the graded buffer region 134 so that the graded buffer region 134 comprises In0.52Al0.48As adjacent the bottom barrier region 106. In some embodiments, the top of the graded buffer region 134 comprises InxAl1-xAs, with x being between 0.52 and 0.70. The graded buffer region 134 has a thickness of less than about 5 microns in an embodiment. In other embodiments, it may have sufficient thickness that most defects present at its bottom surface are not present at its top surface. Any suitable method may be used to form the graded buffer region 134.
Note that some embodiments may lack a buffer region 132 and/or graded buffer region 134. For example, in embodiments where the substrate 102 comprises a group III-V material, the device 100 may lack buffer region 132 and/or graded buffer region 134.
The gate electrode 118 may comprise a metal-containing material such as Pt/Au, Ti/Au, Ti/Pt/Au, or another material or materials. In some embodiments, the gate has a work function of over 4.5 eV, although other workfunction may be possible.
In the illustrated embodiment, the source and drain regions 120, 122 are on contact regions 150. These separate contact regions 150 may be absent in some other embodiments. In an embodiment, the contact regions 150 may comprise InGaAs (InxGa1-xAs), and may be graded or have a substantially constant ratio of In to Ga through their thicknesses. In an embodiment, the top region of the contact regions 150 may comprise In0.53Ga0.47As, but other compositions may be used in other embodiments.
In one embodiment, the source and drain regions 120, 122 may comprise NiGeAu. In another embodiment, the source and drain regions 120, 122 may comprise TiPtAu. In other embodiments, the source and drain regions 120, 122 may comprise another material.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on arid in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
