Hard mask layer stack and a method of patterning

Abstract

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIGS. 1A and 1B illustrate plan views on conventional devices.

FIG. 2A illustrates a plan view on a memory device with symmetrical landing pads.

FIG. 2B illustrates a plan view on a memory device with asymmetrical landing pads.

FIGS. 3A to 3C illustrate plan views on a plurality of subsets of landing pads according to embodiments of the invention.

FIGS. 4A to 4F illustrate cross-sectional views of the substrate at different processing steps and plan views on the substrate after those processing steps according to an embodiment of the invention.

FIGS. 5A to 5G illustrate cross-sectional views of the substrate at different processing steps and plan views on the substrate after those processing steps according to another embodiment of the invention.

FIG. 6 illustrates a cross-sectional view of the new hard mask.

FIGS. 7A to 7D illustrate cross-sectional views of the substrate at different processing steps using the new hard mask.

FIGS. 8A and B illustrate plan views on the first photomask according to embodiments of the invention.

FIG. 9 illustrates a plan view on the second photomask according to the first photomask of FIGS. 8A and 8B.

FIGS. 10A and 10B illustrate plan views on the first photomask according to other embodiments of the invention.

FIG. 11 illustrates a plan view on the second photomask according to the first photomask of FIGS. 10A and 10B.

FIGS. 12A to 12D illustrate plan views on the first photomask according to yet another embodiment of the invention.

FIG. 13 illustrates a plan view on the second photomask according to the first photomask of FIG. 12D.

FIG. 14 illustrates a plan view on assist structures in the second photomask according to the detail of FIG. 11.

Claims

1. A hard mask layer stack for patterning a layer to be patterned, comprising: a carbon layer disposed on top of the layer to be patterned;a first layer of a material selected from a group comprising SiO2 and SiON, disposed on top of the carbon layer; anda silicon layer disposed on top of the first layer.

2. The hard mask layer stack of claim 1, wherein the carbon layer is thicker than the first layer.

3. The hard mask layer stack of claim 1, wherein the first layer is thicker than the silicon layer.

4. The hard mask layer stack of claim 1, wherein the thickness of the silicon layer is less than 50 nm.

5. The hard mask layer stack of claim 1, wherein the carbon layer is made of elemental carbon.

6. The hard mask layer stack of claim 1, wherein the carbon layer is deposited by a CVD process.

7. The hard mask layer stack of claim 1, wherein the stack has a thickness greater than 100 nm.

8. A method of patterning a layer to be patterned, comprising: providing a layer to be patterned;providing a hard mask layer stack, comprising a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from a group comprising of SiO2 and SiON disposed on top of the carbon layer, and a silicon layer diposed on top of the first layer, on the layer to be patterned;patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer to be patterned; andetching the uncovered portions of the layer to be patterned.

9. The method of claim 8, wherein the patterning of the silicon hard mask layer further comprises: providing a first photoresist layer on top of the silicon hard mask layer;imaging first structures in a first exposure step using a first photomask into the first photoresist layer; anddeveloping the first photoresist layer, so as to generate a photoresist pattern on the silicon hard mask layer;

10. The method of claim 9, wherein the patterning of the silicon hard mask layer further comprises: etching the uncovered portions of the silicon hard mask layer thereby forming first patterns; andremoving the first photoresist layer from the silicon hard mask layer leaving a surface of the substrate with regions covered by the silicon hard mask layer and regions with uncovered first layer of the hard mask layer stack.

11. The method of claim 10, wherein the patterning of the silicon hard mask layer further comprises: providing a second photoresist layer on top of the surface; andimaging second structures in a second exposure step using a second photomask into the second photoresist layer.

12. The method of claim 11, wherein the patterning of the silicon hard mask layer further comprises: developing the second photoresist, so as to generate a photoresist pattern on the surface; andetching the uncovered portions of the silicon hard mask layer thereby forming second patterns.

13. The method of claim 12, wherein the first structures comprise conductive lines and the second structures comprise landing pads connected with the conductive lines of a semiconductor device.

14. A memory device with at least a first layer pattern with a hard mask layer stack, the stack comprising: a carbon layer disposed on top of the layer to be patterned;one of a silicon oxide layer and a silicon oxinitride layer on the carbon layer; anda silicon layer disposed on top of one of the silicon oxide and silicon oxinitride layers.

15. The hard mask layer stack of claim 14, wherein the carbon layer is thicker than the first layer.

16. The hard mask layer stack of claim 14, wherein the first layer is thicker than the silicon layer.

17. The hard mask layer stack of claim 14, wherein the thickness of the silicon layer is less than 50 nm.

18. The hard mask layer stack of claim 14, wherein the carbon layer is made of elemental carbon.

19. The hard mask layer stack of claim 14, wherein the carbon layer is deposited by a CVD process.

20. The hard mask layer stack of claim 14, wherein the stack has a thickness greater than 100 nm.