HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH SELF-ALIGNED SUB-LITHOGRAPHIC METAL-SEMICONDUCTOR ALLOY BASE CONTACTS

Abstract

A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.

Description

FIELD OF THE INVENTION

The present invention relates to contacts made to semiconductor devices, and more specifically to metal-semiconductor alloy (e.g., silicide or germanide) contacts with sub-lithographic dimensions made to the base of a heterojunction bipolar transistor (HBT). The present invention also relates to methods of fabricating sub-lithographic contacts to the HBT base.

BACKGROUND OF THE INVENTION

Reduction of the extrinsic base-collector capacitance (C_bex) improves the heterojunction bipolar transistor's (HBT's) speed. Both f_t (cutoff frequency) and f_max (maximum oscillation frequency) are dependent on C_box. In conventional HBTs much of the extrinsic base-collector junction area is required for forming the base contacts. Additionally, the metal contacts (e.g., vias) to the extrinsic base are not self-aligned to the emitter, but defined by lithography. This further increases the extrinsic base area since the layout design rules must allow for overlay error.

It is therefore desirable to fabricate an HBT having a base self-aligned to the emitter, and a small (preferably sub-lithographic; less than 100 nm) extrinsic base region to which metal contacts are also made self-aligned. The extrinsic base resistance can also be minimized by thickening the extrinsic base and by converting the top portion of the extrinsic base into a metal-semiconductor alloy such as, for example, a silicide.

In view of the foregoing, there is a need for providing an HBT with a small base-collector capacitance and a low extrinsic base resistance. The present invention provides an HBT with a sub-lithographic extrinsic base that is defined by the footprint of a sidewall spacer made adjacent to the emitter. The fabrication of the extrinsic base is therefore self-aligned to the emitter. To lower the base resistance, the extrinsic portion of the base is first thickened by selective epitaxy and then the top portion of the extrinsic base is converted into a metal-semiconductor alloy. The metal contacts to the extrinsic base are also fabricated as part of a silicidation process, and are self-aligned to the extrinsic base.

SUMMARY OF THE INVENTION

The present invention provides an HBT with a self-aligned sub-lithographic extrinsic base to which self-aligned metal-semiconductor alloy and metal contacts are made.

The inventive structure and method provide several advantages over the prior art. First, the present invention minimizes the parasitic component of the capacitance between the extrinsic base and the collector, and it lowers the base extrinsic resistance. Secondly, the present invention provides a self-align metal-semiconductor alloy (e.g., SALICIDE) process for forming metal-semiconductor alloy regions over the extrinsic base and the emitter that avoid lithography. Third, the inventive method forms metal contacts to the metal-semiconductor alloy regions of the extrinsic base, again without the use of lithography.

In a first aspect of the present invention, a semiconductor structure such as a HBT comprising, from top to bottom, an emitter, a base, and a collector isolated by a shallow trench isolation oxide is disclosed. The base has an extrinsic portion that is defined by a disposable spacer previously formed on the sidewalls of the emitter. The extrinsic base is further thickened by epitaxy and its top surface is converted into a metal-semiconductor alloy, preferably a silicide, which connects to a conductive line that extends over the shallow trench isolation oxide.

In a second aspect of the invention, a method for fabricating an HBT with a self-aligned sub-lithographic extrinsic base to which self-aligned metal-semiconductor alloy and self-aligned metal contacts are made is disclosed. The disclosed HBT comprises an emitter with thin sidewall spacers (e.g., SiO₂) and thick disposable spacers (Si₃N₄) formed by a damascene process. The extrinsic base-collector junction area is defined by the disposable spacer that is formed on the emitter's thin SiO₂ sidewall. The portion of the extrinsic base-collector junction, not protected by the disposable spacer, is etched out by reactive-ion etching (RIE), and later replaced by an oxide. The oxide, which is blanket deposited, is polished by chemical mechanical polishing (CMP) to the level of the emitter, and may be recessed further by some amount. The disposable spacers are etched to expose the extrinsic base.

Next, selective semiconductor epitaxy is used to thicken the extrinsic base. A blanket metal film is deposited and thereafter patterned by the mask that defines the shallow trench isolation (STI) around the device. Annealing is used to form a metal-semiconductor alloy, e.g., a silicide, by reacting the metal film with the raised base and the top of the emitter. The structure is then planarized by a second oxide deposition and CMP such that the top of the emitter is exposed. The top portion of the unreacted metal over the emitter's SiO₂ sidewalls is also exposed. The unreacted metal is then selectively etched (with respect to the metal-semiconductor alloy) from the sidewalls of the emitter. The unreacted metal buried beneath the oxide is protected from this etching process and remains in contact with the metal-semiconductor alloy over the raised base regions. Contact to the base is then made by a via to the buried metal.

In yet another embodiment of the present invention, which is aimed to avoid further metal-semiconductor formation, e.g., silicidation, of the base during back-end of the line (BEOL) processing, the dielectric protecting the unreacted metal is removed and that metal is converted into a metal-semiconductor alloy.

This aspect of the present invention is performed in a self-aligned manner by the following processing steps: a blanket semiconductor, e.g., silicon, layer is deposited, the buried conductive metal is converted into a metal-semiconductor alloy, e.g., a silicide, by annealing and reacting the conductive metal with the deposited semiconductor layer, and finally etching is used to remove any unreacted semiconductor (for example, a wet tetramethylammonium-hydroxide (TMAH) etch). The structure is planarized by oxide deposition and CMP. A contact to the base is made using a via to the metal-semiconductor alloy that extends over the oxide.

It is noted that the preferred metal-semiconductor alloys comprise a silicide or a germanide, with silicides being most preferred.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-13 are pictorial representations (through cross sectional views) illustrating the basic processing steps of the present invention for fabricating an HBT with a self-aligned sub-lithographic extrinsic base including self-aligned silicide and metal contacts.

FIGS. 14-19 are pictorial representations (through cross sectional views) illustrating further processing steps that may optionally be used in the present invention in conjunction with the basic processing steps illustrated in FIGS. 1-13.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides an HBT with a self-aligned sub-lithographic extrinsic base as well as methods for fabricating the same, will now be described in greater detail by referring to the following discussion. In this discussion, reference will be made to various drawings that illustrate embodiments of the present invention. Since the drawings of the embodiments of the present invention are provided for illustrative purposes, the structures contained therein are not drawn to scale.

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced with viable alternative process options without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.

It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present, In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.

As stated above, a semiconductor structure such as a HBT is provided that comprises, from top to bottom, an emitter, a base, and a collector isolated by a shallow trench isolation oxide. The base has an extrinsic portion that is defined by a disposable spacer previously formed on the emitter sidewalls. The extrinsic base is further thickened by epitaxy and its top surface is converted into a metal-semiconductor alloy, preferably a silicide, which connects to a conductive line (e.g. metal) that extends over the shallow trench isolation oxide.

The basic method of the present invention that fabricates the above mentioned semiconductor structure is shown, for example, in FIGS. 1-13. Referring to FIG. 1, the starting semiconductor substrate consist of a semiconductor wafer, such as silicon, 101, a collector region (C) 100 isolated by a shallow trench isolation (STI) oxide 102, a base (B) consisting of a single-crystal semiconductor film region 103 formed over the collector region 100 and a polycrystalline semiconductor film 103A formed over the STI oxide 102, and an emitter (E) 104 formed over the base using a damascene process. In a highly preferred embodiment of the present invention, the wafer 101 is comprised of bulk silicon, and the semiconductor films 103 and 103A are comprised of SiGe.

The HBT base (B) is typically formed by non-selective semiconductor epitaxy. In one embodiment of the present invention, a non-selective SiGe epitaxy is employed. The base layer forms as a single-crystal semiconductor film 103 over the single-crystal semiconductor collector region 100, which serves as a template for the semiconductor epitaxy. It is noted that a portion of the single-crystal semiconductor film 103 serves as the extrinsic base of the inventive structure, Over the STI oxide 102, the base layer deposits as polycrystalline semiconductor 103A since the oxide is amorphous and does not provide a template for epitaxy. The HBT emitter (E) 104 is typically formed by deposition of poly-Si into a trench formed in an oxide 105. The excess poly-Si deposited over the oxide 105 is removed by CMP, The details of this damascene process can be found in U.S. Ser. No. 11/460,013, filed Jul. 26, 2006 (attorney docket FIS920050312US1), the disclosure of which is incorporated fully herein by reference.

Referring to FIG. 2, the emitter 104 is recessed by conventional etching and a silicon nitride cap 106 is deposited by conventional techniques such as chemical vapor deposition, over the recessed emitter 104. The oxide 105 is thereafter etched selectively to expose the base (B) and sidewalls of the emitter (E). Referring to FIG. 3, thin SiO₂ spacers 107 are formed on either side of the emitter. A Si₃N₄ layer is blanket deposited and etched to form Si₃N₄ spacers 108, as illustrated in FIG. 4. During the etching process used in forming the spacers 108, the cap 106 is also etched forming emitter cap 106′.

The width W of the spacer 108 footprint will later define the lateral dimension of the extrinsic base. As illustrated in FIG. 5, reactive ion etching (RIE) is used to etch the semiconductor film 103 and 103A from regions not masked by the spacer 108 or the emitter 104. The RIE chemistry is chosen to etch primarily silicon or SiGe and is selective to dielectrics such as silicon dioxide (SiO₂) and silicon nitride (Si₃N₄). As an example, RIE with HBr chemistry can have a typical etch selectivity larger than 1:100 (i.e., oxide etching is 100 times slower than silicon etching). The etching also removes some of the collector (C) material. The details of a similar collector material removal process can be found in U.S. Ser. No. 6,864,560. The amount of etching into the collector is not critical. It is noted that in FIG. 5 reference numeral 109 denotes the etched region created by this step of the present invention.

Referring to FIG. 6, an oxide or other like insulator 110 is blanket deposited, and chemical mechanical polishing (CMP) is performed to planarize the surface. The insulator 110 is polished down to the emitter cap 106′ level. The insulator 110 is then recessed farther below the emitter cap 106′ line, but is kept above the STI 102 line.

Referring to FIG. 7, the silicon nitride spacers 108 are selectively removed to expose the top surface of the semiconductor film 103. It is noted that during the removal of the spacers 108 the emitter cap 106′ is also removed from the structure. The etched area previously occupied by spacers 108 is denoted by reference numeral 111 in FIG. 7. Since the semiconductor film 103 (which also forms the extrinsic base 103e) is typically made thin (on the order of about 30 nm or less) to achieve high gain in the HBT, the exposed semiconductor film 103 which forms the extrinsic base 103e has to be thickened prior to metal-semiconductor alloy, e.g., silicide, formation. The exposed portions of the semiconductor film 103 are thickened by selective semiconductor, e.g., silicon or SiGe, epitaxy (i.e., additional semiconductor 112 is deposited only over the exposed semiconductor surfaces, but not over dielectric surfaces) as illustrated by FIG. 8. Because the emitter 104 is also exposed, additional semiconductor 112′ also forms atop the emitter 104.

The semiconductor 112 may be in-situ doped (i.e., the dopant atoms are added to the semiconductor lattice during epitaxy). In principle, ion implantation can also be used to dope semiconductor 112, however, an emitter capping may be required to block the dopants from doping the emitter 104. Other methods can also be employed to dope the semiconductor 112. For example, the semiconductor 112 may be selectively doped later on in the process or block masks can be formed atop the emitter and then an in-situ doped deposition process can be used to form the semiconductor selectively.

Referring to FIG. 9, a metal film 113 such as Ti, Co, Ni, Pt, W or alloys thereof is blanket deposited over the structure. The metal 113 is patterned with a mask (not shown) that is slightly larger than the mask used to define the collector (shallow trench isolation mask).

Referring to FIG. 10, a metal-semiconductor alloy 115 such as, a silicide or germanide, is formed by reacting the metal 113 with the semiconductor surface 112 and the top surface of the emitter 104. The portions of metal 113 not in contact with a semiconductor surface, e.g., over the SiO₂ spacers 107 and over the insulator 110, do not convert into a metal-semiconductor alloy. Reacting the metal with the semiconductor surface is typically done by rapid thermal annealing (RTA). The thickness of the metal layer 113 is chosen such that all of the added semiconductor 112′ over the emitter, and some of the top emitter material 104 is reacted to from the metal-semiconductor alloy 115. This circumvents the formation of a p-n junction over the emitter (E) since the emitter (E) 104 has a different doping polarity than that of the base (B) 103.

Referring to FIG. 11, an insulator 116 such as an oxide or nitride is blanket deposited over the structure. The structure is polished by CMP, such that the metal-semiconductor alloy 115 on the top of the emitter (E) is exposed. The top edge of metal 113 that covers the SiO₂ spacers 107 is also exposed. It is also possible to deposit the insulator 116 prior to reacting metal 113 with the semiconductor surface, and then perform the RTA step with the dielectric 116 covering the metal 113.

Referring to FIG. 12 the unreacted metal 113 over the SiO₂ spacers 107 is selectively etched with respect to the metal-semiconductor alloy 115 and the insulators. In FIG. 12, reference numeral 117 denotes the gap created after removing the unreacted metal 113. As an example, for metal-semiconductor alloys such as Ni-silicide (NiSi) and Co-silicide (CoSi₂) a common etch chemistry used to remove the unreacted metal is H₂O₂:H₂SO₄ 10:1 at 65° C. for 10 min. The unreacted metal 113 over the insulator 110 is not etched since it is protected by the insulator 116.

Referring to FIG. 13, an insulator 118 such as an oxide or nitride is blanket deposited over the structure. The insulator 118 also fills the gap 117 left by the etched metal 113. CMP is used to planarize the structure. Contact vias to the buried conductive extension 113, emitter and collector (not shown) are defined by lithography and RIE and filled with metal 119.

To avoid further metal-semiconductor alloy formation (e.g., silicidation) of the base during back-end of the line (BEOL) processes that requires elevated temperatures (of about 400° C.) the unreacted metal 113 is converted into a metal-semiconductor alloy. This aspect of the present invention is now described in greater detail by referring to the following discussion as well as FIGS. 14-19.

This aspect of the present invention begins with first providing the structure shown in FIG. 10. A film 216 is then blanket deposited over the substrate providing the structure shown, for example, in FIG. 14. Following the deposition, film 216 is polished to expose the top of the emitter including the edge of metal 113 that is laid over the SiO₂ spacers 107. The purpose of film 216 is to mask the portion of metal 113 laid over the insulator 110, while the portion of the metal 113 laid over the SiO₂ spacers 107 is etched out forming etched area 117′ (FIG. 15). Film 216 can also consist of materials such as a polyimide or even a photoresist. These materials are deposited by spin-coating and tend to be self-planarizing (i.e., the surface topography is washed out by the film). Rather than using CMP for planarization, it is possible to etch these materials until the top surface of the emitter is exposed. Typical etching techniques that can be used comprises of oxygen plasma and reactive ion etching.

As stated above and illustrated in FIG. 15, the unreacted metal 113 over the SiO₂ spacers 107 is selectively etched with respect to the metal-semiconductor alloy 115 and the insulators forming etched area 117′. The details of the etching chemistry were discussed earlier in reference to FIG. 12.

Next, and as shown in FIG. 16, film 216 is stripped to expose the metal 113. A blanket film of silicon (or other like semiconductor) 218 is deposited over the structure. The silicon (or other like semiconductor) film 218 is reacted with the metal 113 to form a silicide (or other like metal-semiconductor alloy) 219 as illustrated in FIG. 17. The silicide (or other like metal-semiconductor alloy) 219 formation is carried out by a rapid thermal anneal similar to that used to form the metal-semiconductor alloy 115. The silicide (or other like metal-semiconductor alloy) 219 forms only where a metal 113 exist. In regions not covered by the metal 113, the silicon (or other like semiconductor) film 218 does not react. The unreacted semiconductor material, e.g., silicon, is removed by a selective etch. As an example, tetramethylammonium-hydroxide (TMAH) can be used to etch the unreacted silicon with very little etching of SiO₂, Si₃N₄ and most silicides.

The remaining processing steps of the present invention are shown in FIGS. 18 and 19. Specifically, a dielectric film 220 is blanket deposited over the structure and planarized. A second dielectric film 221 is deposited over the planarized dielectric film 220, and via holes are made to the base, emitter and collector (not shown). The via holes are filled with metal 222 such as W, Cu, Al, or CuAl to form contacts to the device.

While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. A heterojunction bipolar transistor (HBT) comprising: a stack including, from top to bottom, an emitter, a base and a collector;an extrinsic base adjacent to said base wherein a lateral dimension of said extrinsic base is defined by the footprint of a sacrificial spacer;a metal-semiconductor alloy region over said extrinsic base; andburied conductive lines connecting to an edge of said metal-semiconductor alloy region.

2. The HBT of claim 1 wherein said metal semiconductor alloy is one of NiSi, CoSi2, and PtSi2.

3. The HBT of claim 1 further comprising an epitaxial layer of a semiconductor located on top of said extrinsic base.

4. The HBT of claim 1 wherein said base comprises SiGe and said extrinsic base comprises SiGe.

5. The HBT of claim 3 wherein said epitaxial layer of a semiconductor comprises epitaxial SiGe.

6. The HBT of claim 1 wherein said buried conductive lines comprise one of Ti, Co, Ni, Pt, W or a metal-semiconductor alloy.

7. The HBT of claim 1 farther comprising a shallow trench isolation region adjacent to said collector, and said buried conductive lines are located over said shallow trench isolation region.

8. A heterojunction bipolar transistor (HBT) comprising: a stack including, from top to bottom, an emitter, a base and a collector;an extrinsic base adjacent to said base wherein lateral dimension of said extrinsic base is defined by the footprint of a sacrificial spacer;a silicide region over said extrinsic base; andburied silicide lines connecting to the edge of said silicide region.

9. The HBT of claim 8 wherein said silicide region is one of NiSi, CoSi2, and PtSi2.

10. The HBT of claim 8 wherein said buried silicide lines are one of NiSi, CoSi2, and PtSi2.

11. The HBT of claim 8 further comprising an epitaxial layer of a semiconductor located on top of said extrinsic base.

12. The HBT of claim 8 wherein said base comprises SiGe and said extrinsic base comprises SiGe.

13. The HBT of claim 11 wherein said epitaxial layer of a semiconductor comprises epitaxial SiGe.

14. The HBT of claim 8 further comprising a shallow trench isolation region adjacent to said collector, and said buried silicide lines are located over said shallow trench isolation region.

15. A method of forming a heterojunction bipolar transistor (HBT) comprising: forming a collector region isolated by a shallow trench isolation (STI) oxide;forming a base layer over the collector and said STI oxide, wherein the base layer is single-crystalline over the collector and poly-crystalline over the STI oxide;forming an emitter over said base layer, wherein said emitter is fully enclosed within said collector region;forming oxide sidewall spacers over said emitter sidewalls;forming sacrificial sidewalls spacers adjacent to said emitter;defining an extrinsic base region by etching unmasked regions of said base layer;forming a planarizing first dielectric;recessing said first dielectric below an upper surface of said emitter;removing said sacrificial sidewall spacers to expose an upper surface of said extrinsic base region;depositing a metal and reacting said metal to form a metal-semiconductor alloy;depositing a second dielectric over said metal and said metal-semiconductor alloy and planarizing second dielectric by chemical mechanical polishing; andetching selectively said metal over said oxide sidewall spacers.

16. The method of claim 15 further comprising forming vias to said metal covered by second dielectric.

17. The method of claim 15 further comprising thickening said extrinsic base region by selective epitaxy.

18. The method of claim 15 comprising removing said second dielectric to expose said metal and converting said exposed metal to a metal-semiconductor alloy.

19. The method of claim 15 wherein said metal covered by said second dielectric comprises one of Ti, Co, Ni, Pt and W.

20. The method of claim 16 wherein said selective epitaxy comprises growing SiGe.