The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor wafers with a backside sub-collector contact and methods of manufacture.
A heterojunction bipolar transistor (HBT) is a type of bipolar junction transistor (BJT) which uses differing semiconductor materials for the emitter and base regions or collector and base regions, creating a heterojunction. The HBT can handle signals of very high frequencies, up to several hundred GHz. The HBT is commonly used in ultrafast circuits, mostly radio frequency (RF) systems, and in applications requiring a high power efficiency, such as RF power amplifiers in cellular phones due to good RF performance, high breakdown voltage and integration with CMOS devices. SiGe HBT devices have a higher power dissipation and combining them into a 3D process results in degradation of performance due to excessive self-heating.
In an aspect of the disclosure, a structure comprises: a first chiplet comprising a first device with a backside contact; and a second chiplet connected to the first chiplet, the second chiplet comprising a second device with a frontside contact.
In an aspect of the disclosure, a structure comprises: a first chiplet comprising a heterojunction bipolar transistor, the heterojunction bipolar transistor comprising a sub-collector, a collector, a base and an emitter; a backside contact directly contacting to the sub-collector; and a second chiplet connected to the first chiplet, the second chiplet comprising a CMOS device with a frontside contact connecting to the heterojunction bipolar transistor.
In an aspect of the disclosure, a method comprises: forming a first chiplet comprising a first device with a backside contact; and forming a second chiplet connected to the first chiplet, the second chiplet comprising a second device with a frontside contact.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor wafers with a backside sub-collector contact and methods of manufacture. In embodiments, the heterojunction bipolar transistor wafers with the backside sub-collector contact can be bonded to a CMOS wafer. Advantageously, the heterojunction bipolar transistor wafers with the backside sub-collector contact provide reduced self-heating, lower Ccb (collector to base capacitance) and lower Rc (collector resistance), in addition to a reduced chip area. In addition, the heterojunction bipolar transistor wafers provide a simplified process of manufacture, e.g., reduces masking steps.
In more specific embodiments, an HBT chiplet (wafer) may be bonded to a CMOS chiplet. A sub-collector of the HBT chiplet directly connects to a backside metal using a bottom contact through, for example, an insulator layer, e.g., buried oxide, and passivation layer. In embodiments, a width of each of the emitter, collector and sub-collector is less than the width of the base region, e.g., intrinsic base and extrinsic base. An interconnect may be coupled to the emitter and/or base with the interconnect coupled to a backside metal.
The structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material layers as is known in the art.
More specifically, the bottom wafer (e.g., chiplet) 12 comprises a transistor 16 formed on semiconductor on insulator (SOI) substrate 30, as an example. In embodiments, SOI substrate 30, from bottom to top, may include a handle substrate 30a, a buried insulator layer 30b, and a top semiconductor layer 30c. The handle substrate 30a and top semiconductor layer 30c may include a semiconductor material such as, for example, Si, Ge, SiGe, SiC, SiGeC, a III-V compound semiconductor, a II-VI compound semiconductor or any combinations thereof. The top semiconductor layer 30c may comprise any suitable single crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The buried insulator layer 30b may include silicon dioxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof. In embodiments, the buried insulator layer 30b may be a buried oxide (BOX). In embodiments, the bottom wafer 30 may be a bulk silicon.
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As an exemplary explanation of the transistor 16, the gate dielectric material of the transistor 16 may be a low-k or high-k dielectric material e.g., HfO2 Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaALO3, ZrO2, Y2O3, Gd2O3, and combinations thereof. The gate electrode may be, for example, polysilicon material. The sidewall spacers may be an oxide material, nitride material, or combinations thereof. The transistor 16 may also include source and drain regions 16a as is known in the art such that no further explanation is required for a complete understanding of the present disclosure. The transistor 16 including, e.g., source and drain regions 16a, may connect to wiring structures 32 embedded within interlevel dielectric material 34 as is known in the art.
In embodiments, the top wafer may include an HBT 18 comprising the sub-collector 20, a collector 36, a base 38 and an emitter 40. In embodiments, the sub-collector 20 and the collector 36 may be semiconductor material, e.g., Si material and, preferably, N+ doped Si material. The sub-collector 20 may directly connect to a backside metal 22 using a bottom contact 24 passing through the passivation layer 26 and, in embodiments, an insulator layer 28, e.g., buried oxide material. In embodiments, the passivation layer 26 may be nitride material or oxide material. The bottom contact 24 may be, for example, an interconnect structure comprising, for example, tungsten aluminum, TiN, TaN, etc. The base 38, e.g., extrinsic and intrinsic base, may be Si or SiGe material and the emitter 40 may be polysilicon or single crystal silicon material. The backside metal 22 may connect to an I/O port.
In embodiments, the sub-collector 20 and the collector 36 may be formed by an epitaxial growth process. In more specific embodiments, the sub-collector 20 and the collector 36 may be formed by an epitaxial growth process with an in-situ doping. In embodiments, the in-situ doping would use an N+ dopant. In embodiments, the N+ dopant may be, e.g., Arsenic (As), Phosphorus (P) or Antimony (Sb), among other suitable examples. The base 38 may also be formed by an epitaxial growth process using, e.g., Si or SiGe.
The interconnect structure 24 can be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over the passivation layer 26 is exposed to energy (light) and developed utilizing a conventional resist developer to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern from the patterned photoresist layer to form one or more trenches in the passivation layer 26 and insulator layer 28, exposing the backside of the sub-collector 20. Following the resist removal by a conventional oxygen ashing process or other known stripants, conductive material can be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the passivation layer 26 can be removed by conventional chemical mechanical polishing (CMP) processes.
In further embodiments, the emitter 40 and the base 38 may be connected to the CMOS wafer 12 and, preferably, the transistor 16 through the use of the wiring structures 32, 32a. As an example, the wiring structures 32, 32a may be 3D heterogeneously integrated (3DHI) contact structures. The base 38 may also be connected to backside wiring by wiring structures 32b, passing through the passivation layer 26 and the insulator layer 28. The wiring structures 32b may be formed using conventional lithography, etching and deposition processes as described herein. In further embodiments, the width of the emitter 40, collector 36 and sub-collector 20 is less than the width of the base 38, e.g., intrinsic base and extrinsic base. The collector 36 and sub-collector 20 may be surrounded by insulator material 44, e.g., buried oxide material or sidewall spacers; whereas the base 38 and emitter 40 are provided in the interlevel dielectric material 34.
The emitter 40 and the base 38 (and transistor 16 of the CMOS wafer 12) may include silicide contacts 42 connecting to the wiring structures 32, 32a, 32b. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt or titanium, over fully formed and patterned semiconductor material (e.g., transistor 16, source and drain regions 16a, base 38 and emitter 40). After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 42 in the active regions of the device.
In this embodiment, the sub-collector 20 and collector 36 of the HBT structure 18a may be connected to the backside metal 24 by the interconnect 22; whereas the sub-collector 20 and collector 36 of the HBT structure 18b may be connected to the emitter 40 of the HBT structure 18a using frontside wiring structures 34c. In addition, the emitter 40 of the HBT structure 18a may be connected to the sub-collector 20 and collector 36 of the HBT structure 18b; whereas the emitter 40 may be connected to a backside (e.g., I/O port). The HBT structures 18a, 18b can be wired to form a cascode amplifier where structure 18a forms a common base device and 18b forms a common emitter device.
In addition, in this structure 10b, the sub-collector 20 may be formed by a blanket ion implantation process with an n+ dopant in a bulk semiconductor substrate 36a. In addition, the collector 36 may be formed by an epitaxial growth process with an in-situ doping, with isolation regions 44 surrounding the collector 36. Moreover, deep trench isolation structures 50 may be used as a polish stop. The deep trench isolation structures 50 may be filled with high density oxide, as an example.
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The blanket ion implantation process may include introducing a dopant in the bulk substrate 36a. In embodiments, respective patterned implantation masks may be used to define selected areas exposed for the implantations. The implantation mask used to select the exposed area for forming sub-collector 20 is stripped after implantation. The implantation masks may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. Each of the implantation masks has a thickness and stopping power sufficient to block masked areas against receiving a dose of the implanted ions. The collector 36 is doped with p n-type dopants, e.g., Arsenic (As), Phosphorus (P) and Antimony (Sb), among other suitable examples.
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The structures can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.