Claims
- 1. A dual in-line memory module (DIMM) comprising:
- a circuit board; and
- a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,
- wherein said first and second memory bank portions are separately addressable,
- wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and
- wherein said plurality of semiconductor memory chips provide 128M of data storage on the DIMM.
- 2. The DIMM of claim 1, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M.times.4), eight megabit by eight bit (8M.times.8), four megabit by 16 bit (4M.times.16) SDRAM chips and any combination thereof.
- 3. A pair of dual in-line memory modules (DIMMs), each DIMM comprising:
- a circuit board; and
- a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,
- wherein said first and second memory bank portions are separately addressable,
- wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and
- wherein said plurality of semiconductor memory chips provide 256M of data storage on the DIMM pair.
- 4. The DIMM of claim 3, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M.times.4), eight megabit by eight bit (8M.times.8), four megabit by 16 bit (4M.times.16) SDRAM chips and any combination thereof.
- 5. A piggyback dual in-line memory module (DIMM) comprising:
- a circuit board having a piggyback board mounted thereon; and
- a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,
- wherein said first and second memory bank portions are separately addressable,
- wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and
- wherein said plurality of semiconductor memory chips provide 256M of data storage on the piggyback DIMM.
- 6. The DIMM of claim 5, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M.times.4), eight megabit by eight bit (8M.times.8), four megabit by 16 bit (4M.times.16) SDRAM chips and any combination thereof.
- 7. A pair of piggyback dual in-line memory modules (DIMMs), each DIMM comprising:
- a circuit board having a piggyback board mounted thereon; and
- a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,
- wherein said first and second memory bank portions are separately addressable,
- wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and
- wherein said plurality of semiconductor memory chips provide 512M of data storage on the piggyback DIMM pair.
- 8. The DIMM of claim 7, wherein said memory chips are selected from the group consisting of thirty-two megabit by four bit (32M.times.4), sixteen megabit by eight bit (16M.times.8), eight megabit by sixteen bit (8M.times.16) SDRAM chips and any combination thereof.
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of application Ser. No. 08/747,975, filed Nov. 12, 1996, now U.S. Pat. No. 5,790,447, which is a continuation of application Ser. No. 08/440,214, filed May 15, 1995, now abandoned.
This application is related to commonly owned, U.S. patent application Ser. No. 08/747,976, filed Nov. 11, 1997, (now U.S. Pat. No. 5,686,730) which is an FWC of application Ser. No. 08/440,967, filed May 15, 1995, entitled "DIMM Pair with Data Memory and State Memory," which is incorporated herein by reference.
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Continuations (2)
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747975 |
Nov 1996 |
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440214 |
May 1995 |
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